Application of fccube TM Technology to Enable Next Generation Consumer Device

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1 Application of fccube TM Technology to Enable Next Generation Consumer Device by Simon Stacey**, Jonathan Wei** **CSR Nokibul Islam*, Mukul Joshi*, Cory Lindholm*, KeonTaek Kang*, JoungIn Yang*, Gwang Kim* *STATS ChipPAC Copyright Reprinted from 2013 Electronic System Technologies Conference and Exhibition (ESTC ) Proceedings. The material is posted here by permission of the authors and of IPC International, Incorporated. Such permission of the IPC does not in any way imply IPC endorsement of any STATS ChipPAC Ltd s products or services. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 Application of fccube TM Technology to Enable Next Generation Consumer Device Simon Stacey**, Jonathan Wei** **CSR Nokibul Islam*, Mukul Joshi*, Cory Lindholm*, KeonTaek Kang*, JoungIn Yang*, Gwang Kim* *STATS ChipPAC Abstract The rapid growth rate of the commercial GPS/auto infotainment market surprised many across the semiconductor industry. The application space of GPS is no longer limited to simple military navigation, now it is a much more complex and wider application space using modern communication and technology. Flip Chip with Copper Column Bond On Lead (BOL) Enhanced Process (fccube TM ) delivers the cost effective, high performance packaging solution that is required by the industry. Continuous trends in bump pitch reduction, performance improvement and Si node reduction, and the resultant move to ELK dielectrics, have created the need for a robust Flip Chip bump process that is serviced by the copper column technology. Adoption of the copper column in place of flip chip solder bumps has a number of potential benefits including bump pitch reduction and possible substrate design rule relaxation by using wider Line and Space for signal routing in a given design. In addition to the benefits achieved by BOL design, as described above, there are complementary technologies, including MUF (Molded Underfill), that provide additional assembly cost reductions for applicable package types. The manufacturing process DOE for studying the bump height effect and void elimination, along with component level reliability of an fccube TM package using 40nm ELK Si technology for CUF (Capillary Underfill) and MUF are explained in the paper. MUF with full open SR fulfills all package level reliability requirements (JEDEC MSL3) with data passing / exceeding minimum read-points. The designed package currently in HVM has excellent assembly yield and dppm level losses for Opens/Shorts. Smaller form factor flip chip packaging has lead to a reduced bump size and an increased current density. When too great, a high current density combined with Joule heating induces an electromigration failure within the bump structure. Besides various manufacturing issues and remedies to fix them, one of the key reliability concerns is the EM (Electro-Migration) lifetime of copper column bumps with a very small (typical size; ~35um) BOL pad on the substrate. Many researchers have published copper column EM data with SMD pads but no data has been published for the BOL pads failure. In this study, we will investigate the effects of pad type (BOL vs. BOC or SMD pad) on the electro-migration lifetime. The step-by-step package design including the substrate, bump, assembly BOM DOE, reliability, and EM results will be analyzed in the paper. Introduction Consumer product differentiation is dominated by the end user experience and the expectation is for a simple user interface with intuitive navigation and controls combined with rich graphics and outstanding audio quality. This is driving the need for faster processors combined with integrated control of peripherals, e.g. touch screen controllers, multimedia decoders etc. As consumer products continues their advancement into the faster demanding digital market, the complexity of the device increases exponentially. Package solutions become very challenging to deliver cleaner power to the device, provide enough I/Os to accommodate the volume of a high speed consumer device and still satisfy all other requirements without compromising reliability and/or cost. In order to bundle this much functionality into a single piece of 40nm silicon requires a large interconnect gap between the silicon and the system PCB to be bridged Adoption of a Cu column in place of flip chip solder bumps has number of potential benefits including bump pitch reduction, possible design

3 rule relaxation by using wider line and space for signal routing in a given design, removal of tight solder registration, and the removal of Solder-On- Pad (SOP) on the substrate, all of which result in a low cost flip-chip package solution. The reduction in pitch capability is simply driven by the fact that bump to bump spacing can be controlled better with finer pitch Cu column as compared to a standard solder bump due to the bump geometry, spherical for solder vs. cylindrical for Cu, in addition to the differences that exist in the bump geometry post reflow process. At the reflow step, solder collapses and an increase in bump diameter is observed, whereas Cu column will not go through such transformation and any dimensional changes. Furthermore the collapse height, which defines the die to substrate gap (stand-off height), can better be controlled by Cu column as the column height can be modulated to provide the required stand-off height without any increase in bump diameter, whereas for solder bump, any increase in stand-off height is associated with the increase in bump diameter. Such an increase in bump diameter is not desirable as it would reduce the bump to bump spacing and hence result in potential bump bridging and electrical shorts. Additionally, the reduced bump to bump spacing would create issues for Capillary Underfill (CUF) flow and lead then to underfill voids. Alternatively, it would create more voiding problem for the Molded Underfill (MUF) process due to a larger filler size used by the MUF material. Peripheral array technology was used in the design. One of the great feature of peripheral array design is it can easily replace legacy wire bond device to flip chip for higher performance which is very common for consumer flip chip applications. In the design, peripheral array bumps were functional and designed with BOL pad whereas no electrical connection with center bumps (i.e; dummy bumps) and were designed to maintain mechanical robustness of the package. Typically a Cu pillar bump has a much higher current carrying capacity than a standard Pb free bump, but in this design of a Cu column attached on a tiny BOL pad on the substrate, it has a higher concern for bump reliability and EM performance. EM tests of the package were conducted with the following Objectives: Develop an empirically validated EM life time prediction model for the fccube interconnect structures used in a package. Through suitable selection of accelerated test conditions, develop an estimate of field life for the device under nominal operating conditions. Develop a guideline/specification for max current per bump (based on the abovedeveloped model) for a specified min field life and junction temp of the device. Develop insight and quantify where possible, the effects of skews in design and material variables such as Si pad design, substrate pad design and bump metallurgy on EM lifetime further assisted by FEA modeling of phenomena such as current crowding. Package Design In this device design, 40nm silicon was used with peripheral array bumps with one trace in 150um pitch, and two traces in 175um bump pitch respectively. Package body size was a 17ⅹ17 mm package with 425 solder balls of 0.35mm diameter and 0.8mm pitch in four layers PTH (Plated Through Hole) substrate. The die size was approximately 5.2 x 5.7 mm. Substrate core material was chosen as Low CTE material to control the package warpage/coplanarity in addition to ELK die protection. The gap between the bump to nearest trace is the key for the fccube design. Too narrow of a gap can cause assembly related issues such as solder bridging, shorting, etc. Bumping process included PI re-passivation, Ti/Cu Under Bump Metallization (UBM), and Cu column plating with a SnAg solder cap on top. As a result of this bumping structure, the peripheral bumps were located on the Al pads while the center mechanical bump array was located on the top passivation layer (no electrical contact). Figure-1 shows the fccube Cu bump and SnAg solder cap along with BOL trace detail for 175um bump pitch design. Overall Cu column and solder cap height were optimized in order to create the optimum stand-off height required for successful CUF/MUF process and ELK die risk mitigation during chip attach and subsequent assembly process.

Figure 1: Bump pattern, and Cu pillar bump dimension detail w/ BOL pad Assembly Process Assembly process includes several design iteration for bump height in order to optimize the CUF/MUF flow

Modified design had 60um pillar height with 35um cap which enables to increase quite a significant gap height.

Significant ELK damage experienced with taller pillar design even it gives better CUF/MUF process. Figure 2 below shows white bump with taller pillar height.

Finally a design with 42um pillar and 35um solder cap with full open SR introduces which maintained smaller bump height to fix the white bump issue on the other hand it increases the gap height

4 Figure 1: Bump pattern, and Cu pillar bump dimension detail w/ BOL pad Assembly Process Assembly process includes several design iteration for bump height in order to optimize the CUF/MUF flow underneath the die. Original design with 42um pillar height with 35um solder cap encountered significant MUF voids. Modified design had 60um pillar height with 35um cap which enables to increase quite a significant gap height. Higher pillar over solder cap ratio increases die level stress results in ELK crack (white bump) during chip attach process. Significant ELK damage experienced with taller pillar design even it gives better CUF/MUF process. Figure 2 below shows white bump with taller pillar height. Extensive simulation has been conducted to understand the safe limit of pillar/solder cap ratio. Finally a design with 42um pillar and 35um solder cap with full open SR introduces which maintained smaller bump height to fix the white bump issue on the other hand it increases the gap height significantly for void free MUF process. were fully optimized for assembly. The critical areas in assembly process were identified as chip attach, molding, and ball mount processes. Additionally, an optimum amount of flux is needed in the chip attach process to make a good joint of very fine size/pitch Cu pillar. Die placement also plays a crucial role; if by any means the dies are misaligned solder bridging, non-wet, etc. might occurred in the chip attach process. Another important concern is white bump (bump delamination) for low K /ELK die. The White bump risk is much lower with the BOL pad vs. BOC type pad. Having a smaller BOL pad helps to resolve the die level stress during chip attach process by shifting the stress from die side to substrate side. Figure 2: white bump w/ taller bump (left picture), and no white bump w/ smaller bump (right picture) The detail assembly process (shown in Figure 3) includes Flip Chip Attach, Under-filling, Overmold, Ball Attach process, and Singulation Figure 3: Typical Assembly Process Flow (Molded Package) MUF process characterization focused on void free molding underneath the die. In this study void free MUF was one of the biggest challenges due to a finer diameter and a smaller gap height pillar. Moreover, MUF filler size is much coarser than CUF which makes the challenge even bigger. Now there are some finer filler MUF available in the market but not yet preferred for a cost sensitive

package. Several iterations such as fine filler, taller bump height, and two step height solder resist, and an open solder resist under the die were done to fix the voiding issue.

Figure 4 shows MUF CSAM Void pictures with and without Full-Open Solder Resist design substrates. Electrical open short tests were performed on every part after every read-point.

Extensive failure analyses were conducted on post reliability TCB parts to see bump crack or other oddities in the package. Cu pillar bump X-section picture is shown in Figure 5.

5 package. Several iterations such as fine filler, taller bump height, and two step height solder resist, and an open solder resist under the die were done to fix the voiding issue. Comprehensive hammer test, MRT, and temperature cycles were conducted to authenticate void free design and process. Figure 4 shows MUF CSAM Void pictures with and without Full-Open Solder Resist design substrates. Electrical open short tests were performed on every part after every read-point. No failure or other degradation was observed in any of qualification samples. Extensive failure analyses were conducted on post reliability TCB parts to see bump crack or other oddities in the package. Cu pillar bump X-section picture is shown in Figure 5. Fully assembled package coplanarity/warpage also was measured to make sure it meets the requirement. Figure 4: MUF void study with 2-Step vs. Full Open S/R Qualification Build: The leg with the best result (Full Open S/R) from the characterization build was selected for comprehensive package level qualification. Packages were built with standard sample size and lot size. No noticeable issues were encountered in the package assembly process. CSAM results were taken on every part after the MUF cure process to make sure no MUF voids or delamination detected in the CSAM pictures. Typical standard package level post reliability requirements were maintained in the qualification build. JEDEC standard package level reliability tests such as MSL-3 (30 C, 60% RH, and 192 hours) w/ 3X reflow, uhast (130 C, and 85% RH, 192 hours), TCB (-55 C to 125 C, 30 minute a cycle), HTS (125 C), etc. were performed extensively on qualification lots. The detailed test matrix with sample size for the package level qualification build is shown in Table 1. Table 1: Package Level Reliability Data Figure 5: Bump x-section of a Full-Open S/R Package Electro-Migration Analysis To drive down the bump count and, hence, the pitch requirements the IO are multiplexed as far as possible. The only remaining opportunity for bump reduction is to combine power and ground pins but key to this is the long term EM reliability of the interconnect. If the EM reliability can be improved then the maximum allowable current per bump can be increased therefore permitting further reduction of power and ground pins. A motivation of fine pitch Cu pillar is to improve the EM performance of the device due to higher device current. Bump level EM tests were performed both at in-house and 3 rd party vendor. EM test vehicle body size, die size, and bump structures were very similar to actual product. Current flow in and out direction (current push through three bumps and out one bump and vice versa) are designed in such a way so both die side and substrate side failure can be captured in actual EM test. Figure 6 below shows the typical EM bump schematic for three to one current flow condition. A dummy bump is attached between the functional bump to mimic the actual bump pattern in the product, moreover dummy bumps help to normalize the joule heating effect during EM test.

Figure 6: Typical EM Bump Schematic for 3 to 1 Current Flow Condition Actual electro-migration tests have been conducted both at in-house lab, and 3 rd party vendor.

Solder caps are 35um with 3 um thin Ni barriers between solder caps to Cu pillar. EM TV is very similar to actual product with 17X17mm body, 4layer substrates with Cu OSP finish.

In order to create a Black s model fit at least combination of five legs were used in the study. The DUTs (device under test) are being tested at constant current and temperature conditions.

Joule heating increases with stress current conditions (higher joule heating with higher stress current).

6 Figure 6: Typical EM Bump Schematic for 3 to 1 Current Flow Condition Actual electro-migration tests have been conducted both at in-house lab, and 3 rd party vendor. Harsher condition legs were considered in 3 rd party vendor DOE than in house DOEs. Test matrix DOE is shown in Table 2 below. All samples have Cu pillar with 80um diameter, and 52um gap height. Solder caps are 35um with 3 um thin Ni barriers between solder caps to Cu pillar. EM TV is very similar to actual product with 17X17mm body, 4layer substrates with Cu OSP finish. Effect of current flow in the bump in and out direction (3 in 1 out vs. 1 in 3 out), BOL vs. BOC (bond on capture pad shown in Figure 7 below) pad, were also considered in the DOE matrix. In order to create a Black s model fit at least combination of five legs were used in the study. The DUTs (device under test) are being tested at constant current and temperature conditions. Table 2: EM Test DOE Figure 7: fccube w/ BOL vs. BOC (SMD) Pad The increase of device temperature due to stress current called Joule heating is calculated in the study. Joule heating increases with stress current conditions (higher joule heating with higher stress current). Temperature Coefficient of Resistance (TCR) was also calculated for each current and temperature condition. Various DUTs with different stress currents were tested at the same oven temperature; due to Joule heating oven temperatures were adjusted accordingly to get an average DUT temperature. Max Joule heating of C was calculated from the highest current and temperature leg (leg#5). TCR for leg#5 along with Joule heating number is shown in Figure 8. Figure 8: Resistance vs. Temperature for Leg#5 EM Results As of today up to 4000 hours testing has been completed without a single failure. The failure criterion is 10% resistance change from initial resistance value, however some minor shifting (<4%) of the resistance values was observed in all the legs in the DOE. The higher resistance shift observed was with higher current and temperature conditions as shown in Figure 9 (a), and (b) respectively. Resistance shift of each leg were monitored and analyzed. Based on early resistance shift data, almost no effect has been found between BOL and BOC pad, nor for 3 to 1 vs. 1 to 3 current flow patterns. Early EM data indicates significantly better EM life with fccube bump even with very small BOL pad. Our goal is to continue testing at least 7000 hours or more to get adequate amount of failure data so Black s equation can be constructed as a tool for future package design optimization.

7 Figure 9 (a): For a Given Current, Stress Resistance Shift Increases with Temperature Figure 9 (b): For a Given Temperature, Resistance Shift Increases with Stress Current Conclusions Continuous trends in bump pitch reduction, performance improvement and Si node reduction, and the resultant move to ELK dielectrics, have created the need for a robust Flip Chip bump process that is serviced by the copper column technology (fccube). The fine pitch fccube technology evaluation for low cost consumer package has proved that the technology is very robust for assembly and performs exceptionally well through all critical JEDEC level reliability, and high current EM testing. The designed package currently in HVM has excellent assembly yield and dppm level losses for Opens/Shorts. Furthermore, the fccube technology will extend beyond consumer markets as the SoCs undergo various application environments including rigorous automotive qualification program. Further enhancements to the technology are being developed to cost optimize thermal and electrical performance with the potential for adoption at 28nm and beyond. Future Work Currently the EM test is ongoing and our plan is to continue the EM tests till we get adequate failure to construct the Black s model. Comprehensive failure analysis will be conducted to identify the failure model. Will develop insight and quantify where possible, the effects of skews in design and material variables such as Si pad design, substrate pad design and bump metallurgy on EM lifetime further assisted by FEA modeling of phenomena such as current crowding. Acknowledgments The authors would like to thank CSR team (Ian Talbot), and Dr. Raj Pendse of STATSChipPAC for their continued guidance in the study. The authors want to express gratitude to the individuals at our partner companies that helped design the advanced packages; including actual EM tests. References [1]Yasumitsu Orii et al, Electromigration Analysis of Peripheral Ultra Fine Pitch C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump, Electronic Components and Technology Conference, ECTC st, Lake Buena Vista, Florida, pp , May 31 st June 1st, 2011 [2]Hamid Eslampour et al, Low Cost Cu Column fcpop Technology, Electronic Components and Technology Conference, ECTC nd, San Diego, CA, pp , May 29 th -June 1 st, 2012 [3]US Patent# US , US Bump-onlead flip chip interconnection, Raj Pendse, Nov [4]Ahmer Syed et al, Flip Chip Bump Electromigration Reliability: A Comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures, IMAPS Device Packaging Conference 2010, Scottsdale, AZ, pp , March 9-11, 2010 [5] JH Yoo et al, Analysis of Electromigration for Cu Pillar Bump in Flip Chip Package, Electronics Packaging Technology Conference, EPTC th, Singapore, pp , December 8-10 th, 2010.

Electromigration for Advanced Cu Interconnect and the Challenges with Reduced Pitch Bumps

Electromigration for Advanced Interconnect and the Challenges with Reduced Pitch Bumps by Nokibul Islam, Gwang Kim, KyungOe Kim STATS ChipPAC Copyright 2014. Reprinted from 2014 Electronic Components and