CS250 VLSI Systems Design

Transcription

1 CS250 VLSI Systems Design Lecture 4: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing Spring 2016 John Wawrzynek with Chris Yarp (GSI) Lecture 04, Timing CS250, UC Berkeley Sp16

2 What do Computer Architects need to know about physics? Physics effect: Area cost Delay performance Energy performance & cost Ideally, zero delay, area, and energy However, the physical devices occupy area, take time, and consume energy CMOS process lets us build transistors, wires, connections, and we get capacitors, inductors, and resistors whether or not we want them Lecture 04, Timing 2 CS250, UC Berkeley Sp16

3 Physical Layout Switch-level abstraction gives a good way to understand the function of a circuit nfet (g=1? short circuit : open) pfet (g=0? short circuit : open) Understanding delay means going below the switch-level abstraction to transistor physics and layout details Lecture 04, Timing 3 CS250, UC Berkeley Sp16

4 Models should be as simple as possible, but no simpler Albert Einstein Lecture 04, Timing 4 CS250, UC Berkeley Sp16

5 Gate Delay Modern CMOS gate delays on the order of a few picoseconds (However, highly dependent on gate context) Often expressed as FO4 delays (fan-out of 4) - as a process independent delay metric: the delay of an inverter, driven by an inverter 4x smaller than itself, and driving an inverter 4x larger than itself For a 90nm process FO4 is around 20ps Should be less than 10ps for our 32nm process Lecture 04, Timing 5 CS250, UC Berkeley Sp16

6 Path Delay For correct operation: Total Delay clock_period - FFsetup_time - FFclk_to_q - Clock_skew on all paths High-speed processors critical paths have around 20 FO4 delays Lecture 04, Timing 6 CS250, UC Berkeley Sp16

7 FO4 Delays per clock period FO4 Delays CPU Clock Periods intel intel 486 intel pentium MIPS stages intel pentium 2 intel pentium 3 intel pentium 4 intel itanium Alpha Pentium Pro 10 stages Alpha Alpha Sparc Historical limit: about Pentium 4 20 stages SuperSparc Sparc64 Mips HP PA Power PC AMD K6 AMD K7 AMD x Thanks to Francois Labonte, Stanford 7 Lecture 04, Timing CS250, UC Berkeley Sp16

8 CPU DB: Recording Microprocessor History With this open database, you can mine microprocessor trends over the past 40 years Andrew Danowitz, Kyle Kelley, James Mao, John P Stevenson, Mark Horowitz, Stanford University F04 Delays Per Cycle for Processor Designs F04 / cycle FO4 delay per cycle is roughly proportional to the amount of computation completed per cycle

9 Gate Delay What determines the actual delay of a logic gate? Transistors are not perfect switches - cannot change terminal voltages instantaneously Consider the NAND gate: Current (I) value depends on: process parameters, transistor size CL / I CL models gate output, wire, inputs to next stage (Cap of Load) C integrates I creating a voltage change at output Lecture 04, Timing 9 CS250, UC Berkeley Sp16

10 More on transistor Current Transistors act like a cross between a resistor and current source ISAT depends on process parameters (higher for nfets than for pfets) and transistor size (layout): ISAT W/L Lecture 04, Timing 10 CS250, UC Berkeley Sp16

11 Transistors as water valves (Cartoon physics) If electrons are water molecules, transistor strengths (W/L) are pipe diameters, and capacitors are buckets Vdd 1 A on p-fet fills up the capacitor with charge Open Charge 0 Water level Time Vdd Vdd 1 A on n-fet empties the bucket Open Out CS 250 L4: Timing Discharge n This model is often good enough 0 Time Water level UC Regents Spring 2016 UCB

12 More on CL Everything that connects to the output of a logic gate (or transistor) contributes capacitance: I Transistor drains Interconnection (wires/ contacts/vias) Transistor Gates Lecture 04, Timing 12 CS250, UC Berkeley Sp16

13 What is the bucket? A gate s fan-out Inverter: NAND gate: Fan-out : The number of gate inputs driven by a gate s output Driving other gates slows a gate down Driving wires slows a gate down Driving it s own parasitics slows a gate down CS 250 L4: Timing UC Regents Spring 2016 UCB

14 A closer look at fan-out Driving more gates adds delay Linear model works for reasonable fan-out 05ns Out: Low -> High Slope = 00021ns / ff FO4: Fanout of four delay CS 250 L4: Timing Delay time of an inverter driving 4 inverters Cout UC Regents Spring 2016 UCB

15 Wires So far, simple capacitors: C Area = width length Wires have finite resistance, so have distributed R and C: with r = res/length, c = cap/length, rcl 2 rc + 2rc +3rc + v1 v2 v3 v4 v1 v2 v3 v4 time Lecture 04, Timing 15 CS250, UC Berkeley Sp16

16 Wires For short wires (between gates) R is insignificant: (total wire RC delay << total gate delay) For long wires R becomes significant Ex: busses, clocks, reset rebuffering helps Finding the correct number and spacing requires solving a quadratic optimization problem Tradeoff fixed delay (overhead) of buffers with RC wire delay Lecture 04, Timing 16 CS250, UC Berkeley Sp16

17 Turning Rise/Fall Delay into Gate Delay Cascaded gates: transfer curve for inverter Lecture 04, Timing 17 CS250, UC Berkeley Sp16

18 Driving Large Loads Large fanout nets: clocks, resets, memory bit lines, off-chip Relatively small driver results in long rise time (and thus large gate delay) Strategy: Staged Buffers Optimal trade-off between delay per stage and total number of stages fanout of 4-6 per stage Lecture 04, Timing 18 CS250, UC Berkeley Sp16

19 Recall: Positive edge-triggered flip-flop D Q A flip-flop samples right before the edge, and then holds value clk Sampling circuit clk Holds value clk clk clk clk clk Clock to Q delay results fr 16 Transistors: Makes an SRAM look compact! What do we get for the 10 extra transistors? Clocked logic semantics clk CS 250 L4: Timing UC Regents Spring 2016 UCB

20 Sensing: When clock is low D Q A flip-flop samples right before the edge, and then holds value clk Sampling circuit clk Holds value clk clk clk clk clk = 0 clk = 1 clk clk Clock to Q delay results fr clk clk clk clk clk clk CS 250 L4: Timing Will capture new clk value on posedge Clock to Q delay results fr Outputs last clk value captured UC Regents Spring 2016 UCB

21 Capture: When clock goes high D Q A flip-flop samples right before the edge, and then holds value clk Sampling circuit clk Holds value clk clk clk clk clk = 1 clk = 0 clk Clock to clk Q delay results fr clk clk clk clk clk clk CS 250 L4: Timing Remembers value clk just captured Clock to Q delay results fr Outputs value clk just captured UC Regents Spring 2016 UCB

22 Flip Flop delays: clk-to-q? setup? hold? clk clk D Q CLK clk clk clk clk CLK == 0 Sense D, but Q outputs old value clk Clock to Q delay results fr setup clk CLK 0->1 Capture D, pass value to Q hold? clk-to-q CS 250 L4: Timing UC Regents Spring 2016 UCB

23 Timing Analysis and Logic Delay Register: An Array of Flip-Flops Combinational Logic If our clock period T > worst-case delay through CL, does this ensure correct operation? CS 250 L4: Timing UC Regents Spring 2016 UCB

24 Flip-Flop delays eat into time budget Combinational Logic ALU time budget T! # clk"q + # CL + # setup CS 250 L4: Timing UC Regents Spring 2016 UCB

25 Clock skew also eats into time budget CLKd CLK CLK CLK CLKd CLK CL As T 0, which circuit fails first? CL CLK CLK CLKd clock skew, delay in distribution T " T CL +T setup +T clk!q + worst case skew ost modern large high-performance chi CS 250 L4: Timing UC Regents Spring 2016 UCB

26 Grid Tuned sector trees Delay Delay Sector buffers x CS 250 L3: Timing Clock Tree Delays, IBM Power CPU y Buffer level 2 Buffer level 1 UC Regents Fall 2013 UCB

27 15 Delay Volts (V) ps skew Time (ps) Multiplefingered transmissio line x CS 250 L3: Timing Clock Tree Delays, IBM Power y UC Regents Fall 2013 UCB

28 Components of Path Delay # of levels of logic Internal cell delay wire delay cell input capacitance cell fanout cell output drive strength Lecture 04, Timing 28 CS250, UC Berkeley Sp16

29 Who controls the delay? foundary engineer (TSMC) Library Developer (Aritsan) CAD Tools (DC, IC Compiler) Designer (Chris) 1 # of levels synthesis RTL 2 Internal cell delay physical parameters cell topology, trans sizing cell selection 3 Wire delay physical parameters place & route layout generator 4 Cell input capacitance physical parameters cell topology, trans sizing cell selection instantiation 5 Cell fanout synthesis RTL 6 Cell drive strength physical parameters transistor sizing cell selection instantiation Lecture 04, Timing 29 CS250, UC Berkeley Sp16

30 From Delay Models to Timing Analysis clk Timing Analysis What is the smallest T that produces correct operation? Or, can we meet a target T? f T 1 MHz 1 μs 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns CS 250 L4: Timing UC Regents Spring 2016 UCB

31 Timing Closure: Searching for and beating down the critical path? Must consider all connected register pairs, paths, plus from input to register, plus register to output Design tools help in the search Synthesis tools work to meet clock constraint, report delays on paths, Special static timing analyzers accept a design netlist and report path delays, and, of course, simulators can be used to determine timing performance Tools that are expected to do something about the timing behavior (such as synthesizers), also include provisions for specifying input arrival times (relative to the clock), and output requirements (set-up times of next stage)

32 Timing Analysis, real example The critical path Most paths have hundreds of picoseconds to spare Late-mode timing checks (thousands) Timing slack (ps) From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al

33 Timing Optimization As an ASIC designer you get to choose: The algorithm The Microarchitecture (block diagram) The RTL description of the CL blocks (number of levels of logic) Where to place registers and memory (the pipelining) Overall floorplan and relative placement of blocks

34 How to retime logic Critical path is 5 We want to improve it without changing circuit semantics IN Circles are combinational logic, labelled with delays OUT Figure 1: A small graph before retiming The nodes represent logic delays, with the inputs and outputs passing through mandatory, fixed registers The critical path is 5 Add a register, move one circle Performance improves by 20% IN OUT Figure 2: The example in Figure 2 after retiming The critical path is reduced from 5 to 4 Post-Placement C-slow Retiming for the Xilinx Virtex FPGA Technology X can do this in simple cases Nicholas Weaver UC Berkeley Berkeley, CA Yury Markovskiy UC Berkeley Berkeley, CA Yatish Patel UC Berkeley Berkeley, CA John Wawrzynek UC Berkeley Berkeley, CA

35 Power 4: Timing Estimation, Closure Timing Estimation Predicting a processor s clock rate early in the project From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al CS 250 L4: Timing UC Regents Spring 2016 UCB

36 Power 4: Timing Estimation, Closure Timing Closure Meeting (or exceeding!) the timing estimate From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al CS 250 L4: Timing UC Regents Spring 2016 UCB

37 Floorplaning: essential to meet timing CS 250 L4: Timing (Intel XScale 80200) UC Regents Spring 2016 UCB

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39 Timing Analysis Tools Static Timing Analysis: Tools use delay models for gates and interconnect Traces through circuit paths Cell delay model capture For each input/output pair, internal delay (output load independent) output dependent delay Standalone tools (PrimeTime) and part of logic synthesis Back-annotation takes information from results of place and route to improve accuracy of timing analysis DC in topographical mode uses preliminary layout information to model interconnect parasitics Prior versions used a simple fan-out model of gate loading delay output load Lecture 04, Timing 39 CS250, UC Berkeley Sp16

40 clk Hold-time Violations d FF q Lecture 04, Timing Some state elements have positive hold time requirements How can this be? Fast paths from one state element to the next can create a violation (Think about shift registers!) CAD tools do their best to fix violations by inserting delay (buffers) Of course, if the path is delayed too much, then cycle time suffers Difficult because buffer insertion changes layout, which changes path delay 40 CS250, UC Berkeley Sp16

41 26 Billion Moore s Law 1 Million Synchronous logic on a single clock domain is not practical for a 26 billion transistor design 2 Thousand

42 GALS: Globally Asynchronous, Locally Synchronous Synchronous modules typically 50K-1M gates, so that the synchronous logic approach works well without requiring heroics Examples

43 IBM Power 5 CPU - Dynamically Scheduled Program counter Instruction cache Instruction translation Alternate Branch history tables Instruction buffer 0 Instruction buffer 1 Branch prediction Return stack Thread priority Target cache Group formation Instruction decode Dispatch Sharedregister mappers Dynamic instruction selection Shared issue queues Read sharedregister files Shared execution units LSU0 FXU0 LSU1 FXU1 FPU0 FPU1 BXU CRL Write sharedregister files Data Translation Group completion Data translation Data Cache Store queue Data cache L2 cache Shared by two threads Thread 0 resources Thread 1 resources Stars denote FIFOs that create separate synchronous domains An example of how architecture and circuits work together

44 Rocket uses GALS for accelerator interface Your project interfaces with the RISC-V pipeline and the memory system using FIFOs Your timing closure is independent of the CPU logic domain

45 Conclusion Timing Optimization: You start with a target on clock period What control do you have? Biggest effect is RTL manipulation ie, how much logic to put in each pipeline stage We will be talking later about how to manipulate RTL for better timing results In most cases, the tools will do a good job at logic/ circuit level: Logic level manipulation Transistor sizing Buffer insertion But some cases may be difficult and you may need to help Lecture 04, Timing 45 CS250, UC Berkeley Sp16

46 End of Physical Realities part 1 Timing Lecture 04, Timing 46 CS250, UC Berkeley Sp16

47 Simple exercises for gaining intuition about timing for your process + EDA tools Thanks to Bhupesh Dasila, Open-Silicon Bangalore

48 Synthesize gate chains using hand-specified library cells Exercises cell library and place and route tools weak NANDs 40 nm process 29 ps/gate av Synthesis constrained to 2ns clock Lets you know how many levels of logic you can use in the best case Delay of a chain of 3 inverters with strongest strength Guaranteed not to exceed speed Chain lengths Helps you see through Technology X Bhupesh Dasila

49 Force P&L to drive a long wire with a known buffer cell Bhupesh Dasila Vary driver strength, wire length, metal layer Distributed RC is the Shows the square of maximum the length distance two is clearly gates can be seen! placed and still meet your clock period

50 Driving Large Loads Large fanout nets: clocks, resets, memory bit lines, off-chip Relatively small driver results in long rise time (and thus large gate delay) Strategy: Staged Buffers Optimal trade-off between delay per stage and total number of stages fanout of 4-6 per stage Lecture 04, Timing CS 250 L3: Timing UC CS250, Regents UC Fall Berkeley 2013 Fall UCB 12 12

51 Register file: Synthesize, or use SRAM? sel(ws) 5 WE D E M U X clk wd R0 - The constant 0 Q 32 D D D En En En R1 R2 R31 Q Q Q Speed will depend on how large it lays out two read ports sel(rs1) M U X M U X 5 32 rd1 sel(rs2) 5 32 rd2 CS 250 L4: Timing UC Regents Spring 2016 UCB

52 Synthesized, custom, and SRAM-based register files, 40nm For small register files, logic synthesis is competitive Synthesis Not clear if the SRAM data points include area for register control, etc SRAMS Register file compiler Figure 3: Using the raw area data, the physical implementation team can get a more accurate area estimation early in the RTL development stage for floorplanning purposes This shows an example of this graph for a 1-port, 32-bit-wide SRAM Bhupesh Dasila

53 Today: Timing insights for your project What we re not doing If this class was EE 241 and your project was an SRAM: You could see through down to the layout Timing? Use SPICE on this hand-drawn schematic

54 Technology X: The CS 250 timing challenge What we are doing ---> If your accelerator is too slow two options: Top-down: Rework high-level micro-architecture Let Technology X keep its job Today Bottom-up: Take control away from logic synthesis Use HDL as textual schematic Also, use command-line tool flags Logic Synthesis Sometimes necessary Ben is the expert, ask in discussion section