Systems I. Pipelining I. Topics Pipelining principles Pipeline overheads Pipeline registers and stages
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1 Systms I Piplinin I Topics Piplinin principls Piplin ovrhads Piplin ristrs and stas
2 Ovrviw What s wron with th squntial (SEQ) Y86? It s slow! Each pic of hardwar is usd only a small fraction of tim W would lik to find a way to t mor prformanc with only a littl mor hardwar Gnral Principls of Piplinin Goal Difficultis Cratin a Piplind Y86 Procssor arranin SEQ Insrtin piplin ristrs Problms with data and control hazards 2
3 al-world Piplins: Car Washs Squntial Paralll Piplind Ida Divid procss into indpndnt stas Mov objcts throuh stas in squnc At any ivn tims, multipl objcts bin procssd 3
4 Laundry xampl Ann, Brian, Cathy, Dav ach hav on load of cloths to wash, dry, and fold Washr taks 30 minuts A B C D Dryr taks 30 minuts Foldr taks 30 minuts Stashr taks 30 minuts to put cloths into drawrs Slid courtsy of D. Pattrson 4
5 Squntial Laundry 6 PM AM T a s k O r d r Tim A B C D Squntial laundry taks 8 hours for 4 loads If thy larnd piplinin, how lon would laundry tak? Slid courtsy of D. Pattrson 5
6 Piplind Laundry: Start ASAP T a s k 12 2 AM 6 PM A B C Tim O D r d r Piplind laundry taks 3.5 hours for 4 loads! Slid courtsy of D. Pattrson 6
7 T a s k O r d r Piplinin Lssons 6 PM Tim A B C D Slid courtsy of D. Pattrson Piplinin dosn t hlp latncy of sinl task, it hlps throuhput of ntir workload Multipl tasks opratin simultanously usin diffrnt rsourcs Potntial spdup = Numbr pip stas Piplin rat limitd by slowst piplin sta Unbalancd lnths of pip stas rducs spdup Tim to fill piplin and tim to drain it rducs spdup Stall for Dpndncs 7
8 Latncy and Throuhput Latncy: tim to complt an opration Throuhput: work compltd pr unit tim Considr plumbin Low latncy: turn on fauct and watr coms out Hih bandwidth: lots of watr (.., to fill a pool) What is Hih spd Intrnt? Low latncy: ndd to intractiv amin Hih bandwidth: ndd for downloadin lar fils Marktin dpartmnts lik to conflat latncy and bandwidth 8
9 lationship btwn Latncy and Throuhput Latncy and bandwidth only loosly coupld Hnry Ford: assmbly lins incras bandwidth without rducin latncy My factory taks 1 day to mak a Modl-T ford. But I can start buildin a nw car vry 10 minuts At 24 hrs/day, I can mak 24 * 6 = 144 cars pr day A spcial ordr for 1 rn car, still taks 1 day Throuhput is incrasd, but latncy is not. Latncy rduction is difficult Oftn, on can buy bandwidth E.., mor mmory chips, mor disks, mor computrs Bi srvr farms (.., ool) ar hih bandwidth 9
10 Computational Exampl 300 ps 20 ps Combinational loic Dlay = 320 ps Throuhput = 3.12 GOPS Clock Systm Computation rquirs total of 300 picosconds Additional 20 picosconds to sav rsult in ristr Must hav clock cycl of at last 320 ps 10
11 3-Way Piplind Vrsion 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps loic A loic B loic C Dlay = 360 ps Throuhput = 8.33 GOPS Systm Divid combinational loic into 3 blocks of 100 ps ach Can bin nw opration as soon as prvious on passs throuh sta A. Bin nw opration vry 120 ps Ovrall latncy incrass 360 ps from start to finish Clock 11
12 Piplin Diarams Unpiplind OP1 OP2 OP3 Tim Cannot start nw opration until prvious on complts 3-Way Piplind OP1 OP2 OP3 A B C A B C A B C Tim Up to 3 oprations in procss simultanously 12
13 Opratin a Piplin Clock OP1 OP2 OP3 A B C A B C A B C Tim 100 ps 20 ps 100 ps 20 ps 100 ps 20 ps loic A loic B loic C Clock 13
14 Limitations: Nonuniform Dlays 50 ps 20 ps 150 ps 20 ps 100 ps 20 ps loic A loic B loic C Dlay = 510 ps Throuhput = 5.88 GOPS OP1 OP2 OP3 Clock A B C A B C A B C Tim Throuhput limitd by slowst sta Othr stas sit idl for much of th tim Challnin to partition systm into balancd stas 14
15 Limitations: istr Ovrhad 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps 50 ps 20 ps loic loic loic loic loic loic Clock Dlay = 420 ps, Throuhput = GOPS As try to dpn piplin, ovrhad of loadin ristrs bcoms mor sinificant Prcnta of clock cycl spnt loadin ristr: 1-sta piplin: 6.25% 3-sta piplin: 16.67% 6-sta piplin: 28.57% Hih spds of modrn procssor dsins obtaind throuh vry dp piplinin 15
16 CPU Prformanc Equation 3 componnts to xcution tim: CPU tim = Sconds Proram = Instructions Proram Cycls Instruction Sconds Cycl Factors affctin CPU xcution tim: Inst. Count CPI Clock at Proram X Compilr X (X) Inst. St X X (X) Oranization X X MicroArch X X Tchnoloy X Considr all thr lmnts whn optimizin Workloads chan! 16
17 Cycls Pr Instruction (CPI) Dpnds on th instruction CPI i = Excution tim of instruction i Clock at Avra cycls pr instruction CPI = n i= 1 CPI i F i whr F i = IC IC i tot Exampl: Op Frq Cycls CPI(i) %tim ALU 50% % Load 20% % Stor 10% % Branch 20% % CPI(total)
18 Comparin and Summarizin Prformanc Fair way to summariz prformanc? Captur in a sinl numbr? Exampl: Which of th followin machins is bst? Computr A Computr B Computr C Proram Proram Total Tim
19 Mans Arithmtic man Gomtric man 1 n n i= 1 n Ti i= 1 T i 1 n Can b wihtd: a i T i prsnts total xcution tim Should not b usd for aratin normalizd numbrs Consistnt indpndnt of rfrnc Bst for combinin rsults Bst for normalizd rsults ln( Go) = 1 n n i= 1 ln( T i ) 19
20 What is th omtric man of 2 and 8? A. 5 B. 4 20
21 Is Spd th Last Word in Prformanc? Dpnds on th application! Cost Not just procssor, but othr componnts (i. mmory) Powr consumption Trad powr for prformanc in many applications Capacity Many databas applications ar I/O bound and disk bandwidth is th prcious commodity 21
22 visitin th Prformanc Eqn CPU tim = Sconds Proram = Instructions Proram Cycls Instruction Sconds Cycl Instruction Count: No chan Clock Cycl Tim Improvs by factor of almost N for N-dp piplin Not quit factor of N du to piplin ovrhads Cycls Pr Instruction In idal world, CPI would stay th sam An individual instruction taks N cycls But w hav N instructions in fliht at a tim So - avra CPI pip = CPI no_pip * N/N Thus prformanc can improv by up to factor of N 22
23 Data Dpndncis 1 irmovl $50, %ax 2 addl %ax, %bx 3 mrmovl 100( %bx ), %dx sult from on instruction usd as oprand for anothr ad-aftr-writ (AW) dpndncy Vry common in actual prorams Must mak sur our piplin handls ths proprly Gt corrct rsults Minimiz prformanc impact OP1 OP2 OP3 Tim 23
24 Data Hazards loic A loic B loic C OP1 A B C OP2 A B C OP3 A B C OP4 A B C Tim Clock sult dos not fd back around in tim for nxt opration Piplinin has chand bhavior of systm 24
25 Data Dpndncis in Procssors 1 irmovl $50, %ax 2 addl %ax, %bx 3 mrmovl 100( %bx ), %dx sult from on instruction usd as oprand for anothr ad-aftr-writ (AW) dpndncy Vry common in actual prorams Must mak sur our piplin handls ths proprly Gt corrct rsults Minimiz prformanc impact 25
26 SEQ Hardwar Stas occur in squnc On opration in procss at a tim On sta for ach loical piplin opration Ftch (t nxt instruction from mmory) Dcod (fiur out what instruction dos and t valus from rfil) Excut (comput) Mmory (accss data mmory if ncssary) Writ back (writ any instruction rsult to rfil) PC Mmory Excut Dcod Ftch Bch CC icod ifun ra Mm. control ALU A Instruction mmory PC nwpc Nw PC rb rad writ vale ALU valc Data mmory Addr ALU B valm data out Data valp vala PC incrmnt ALU fun. valb A B M istr fil E dste dstm srca srcb dste dstm srca srcb Writ back 26
27 SEQ+ Hardwar Mmory Mm. control rad writ valm data out Data mmory Still squntial implmntation ordr PC sta to put at binnin Excut Bch CC ALU A vale ALU Addr ALU B Data ALU fun. PC Sta Task is to slct PC for currnt instruction Basd on rsults computd by prvious instruction Dcod icod ifun ra rb valc valp vala valb A B M istr fil E dste dstm srca srcb dste dstm srca srcb Writ back Procssor Stat Ftch Instruction mmory PC incrmnt PC is no lonr stord in ristr But, can dtrmin PC basd on othr stord information PC PC PC picod pbch pvalm pvalc pvalp 27
28 Addin Piplin istrs vale, valm Writ back W_icod, W_valM valm valm W valm W_valE, W_valM, W_dstE, W_dstM Mmory Data mmory Addr, Data Mmory M_icod, M_Bch, M_valA Data mmory Addr, Data vale M Excut Bch CC ALU Excut Bch CC vale ALU alua, alub alua, alub vala, valb E Dcod Ftch icod, valc valp icod, ifun ra, rb valc Instruction mmory srca, srcb dsta, dstb valp PC incrmnt A B M istr fil E Dcod D icod, ifun, ra, rb, valc d_srca, d_srcb vala, valb A B istr M fil E valp valp Writ back PC Ftch Instruction mmory PC incrmnt prdpc PC pstat PC f_pc F 28
29 Piplin Stas Ftch Slct currnt PC ad instruction Comput incrmntd PC Dcod ad proram ristrs Excut Oprat ALU Mmory ad or writ data mmory Writ Back Updat ristr fil Mmory Excut Dcod Ftch PC W_icod, W_valM M_icod, M_Bch, M_valA W M E D icod, ifun, ra, rb, valc F Instruction mmory Addr, Data Bch d_srca, d_srcb valm CC alua, alub Data mmory valp W_valE, W_valM, W_dstE, W_dstM vale ALU vala, valb PC incrmnt f_pc A B istr M fil E valp Writ back prdpc 29
30 Summary Today Piplinin principls (assmbly lin) Ovrhads du to imprfct piplinin Brakin instruction xcution into squnc of stas Nxt Tim Piplinin hardwar: ristrs and fdback paths Difficultis with piplins: hazards Mthod of mitiatin hazards 30
Systems I. Pipelining I. Topics Pipelining principles Pipeline overheads Pipeline registers and stages
Systms I Piplinin I Topics Piplinin principls Piplin ovrhads Piplin ristrs and stas Ovrviw Whatʼs s wron with th squntial (SEQ) Y86? Itʼs slow! Each pic of hardwar is usd only a small fraction of tim W
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