Marwan Adas December 6, 2011
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1 Marwan Adas December 6, 2011
2 SPONGENT A Lighweight hash function SPONGENT = SPONGE + PRESENT + Unkeyed PRESENT- - - type permutation π: 4- bit S- box and bit diffusion Diagrams from
3 SPONGENT Lightweight Cryptography Low area Low power Low energy Low cost Five Main Variants Different levels of security Two Implementation Options Serial : Low- area, low power option Parallel: High throughput option
4 SPONGENT Variants Variant n (bit) b (bit) c (bit) r (bit) R (No. of Rounds) Security ( bit) Pre. 2nd pre. SPONGENT SPONGENT SPONGENT SPONGENT SPONGENT Col.
5 SPONGENT: Serial Implementa6on
6 SPONGENT: Parallel Implementa6on
7 SPONGENT FPGA Implementa6on Parameterized Verilog code Serial Parallel ATHENa Xilinx (Virtex 5 and Spartan 3) Altera (Cyclone III and Stratix III) Golden reference C model Provided by creator of SPONGENT NCSIM from Cadence for simulation Native FPGA vendor tools for area and power analysis Used the a 27 character long phrase for all analysis: SPONGENT = SPONGE + PRESENT
8 Resource U6liza6on: Altera Cyclone III (No. of LEs) LE (serial) LE (Parallel)
9 Resource U6liza6on: Altera Stra6x III (No. of ALUTs) ALUT (serial) ALUT (parallel)
10 Resource U6liza6on: Xilinx Spartan 3 (No. of Slices) Slices (serial) Slices (Parallel)
11 Resource U6liza6on: Xilinx Virtex 5 (No. of Slices) Slices (serial) Slices (Parallel) 0
12 Maximum Throughput: Altera Cyclone III (Mb/s) TP (Serial) (Mb/s) TP (Parallel) (Mb/s)
13 Maximum Throughput: Altera Stra6x III (Mb/s) TP (Serial) TP (Parallel)
14 Maximum Throughput: Xilinx Spartan 3 (Mb/s) TP (Serial) (Mb/s) TP (Parallel) (Mb/s)
15 Maximum Throughput: Xilinx Virtex 5 (Mb/s) TP (Serial) (Mb/s) TP (Parallel) (Mb/s)
16 Power Analysis Uses 100 KHz clock (reasonable for applications targeted by lightweight hash) Altera PowerPlay Analyzer Switching activity (VCD) from RTL simulation annotated to IOs and registers PowerPlay uses vector- less estimation for rest of logic and nets Medium to high confidence Xilinx Xpower Analyzer Switching activity (VCD) from gatelevel simulation
17 SPONGENT: Altera Cyclone III Variant cycles Data path (bits) Area (LEs) Throughput (Kb/s) SPONGENT SPONGENT SPONGENT SPONGENT SPONGENT Power (mw) Power is dominated by leakage power. (leakage ~80%. IOs=~19%, Logic < 1%)
18 SPONGENT: Altera Stra6x III Variant cycles Data path (bits) Area (ALUTs) Throughput (Kb/s) Power (mw) SPONGENT SPONGENT SPONGENT SPONGENT SPONGENT Power is dominated by leakage power. (leakage ~90%. IOs=~9%, Logic < 1%)
19 SPONGENT: Xilinx Spartan 3 Variant cycles Data path (bits) Area (Slices) Throughput (Kb/s) SPONGENT SPONGENT SPONGENT SPONGENT SPONGENT Power (mw) Power is dominated by leakage power. (leakage ~100%. IOs < 1%, Logic < 1%)
20 SPONGENT: Xilinx Virtex 5 Variant cycles Data path (bits) Area (Slices) Throughput (Kb/s) SPONGENT SPONGENT SPONGENT SPONGENT SPONGENT Power (mw) Power is dominated by leakage power. (leakage =~97%. IOs < 1%, Logic =~2%)
21 SPONGENT: Altera Cyclone III at 166MHz Variant cycles Datapath (bits) Area (LEs) TP (Kb/s) Power (mw) Energy mj/kbit SPONGENT- 8 8 SPONGENT SPONGENT SPONGENT SPONGENT
22 Conclusions Serial implementation resulted in smaller area (except for Cyclone III) Smaller logic area (replacing all Sboxes with a single Sbox) Approximately the same number of registers Slightly larger control (larger state machine and counters) Extent of area savings in FPGA- Based serial implementation does not compare to ASIC FPGA architectures are not as granular as ASIC Partial use of the basic unit (slice/alm) counts as using the entire resource (example register) Using same number of registers results in approximately same number of basic units used (Slices/ALMs) Small saving in FPGA resources compared to the large reduction in throughput of the serial implementation.
23 Conclusions (Cont.) At 100 KHz operation, power is dominated by Leakage No power advantage for serial implementation at this frequency. Parallel Implementation leads to lower energy Both implementations have similar power dissipation profile Serial implementation takes longer to complete At higher frequencies, serial implementation leads to a lower power solution suitable for passive devices. The parallel, more energy efficient implementation, are more suitable for active and battery assisted passive device.
24
25 Building Blocks sboxlayer: 4- bit to 4- bit S- box Player: bit permutation Depictions from
26 Back Up Spartan 3 Slices (serial) Slices (Parallel) LUTs (serial) LUTs (paralle) slice US slice UP spongnet % 20% spongnet % 27% spongnet % 34% spongnet spongnet Vertex5 Slices (serial) Slices (Parallel) LUTs (serial) LUTs (paralle) spongnet spongnet spongnet spongnet spongnet
27 Back up Cyclone III LE (serial) LE (Parallel) spongnet spongnet spongnet spongnet spongnet Stra6x III ALUT (serial) Logic U6l (serial) ALUT (parallel) Logic U6l (parallel) spongnet spongnet spongnet spongnet spongnet
28 Back up Stra6xIII serial total dynamic sta6c ios spongnet % 9.00% 0.00% spongnet % 9.00% 0.00% spongnet % 9.00% 0.00% spongnet % 9.00% 0.00% spongnet % 9.00% 0.00% Stra6xIII paralle total dynamic sta6c ios spongnet % 9.04% 0.02% spongnet % 6.96% 0.00% spongnet % 9.17% 0.00% spongnet % 9.17% 0.00% spongnet % 9.17% 0.00%
29 Back up CycloneIII TP (Serial) (Mb/s) TP (Parallel) (Mb/s) maxfreq(seria) maxfreq(parallel) TP/area spongnet spongnet spongnet spongnet spongnet Stra6xIII TP (Serial) TP (Parallel) maxfreq(seria) maxfreq(parallel) spongnet spongnet spongnet spongnet spongnet
30 Back up Spartan 3 TP (Serial) (Mb/s) TP (Parallel) (Mb/s) rounds widths maxfreq (seria) maxfreq(parallel) spongnet spongnet spongnet spongnet spongnet Virtex 5 TP (Serial) (Mb/s) TP (Parallel) (Mb/s) rounds widths maxfreq (seria) maxfreq(parallel) spongnet spongnet spongnet spongnet spongnet
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