Improved Efficiency and Reduced Parasitics with Integrated Power: Comparison of Monolithic and Multi-Chip Hybrid Power Stages

Transcription

1 Improved Efficiency and Reduced Parasitics with Integrated Power: Comparison of Monolithic and Multi-Chip Hybrid Power Stages Volterra Semiconductor: AMD AMD Technology Forum Exhibit

2 Outline Multi-Chip Hybrid are being positioned as Ultimate Power Stages by several vendors However these devices do not eliminate the parasitic elements between power FETs and drivers, which are still present in the package. Stray inductances in Buck converter, their impact on efficiency. Considerations, estimates, references, examples. Experimental comparison of Monolithic and Multi-Chip Hybrid power stages: same design, board, components, layout. General conclusions 2

3 What is a Multi-Chip Hybrid: HS FET + LS FET + Driver LS FET HS FET Driver A multi-chip hybrid is built of several discrete dies copackaged together. This means there are parasitics and inductive current loops between Driver and FETs HS and LS FETs FETs and external components. All of that leads to losses, similar to discrete design case. 3

4 Connected HS FET + LS FET + Driver Current: Source of HS FET to Vsw Current: Driver to HS FET gate HS FET Source Vin Driver LS FET Source CGND Current: Driver Supplies (for LS and HS) PGND Current: GND to Source of LS FET Vsw Current: Driver to LS FET gate 4

5 Main Parasitics in Multi-Chip Hybrids Buck Vo HS FET Source Cin Vin Driver CGND LS FET Source Lo Vo PGND Vsw Co According to different sources, parasitic inductances in MCH are 2-5nH each

6 Impact of Parasitics Long switching time, switching loss Long switching time, switching loss Vo Cin Slow di/td, switching loss, inductance storage loss Lo Vo Long switching time, switching loss Co Eff(Fs1) Parasitics are active and reactive. Both types are associated with losses. Parasitics are around power FETs, and around driver. Reactive slow down the switching, causing extra switching losses. They are also associated with energy storage lost every switching event. Efficiency Long switching time, switching loss Slow di/td, switching loss, inductance storage loss Fs1 Fs

7 GND GND GND GND Vx Vx Vx Vin Vin Vin Vin Footprint for Integrated Power: Layout Added MCH Smallest, 6x6 MCH Smallest, 6x6 Volterra Largest, 5x3.5 1mm 2 Volterra Typical, 5x3.5 All drawings are to one scale. Integrated Power not just smaller and more dense it also means smaller inductance loops in layout around the package. MCH: large package with large copper polygons large layout loops. Volterra: small package with many interleaved polygons 1) small layout loops 2) many small loops in parallel. 7

8 Losses: Reference 1 [1] W. Eberle, Z. Zhang, Y. Liu, P.C. Sen, A Simple Analytical Switching Loss Model for Buck Voltage Regulators, APEC The reference details and explains how parasitics affect the losses, stray inductances in particular. 8

9 Losses: Reference 2 [2] T. Meade, D. O Sullivan, R. Foley, C. Achimescu, M. Egan and P. McCloskey, Parasitic Inductance Effect on Switching Losses for a High Frequency Dc-Dc Converter, APEC The reference details and explains how parasitics affect the losses, especially stray inductances. Smallest parasitic inductances lead to highest efficiency at high frequency. 9

10 Losses: Reference 3 [3] T. Hashimoto, T. Uno, M. Shiraishi, T. Kawashima, N. Akiyama, N. Matsuura, and H. Akagi, A Cu-Plate-Bonded System-in-Package (SiP) With Low Spreading Resistance of Topside Electrodes for Voltage Regulators, IEEE Trans. on Power Electronics, vol. 25, No. 9, September The reference shows and analyzes the improvement of Cu-plate-bounded MCH vs. wire-bounded MCH due to decreased parasitics. 10

11 Some Typical Multi-Chip Hybrids Parameters Typical MCH datasheet: data for large inductor value, low switching frequency, often - no total system loss, often not even efficiency plot (just losses inside the package). Example: Io=30A, Vo=1.3V, Po=39W, Loss=6W. Efficiency=86.7% - with no losses in inductor or layout accounted!

12 Integrated Power LS FET+HS FET+Driver HS FET, LS FET and drivers all together, on the same die, interleaving. Non existent parasitics between components on the die. Minimal parasitics to external components.

13 Ballpark Estimates: Monolithic Power ~0.1mm ~0.2mm PGND Vsw PGND Vsw PGND Vsw Vin Many small loops in parallel, decreasing the total Anything in series with Vsw is irrelevant (in series with main L)! HS FET, LS FET and drivers literally touch each other.

14 Ballpark Estimates: DrMOS, Multichip Hybrid ~0.1mm ~0.2mm LS FET Source ~0.2mm LS FET Drain PGND Vsw Vin HS FET Source HS FET Drain Industry DrMOS PCB Large inductance loops. Wire-bounded Multi-Chip Hybrid is worse.

15 Estimates for Inductive Loops Before Layout ~0.50mm >0.40mm Industry smallest MCH: approximate inductive loop of ~0.50x0.40=0.20mm 2. This is just before layout considerations. ~0.30mm ~0.25mm Integrated Monolithic FcQFN: approximate inductive loops of ~0.3x0.25/2=0.038mm 2. This is just before layout considerations. Plus many such small loops in parallel. >5x smaller inductive loop and therefore smaller stray inductance, as compared to smallest Multi- Chip Hybrid

16 Stray Inductance Considerations Vo Vo Cin Cin Lo Vo Lo Vo Co Co Industry MCH Monolithic FcQFN: >10x smaller parasitics in drivers >5x smaller parasitics in FETs

17 Experimental Comparison 4 phase, integrated VR board with discrete inductors is compared to the same board but with power stages changed to DrMOS (control chip changed as well). Same board, same layout, same copper, same passive components, same efficiency measurements. Different results. 17

18 Efficiency, [%] Peak Efficiency vs. Fs: Measurements Peak Efficiency Comparison: Monolithic vs DrMOS, 4 phase 210nH DL. Highest Peak Efficiency Highest Peak Efficiency Monolithic: Peak Efficiency (Io~50A) DrMOS: Peak Efficiency (Io~50A) 1% Fs. [KHz/Phase] Two identical four phase test boards are used for monolithic and Multi-Chip Hybrid solutions, both with discrete inductors of 210nH. The efficiency drop due to switching frequency increase is much more visible for Multi-Chip Hybrids: due to larger parasitics. 18

19 Loss, Normalized at 250KHz Normalized Losses vs. Fs: Measurements Normalized Loss Comparison: Monolithic vs DrMOS, 4 phase 210nH DL. Monolithic: Normalized Losses (Io~50A) DrMOS: Normalized Losses (Io~50A) Losses are normalized for both solutions (separately) at 250KHz Losses are normalized at 250KHz The loss increase due to switching frequency increase is much more visible for Multi-Chip Hybrids: due to larger internal parasitics Fs. [KHz/Phase] 19

20 Efficiency Efficiency Comparison Monolithic vs Discrete (Vin=12V; Vout=1.2V) PS0 Efficiency Comparison: Monolithic vs Discrete Monolithic has 4% higher efficiency at lighter loads Io Shunt(A) Monolithic has 1% higher efficiency up to ½ of ICCMAX (130W EP) 4ph_VT1676S_600kHz 4ph_Conv_400kHz 4ph_Conv_600KHz Two four phase test boards are used for monolithic and discrete solutions The boards have same size, number of layers and Cu thickness 220nH FP1308 inductors are used for the discrete solution, whereas a 4ph Gen2 CL is used for the Volterra solution Thanks to lower parasitics and reduced switching losses, monolithic approaches offer higher efficiency even while operating at higher frequency Discrete solution experience significant performance degradation when operating at higher fsw due to much larger parasitics 20

21 Thermals Heat to the heatsink Semiconductor die Monolithic FcQFN Heat to the heatsink Plastic Semiconductor die Heat to the heatsink Plastic Semiconductor die Industry MCH Losses do increase in any circuit with increase of switching frequency. Exposed top of the die in Monolithic solution allows direct connection to the heatsink, while plastic package of the Multi-Chip Hybrid creates a high thermal impedance.

22 Summary Efficiency Eff(Fs1) Efficiency Eff(Fs1) Efficiency Eff(Fs1) Fs Fs1 Discrete FETs+Drivers Worst parasitics, slowest practical Fs. ~300KHz typical Fs1 DrMOS Multi-chips Fs Medium parasitics, mid-range practical Fs. ~ KHz typical Fs1 Integrated Power Fs Smallest parasitics, highest practical Fs KHz typical Monolithic solution provides the smallest possible parasitics between FETs, between FETs and external components, and between drivers and power FETs. Smallest parasitics in power stage and drivers decrease the switching transition times (minimum loss associated with overlap of voltage and current) and minimize the losses associated with energy storage in power stage parasitics. Monolithic solutions are the least sensitive to increase of switching frequency, then there are tightly packaged multi-chip hybrids (DrMOS), with discrete solutions (FETs+Drivers) being the worst.