SFM/TFM Power Integrity Guidelines Samtec SFM/TFM Series Measurement and Simulation Data

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1 SFM/TFM Power Integrity Guidelines Samtec SFM/TFM Series Measurement and Simulation Data Scott McMorrow, Director of Engineering Page 1

2 SFM/TFM Power Integrity Guidelines Modeled Section SFM Board TFM Board Power Via Power Via Power Via Power Via SFM Board TFM Board SFM/TFM Power Integrity Guidelines Test and Evaluation System Page 2

3 SFM/TFM Power Integrity Guidelines Test Board Layer Stackup Layer Thickness Cross Section Layer Definition Material Type 0.5 mil Solder Resist 0.8 mil Cu Plating mil Top Pads 1 oz Cu 4 mil FR mil Plane 0.5 oz Cu 49.8 mil Core FR mil Plane 0.5 oz Cu 4 mil FR mil Bottom Pads 1 oz Cu 0.8 mil Cu Plating 0.5 mil Solder Resist 64 mil Finished Thickness Page 3

4 SFM/TFM Power Integrity SFM/TFM Power Integrity Guidelines simulations were performed with Ansoft SiWave, an advanced power integrity simulation environment. SiWave was previously correlated to DC resistance measurements using the HPM/HPF and PES/PET Power Integrity Guidelines test and measurements boards. Such correlation allow high confidence simulations of future power connector systems. Custom power connector and layout configurations can be easily analyzed and compared. Page 4

5 Serial via resistance Power Integrity Guidelines Correlation Test Structures Arrays of 40 vias with 45, 20, 15, 12, and 10 mil finished hole diameter are available for the accurate measurement of average via resistance, with the inclusion of attach traces. Also used for the accurate adjustment of PCB fabrication parameters. Copper thickness Via barrel plating thickness Page 5

6 SFM/TFM Power Integrity Guidelines Documentation Goals Provide Information for : DC characterization of the power blades of the connector system. Include mounted breakout resistivity. Include via resistivity. Correlate simulation to measurements Page 6

Model/Simulator Validation Via test strip contains 40-45 mil vias 39 trace connections between vias 2 trace connections from test point to via array. 40 Via/Trace overlaps 40 Vias 45 mil hole 1.

7 Model/Simulator Validation Via test strip contains mil vias 39 trace connections between vias 2 trace connections from test point to via array. 40 Via/Trace overlaps 40 Vias 45 mil hole 1.65 mil plating 39 Via-to-via trace connections 65 mil trace width 2 mil trace thickness 30 mil trace length 2 Test point-to-via trace connection 65 mil trace width 2 mil trace thickness 143 mil trace length 40 Via/Trace overlaps 40 via/trace overlapping areas Via increases effective trace resistance Page 7

8 Simplified Incremental Modeling of Vias Connected by Traces Model as Rectangular Trace Model as Via Model as Rectangular Trace Model as Via Model as Rectangular Trace Page 8

This assumption is confirmed by 3D finite element simulation.

9 Via/Trace Overlap Model Approximation Model as a trace and then scale for surface area lost. Assume that negligible current flows on far side of via trace. This assumption is confirmed by 3D finite element simulation. Resistance of Trace = Resistivity x length/area Surface Area of Trace = Via Inner Diameter x Via Pad Diameter / 2 Surface Area of Via Hole = π x Via Diameter 2 / 2 Scale Factor = (Surface Area of Trace Surface Area of Via Hole) / Surface Area of Trace Page 9

10 Via Resistance Calculation The resistance of a via can be approximated by calculating the resistance of the equivalent rectangular volume described by the Via Resistance = Resistivity x Length of Via / Area of Via Plating Area = pi x (Inner diameter + Plating thickness) x Plating thickness Resistivity of Copper = 1.7e-6 Ω-cm (.67e-6 Ω-in) For a 45 mil via hole 62 mils long with 2 mil plating Via Resistance =.67E-6 x.062 / π x ( ) x.002 Via Resistance = 141 µω Page 10

11 Via-to-Via Trace Resistance Calculation The resistance of a trace can be calculated by the following standard formula: Trace Resistance = Resistivity x Length of trace / Area of trace Area = Trace Width x Total Thickness (copper + plating) Resistivity of Copper = 1.7e-6 Ω-cm (.67e-6 Ω-in) For a 30 mil long trace, 65 mil wide, with 2 mil thickness Trace Resistance =.67E-6 x.030 / (.065 x.002) Trace Resistance = 154 µω Page 11

12 Test Point-to-Via Trace Resistance Calculation The resistance of a trace can be calculated by the following standard formula: Trace Resistance = Resistivity x Length of trace / Area of trace Area = Trace Width x Total Thickness (copper + plating) Resistivity of Copper = 1.7e-6 Ω-cm (.67e-6 Ω-in) For a 143 mil long trace, 65 mil wide, with 2 mil thickness Trace Resistance =.67E-6 x.143 / (.065 x.002) Trace Resistance = 737 µω Page 12

13 Via/Trace Overlap Resistance Calculation The resistance of a trace can be calculated by the following standard formula: Trace Resistance = Resistivity x Length of trace / Area of trace Area = Trace Width x Total Thickness (copper + plating) Resistivity of Copper = 1.7e-6 Ω-cm (.67e-6 Ω-in) For a 22.5 mil long trace, 65 mil wide, with 2 mil thickness Trace Resistance =.67E-6 x.0225 / (.065 x.002) Trace Resistance = 116 µω Surface Area of Trace =.045 x.065/2 = e-3 Surface Area of Via Hole = π x (.045/2) 2 /2 =.795e-3 Scale Factor = (1.4625e-3.795e-3) / e-3 =.458 Resistance = 253 µω Page 13

14 45 mil Via Test Array Resistance Calculation The resistance of the via array is calculated as follows: 40 Vias 40 x 141 µω = 5.64 mω (24%) 39 Via-to-via trace connections 39 x 154 µω = 6.01 mω (26%) 2 Test point-to-via trace connection 2 x 737 µω = 1.47 mω (6%) 40 Via/Trace overlaps 40 x 253 µω = mω (44%) Total mω (100%) Key Point: Breakout traces attached to vias contribute 75% of the via resistance. Page 14

15 Power Integrity Guidelines Via Array Resistance Measurements Via 40 Via Resistance Measured 40 Via Resistance Simulated Ansoft SIWave Average Linear Via Interconnect Resistance Ansoft Extracted Via Barrel Resistance Residual non- Via Interconnect Resistance 45 mil 21.9 mω 21.8 mω (23.2 by hand) 510 µω 159 µω 351 µω 20 mil 32.3 mω 33.6 mω 770 µω 401 µω 369 µω 15 mil 43.7 mω 44.2 mω 1.06 mω 647 µω 413 µω 12 mil 47.3 mω 47.3 mω 1.15 mω 704 µω 446 µω 10 mil 48.0 mω 49.1 mω 1.16 mω 729 µω 431 µω Linear Via Interconnect Resistance the resistance of the via barrel, pad and connecting trace, calculated by removing the test trace resistance from the 40 via measured resistance and dividing by 40. Via Barrel Resistance the resistance of the via barrel by itself. Residual non-via interconnect resistance the resistance of the pad and connecting trace for one via, calculated by subtracting the barrel resistance from the linear resistance. Page 15

16 SFM and TFM surface mount breakout regions (BOR) use simple surface mount pads and 18 mil breakout vias. SFM/TFM Power Integrity Guidelines Surface Mount BOR Due to high pad resistance, thermal spokes on vias are not recommend. SFM Surface Mount BOR TFM Through Hole BOR Page 16

17 SFM/TFM Power Integrity Guidelines Direct Plane Attach Resistance Test (1 contact) The direct plane attach resistance test provides a reasonable estimate of the total mounted contact resistance for a connector that is mounted through vias on large planes. Resistance of plane spreading resistance and attachments dominates the total resistance. For multiple contact power systems the focus needs to be on the resistive loss through the planes. Page 17

SFM Surface Mount Power Integrity Guidelines Current Density Plot (One Contact Excited @ 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount

18 SFM Surface Mount Power Integrity Guidelines Current Density Plot (One Contact 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount pads and small vias. 200 mil via used for power delivery to plane, spaced 2 away from connector. Multiple current sources used to inject 1A current evenly into power blades mω spreading resistance with ½ oz copper planes. Bottom plane placed 56 mil below top component pads shows worst case via attach resistance for boards with internal planes. 18 mil surface mount breakout via to power plane. Page 18

SFM Surface Mount Power Integrity Guidelines Current Density Plot (One Contact Excited from Side @ 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to

19 SFM Surface Mount Power Integrity Guidelines Current Density Plot (One Contact Excited from 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount pads and small vias. 200 mil via used for power delivery to plane, spaced 2 away from connector. Multiple current sources used to inject 1A current evenly into power blade mω spreading resistance with ½ oz copper planes. Bottom plane placed 56 mil below top component pads shows worst case via attach resistance for boards with internal planes. 18 mil breakout via to power plane. No significant degradation w.r.t. direction of current flow to power supply. (0.070 mω difference) Page 19

SFM Surface Mount Power Integrity Guidelines Current Density Plot (Forty Contacts Excited @ 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface

20 SFM Surface Mount Power Integrity Guidelines Current Density Plot (Forty Contacts 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount pads and small vias. 200 mil via used for power delivery to plane, spaced 2 away from connector. Multiple current sources used to inject 1A current evenly into power blade mω spreading resistance with ½ oz copper planes. Bottom plane placed 56 mil below top component pads shows worst case via attach resistance for boards with internal planes. 18 mil breakout via to power plane. Page 20

SFM Surface Mount Power Integrity Guidelines Current Density Plot (Forty Contacts Excited from Side @ 1A) Integrity BOR shows degradation of DC current flow into power/ground blade region of

21 SFM Surface Mount Power Integrity Guidelines Current Density Plot (Forty Contacts Excited from 1A) Integrity BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount pads and breakout vias. 200 mil via used for power delivery to plane, spaced 2 away from connector mω spreading resistance with ½ oz copper planes. Bottom plane placed 56 mil below top component pads shows worst case via attach resistance for boards with internal planes. 18 mil breakout via to plane. Multiple current sources used to inject 1A current evenly into power blade. Page 21

SFM Power Integrity Guidelines Current and Voltage Gradient BOR design facilitates high manufacturability and rework capability, while providing even current distribution into the connector

22 SFM Power Integrity Guidelines Current and Voltage Gradient BOR design facilitates high manufacturability and rework capability, while providing even current distribution into the connector power/ground blade. Note increased current density at surface mount pads and vias as current is distributed from plane to the connector contact pad. Using multiple pins on the connector for power delivery helps to mitigate the impact of pad resistance. Page 22

SFM Power Integrity Guidelines Current and Voltage Gradient Near Board Edge w/ 40 Contacts Excited Increased current density as connector is positioned close to the edge of the PCB. 1.

23 SFM Power Integrity Guidelines Current and Voltage Gradient Near Board Edge w/ 40 Contacts Excited Increased current density as connector is positioned close to the edge of the PCB mω spreading resistance with ½ oz copper planes. Power blade at center of connector is fairly immune to current crowding at the edge of the PCB mω resistance degradation vs. connector mounted in center of the board. (0.118 mω 150 mil from edge) Center of connector is positioned 300 mils from edge of PCB. Page 23

TFM Surface Mount Power Integrity Guidelines Current Density Plot (One Contact Excited @ 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount

24 TFM Surface Mount Power Integrity Guidelines Current Density Plot (One Contact 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount pads and 18 mil via breakout. 200 mil via used for power delivery to plane, spaced 2 away from connector mω spreading resistance with ½ oz copper planes. Bottom plane placed 56 mil below top component pads shows worst case via attach resistance for boards with internal planes. 18 mil breakout via to power plane. Multiple current sources used to inject 1A current evenly into power blades. Page 24

TFM Surface Mount Power Integrity Guidelines Current Density Plot (Forty Contacts Excited @ 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface

25 TFM Surface Mount Power Integrity Guidelines Current Density Plot (Forty Contacts 1A) BOR shows degradation of DC current flow into power/ground blade region of connector, due to surface mount pads and 18 mil breakout vias. 200 mil via used for power delivery to plane, spaced 2 away from connector mω spreading resistance with ½ oz copper planes. Bottom plane placed 56 mil below top component pads shows worst case via attach resistance for boards with internal planes. 18 mil breakout via to power plane. Multiple current sources used to inject 1A current evenly into power blade. Page 25

26 SFM/TFM Surface Mount Power Integrity Guidelines Average Contact Attach Resistance Tabulated Results # Pins Attach Resistance SFM/TFM PCB 2 Oz Attach Resistance SFM/TFM PCB 1 Oz Attach Resistance SFM/TFM PCB ½Oz SFM/TFM Contact Resistance per Bank (mω) Total Resistance SFM/TFM 1/2 Oz Cu Total Resistance SFM/TFM 1 Oz Cu Total Resistance SFM/TFM 2 Oz Cu / / / / / / / / / / / / Page 26

27 SFM/TFM Surface Mount Power Integrity Guidelines Parallel Power Resistance Current sharing on the power plane(s) ultimately limits the lowest resistance that can be achieved through a power connector. As additional connector contacts are added to the plane, parallel resistance reduces asymptotically SFM/TFM Power Resistance These results are valid for only the modeled configuration. Other architectures should be validated through measurement or simulation. Resistance (mohms) Pins Total Resistance (2 Oz Cu) Pins Total Resistance (1 Oz Cu) Pins Total Resistance (1/2 Oz Cu) < 4 mω DC path resistance possible with multiple pins < 2 mω DC path resistance possible with multiple pins and 1 or 2 Oz copper Resistance increases by about 5% - 10% when connector is placed close to the PCB edge Number of Pins Page 27

28 SFM/TFM Surface Mount Integrity Guidelines Connection Through 1 Oz Cu Plane Voltage Drop vs. Current Plane spreading resistance and current path sharing dominate the voltage drop through the SFM/TFM system SFM/TFM Connection Through 1 Oz Planes This plot represents a oneway current path from one board to another through SFM/TFM mated connectors. Total voltage drop for a ground and power system would incorporate a round-trip current loop, and would be double the total voltage drop from these curves. Voltage Drop (mv) Amp 2 Amp 10 Amp 15 Amp 20 Amp 40 Amp 80 Amp Voltage drop increases by about 5% - 10% when connector is placed near the PCB edge Number of Pins Page 28

29 SFM/TFM Power Integrity Guidelines Conclusions Key SFM/TFM conclusions: Spreading resistance of PCB dominates < 2 mω DC power/ground resistance achievable with 1/2 oz Cu power/ground planes and multiple contact pins. < 1 mω DC power/ground resistance possible with multiple contact pins and 2 Oz copper. Page 29

Power Integrity Guidelines Samtec MPT/MPS Series Connectors Measurement and Simulation Data

Power Integrity Guidelines Samtec MPT/MPS Series Connectors Measurement and Simulation Data Scott McMorrow, Director of Engineering Page 1 Modeled Section MPS Board MPT Board Power Via Power Via Power