Power Losses and Efficiency Analysis of

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1 Power Losses and Efficiency Analysis of Multilevel DC-DC Converters Zhguo Pan, Fan Zhang and Fang Z. Peng Dept. of Electrical and Computer Engineering Michigan State University 2120 Engineering Building East Lansing, MI USA Absrruct - This paper presents a detailed analysis about the power fosses and efficiency of multilevel dc-dc converters. The analysis considers different loss mechanisms and gives out quantitative descriptions of the power losses and useful design criteria. The analysis is based on a three-level multilevel dc-dc converter and can be extended to other switched-capacitor converters. The comparison between the theoretical analysis and the experimental results are shown to substantiate the theory. Keyword: multilevel converter, dc-de converter, power loss. I. INTRODUCTION There are constant demands for smaller, lighter and higher efficiency power supplies from industry, which push the dc-dc technique moving forward. Therefore a lot of new topologies, devices, and control strategies have been developed. But since the magnetic devices contained in most of the power electronics circuits are bulky, low-efficiency, and can not be further integrated, they become the bottleneck preventing the converter from reaching the high power density and high efficiency. The breakthrough can be achieved by a new breed of dc-dc converters: switched-capacitor dc-dc converter, which consists of only switching devices and capacitors, also called as charge-pump circuit. The simplest switched capacitor dc-dc converter is the serial-parahel structure [ 1][2]. Fig.1 shows a three stages switched capacitor dc-dc converter. During the charging state, the switches SI, S,, and S, is turned on, the three capacitors C, - CJ are connected in series and charged by the input voltage. During the discharging state, the switches SIP, SIN, Szp and S2, are turned on, the three capacitors Cl - C, are connected in parallel and power the load. Several new topologies and control methods based on the switched capacitors are proposed [3]-[6]. Because no magnetic components are needed, the switched-capacitor - C, J- RI. 1 &- Fig. 1. Three-stage switchedsapacitor dc-dc converter topology, converter can obtain high efficiency, high power density and ability to integrate. In the topology shown in Fig. 1, the device ratings required are different. Far the devices in the first stage, SI, SI, and SI, the voltage ratings required are same as the voltage ratings of the capacitors. However, voltage ratings required for the devices in the second stage are twice as the voitage ratings of the capacitors. For the converter with higher numbers of stage, the voltage ratings required are higher. Therefore the applications of the switched-capacitor converter are limited mainly to low power levels up to several tens of watts. The multilevel dc-dc converter has been proposed recently and provides the possibility to implement medium power conversion [7]. A 42 V / 14 V multilevel converter with 1-kW power rating is presented in [SI. The converter can achieve a high efficiency over 98%. Because of /05/$ IEEE. 1393

2 I 1 i 7 "T 0 ' I I."(a) State 1 RI Fig. 2. Multilevel dc-dc converter and its switching states. the high power density of the multilevel converters, the analysis of the power losses and the efficiency becomes very important to the design of the multilevel converter in medium power application. Because multilevel dc-dc converters also only consist of switching devices and capacitors, they can share the similar analysis. State-spaceweraging is widely used to analyze the switched-capacitor converter [9]. Harris and Ngo proposed a modified state-space-averaging technique and suggested a design procedure based on analysis results [I]. In this paper, the switching model of the multilevel dc-dc converter is presented. The power. losses are categorized and analyzed in detail. The analysis is based on the energy transfening between capacitors, and it is less complex than the traditional state-space analysis. The quantitative description of the converter performance and the useful design criteria will be obtained. The compiuison between the theoretical analysis and the experiment results wiil be shown to substantiate the theory. 11. POWER ROW OF THE MULTILEVEL DC-DC CONVERTER Fig2 shows the multilevel dc-dc converter, which is actually a four-level flying capacitor converter. There are only six MOSFETs needed for this topology, and the voltage rating of each MOSFET is same as the voltage rating of each capacitor. Compared with the switched-capacitor converter, the total device ratings of the multilevel converter are much smaller, which make!: it a better choice far the medium power I i d (c) State 111 Fig. 3. Powers flow in each switching states. conversion. Since there are three switching combinations that can make the output to be one voltage level, V,, by rotating among these three switch states, as shown in Fig. 2(b), the voltages of all capacitors could be balanced while the output keeps constant. Fig. 3 shows the power flows between capacitors during each switching state. In,the beginning of each switch state, the capacitors are connected in series into a loop. If the total voltage of the capacitors in the loop is not zero, there will be power flow from the capacitors having higher voltage to those having lower voltage, until the totai'loop voltage equals zero. In State I, the input voltage charges capacitors C, and CO,,, as shown in Fig. 3(a). Similarly, in State II, capacitor C, charges capacitors C1 and CO,,. In State 111, capacitor C, charges capacitors CO,,. Meanwhile, C, keeps outputting power to the load. During the steady state operation, the discharging and charging powers of the capacitors are 1394

3 Therefore, the power flowing out from CA, the power flowing into C,, and the capacitor charging loss can be obtained by Fig. 4. Power flow when two capacitors are connected. balanced. Therefore, the voltage of each capacitor will go.back to its initial value after every cycle POWER Loss ANALYSIS The power losses of multilevel converters, which are similar with those in switch-capacitors dc-dc converters, can be divided into following categories: 1) Capacitor Charging Loss: In the multilevel dc-dc converter circuits, capacitors will be forced to connect to the input voltage source or other capacitors. When capacitors with different voltages are connected together. The capacitor with higher voltage tends to charge the one with lower one until they reach same voltage. There will be a fixed power loss accompany each charging contact. This charging loss which is irrelevant to the parasitic resistance, such as the ESR of the capacitors or the on-state resistance of the MOSFETs,. 2) Conduction Loss: Conduction loss refers to the power dissipated on the parasitic resistance when the capacitor is connected to the load. Unlike the capacitor charging loss, the conduction loss could be reduced by choosing devices with lower parasitic resistance. 3) Switching Loss: Switching loss refers to the power loss every time when the MOSFET is turned on or off. The switching could be neglected when the switching frequency is lower. However, it could become the dominant portion of the total power loss when the switching frequency is high. 4) Conpol Circuit Loss: All power loss on the control and gate drive circuit. A. Capacitor Charging Loss Fig. 4 shows the power transfer process when two capacitors with different voltages are connected together. If there are more than two capacitors in the loop, the capacitors with same polarity could be grouped together and replaced by an equivalent capacitor. Assume the voltage difference of two capacitors is AV. ARer the switch turns on, the charge current ica-cs is given by where R,oop the loop resistance including the ESR of the capacitors and the on-state resistance of the MOSFETs, and C,o, equals C&/(CA + C,). (4) where Tis the turn on period, andfis the switching frequency. According to the switching states discussed before, we can get that T= 1/( 3J) Assume that the ripple voltage AV satisfies dy<<v, Po,, and Pin can be simplified to When T;.>R~,,C,oop is satisfied, the ripple voltage dv can be obtain from (5), which is From (6) it can be concluded that the rippie voltage dvis proportional to the power transferred from the capacitor with higher voltage to the one with lower voltage, P,--.cB, and inversely proportional to the switching frequency5 Substituting (6) into (4), the capacitor charging loss can be obtained by P"'=2.C,.CB.y?f (CA -b C,>PA-,. (7) It can be seen that the capacitor charging loss is irrelevant to the parasitic resistance. In order to reduce the capacitor charging loss, we can either increase the capacitance of the capacitors or increase the switching frequency, J: However, equations (6) and (7) are based on the assumption that ~>R~oop~C~oop is satisfied. If the switching frequency is high enough, that assumption will not be valid any more. The capacitor charging loss under that condition needs to multiply a factor M, which is given by T 1 +e R.4.C.P M= - r 1 - e %% Then the capacitor charging loss is given by (8) 1395

4 Fig. 5. Power flow when the Ioad is connected. Fig V I 14 V multilevel dcdc converter prototype. The factor Mis 1 when P>R,mp.C,oop is satisfied. When f keeps increasing, M will also begin to increase, which will offset the decreasing tendency of the capacitor charging loss. So the minimum capacitor charging loss for given capacitors is Then the conduction loss can be calculated by It can be seen that the conduction loss is proportional to the parasitic resistance of the capacitors and switching devices. Changing the capacitances alone can not significantly reduce the conduction loss. B. Conducting Loss In Fig. 4, only Capacitors are considered. However, the load is always connected to, and keeps drawing power from the output capacitor Cl,. Fig. 5 shows the power transfer process if the two capacitors shown in Fig. 6 are connected to the load at same time. The output power from the capacitor with higher voltage not only charges the one with lower voltage, but also powers the load at same time. it can be seen in Fig. 5 that after the load is connected to capacitor Cs, part of the output power, pa-^, will be directly transferred from CA to the load, and the rest of it will charge capacitor Cs. Assume that the total power Bow out from CA is Pow,, the power flowing between capacitors and load can be solved by,- Since the voltage ripple on the capacitor is far less than the capacitor voltage, the current ica-l and icg-t are nearly dc currents. Assuming that load resistance RL is far greater than the parasitic resistance, the current Ia.L and IcBmL can be expressed by C. Swirching Loss arid Control Circuit Loss The switching loss for each switching could be estimated by the switching current, switching voltage and switching time. The easiest way is to assume that change of the voltage and current are linear during the switching time. Therefore the switching loss can be estimated by 1 ems=-v I t f (161 6 IV where tsw is the switching time. The control circuit loss is difficult to be estimated, however, since it is not related with the Ioad, it can be measured under no-load condition. IV. EXPERIMENTAL RESULTS A multilevel dc-dc converter used for the 42 V I 14 V automotive system was built to demonstrate the advantages. The prototype is shown in Fig. 8. There is no inductor inside the converter, The parameters of the capacitors and MOSFETs are shown in Table I. The prototype was hand-wired on Vector boards with discrete DIP chips. The 1396

5 TABLE 1 PARAMETERS OF THE COMPONENTS Component I Capacitance I Resistance C, I 31.2mF mQ. c2 14.4mF 2.75 d c3 8mF 18.25mR CO, 27.3mF 3.14mn MOSFET mfl,..,.,,.,,,.,....,. Fig. 7. Detailed power loss analysis when load is 600 W. I,,..,,. I I,,.,, Fig. 8. Comparison of the calculated power loss and measured power loss with different switching frequency. size can be further reduced by using PCB, SMT components, and capacitors and MOSFETs with better performance. The converter was test under different load conditions and switching frequencies. The power losses are measured and the efficiencies are calculated. Based on the previous analysis, the capacitor charging loss and conduction loss under different switching frequency can the calculated. The switching time of the MOSFETs is measured, which is about 150 ns, therefore the switching loss also can be calculated, The control circuit loss under no-load condition is also measured. All these power losses when load Fig. 9. Comparison of the calculated efficiency and measured efficiency with different switching frequency, is 600 W are shown in Fig. 7. It can be seen that the capacitor charging loss is the dominate power loss when the switching frequency is low. The capacitor charging loss decreases while switching frequency increased, however, it became stable after the switching frequency reaches 2 khz. When the switching frequency keeps rising, the switching Ioss becomes the dominate power loss. Fig. 8 shows the calculated frequency - power loss curves with 300 W load and 600 W load. The measured power losses are presented by the triangles in the figure. It can be seen that the theoretical calculation results and the experimental results agree well in the low frequency operation. The error during the high frequency operation is relatively higher because there are relatively larger errors in the estimation of the switching loss. The power loss analysis will be more accurate if a better switching Ioss model is used. Fig. 8 can be used to choose the optimal operating switching frequency, which is 2-3 lchz for the prototype converter. The frequency - efficiency curves are shown in Fig. 9. Fig. 10 shows the switching loss under different load conditions when the switching frequency is 5.74 khz. Similarly the measured power losses are also presented by the triangles in the figure. The load - efficiency curves are shown in Fig. 11. V. CONCLUSION In this paper, the power loss of the multilevel dc-dc converter has been analyzed quantitatively. The switching frequency - efficiency curves and load - efficiency curves of a multilevei dc-dc converter have been obtained based on its parameter, which can be used to guide the selection of the devices parameters and the switching frequency. The comparison of the calculation and the measured results prove the validity of the analysis. 1397

6 [6]E. Bay, Optimized Control of the Flying -Capacitor Operating Voltage in Gear-Box -Charge-Pumps, -The Key Factor for a Smooth Operation, Proc. ofpower Electronics Specinlist Conj 03, pp , June [7]F. Zhang, F.Z. Peng, and Z. Qian, Study of the Multilevel Converters in DC-DC Application, Proc. ojpower Electronics Specialist Conf 04, pp , June [SI Fang 2. Peng, Fan Zhang, and Zhaoming Qian, A Novel Compact DC-DC Convefter for 42 V Systems, Proc. ojpower Elecrronics Specialist Con$ 03, pp , June lR.D. Middlebrook, and S. Cuk, A general unified approach to modeling switching converter power stages, Proc. of Power Electronics Specialist Conf 76, pp , June Fig. 10. Comparison of the calculated power loss and measured power loss with differenl. loads, 9, 1 ;,..._.. r_l_:...,...~...~ : ; I 4 A 4& 6k EA lobo lab0 Fig. 11. Comparison of the calculated efficiency and measured efficiency with different loads. REFERENCE [I] K.D.T. Ngo, and R. Webster, Steady-State Analysis and Design of a Switched-Capacitor DC-DC Converter, IEEE Trans. On Aero, ond Elec. Sysrem. Vol. 30.No.1, pp , Jan [ZIW. Harris, and K. Ngo, Power Switched-Capacitor DC DC Converter: Analysis and Design. IEEE Trans. on Aero. and Elec. System, Vol. 10, No. 3, pp , April [3] S.V. Cheong, H. Chung, and A. loinovici, Inductorless DC-to-DC Converter with High Power Converter, IEEE Trcms. on Ind. Elec.. Vol. 41, NO. 2, pp , April [4] 0. Mak, Y. Wang. and A. loinovici, Step-up dc-power supply based on a switched-capacitor circuil.teee Tram. on Ind. Elec., Vol. 42, No. 1, pp , Feb [SICK. Tse, S.C. Wong, and M.H.L. Chow, On Lussless SwitchedSapacitor Power Converkrs, IEEE Truits. on Power Elec., Vol. 10, No. 3, pp , May