LTC1760 Dual Smart Battery System Manager APPLICATIONS TYPICAL APPLICATION

Transcription

1 FEATURES n SMBus Charger/Seector for Two Smart Batteries* n otage and Current Accuracy within 0.2% of aue Reported by Battery n Simpifies Construction of Smart Battery System Manager n Incudes A SMBus Charger 1.1 Safety Features n Supports Autonomous Operation without a Host n Aows Both Batteries to Discharge Simutaneousy into Singe Load with Low Loss (Idea Diode) n SMBus Switching for Dua Batteries with Aarm Monitoring for Charging Battery at A Times n Pin Programmabe Limits for Maximum Charge Current and otage Improve Safety n Fast Autonomous PowerPath Switching (<10µs) n Low Loss Simutaneous Charging of Two Batteries n >95% Efficient Synchronous Buck Charger n AC Adapter Current Limiting* Maximizes Charge Rate n SMBus Acceerator Improves SMBus Timing** n Avaiabe in 48-Lead TSSOP Package APPLICATIONS n Portabe Computers and Instruments n Standaone Dua Smart Battery Chargers n Battery Backup Systems TYPICAL APPLICATION Dua Battery Charger/Seector System Architecture DESCRIPTION LTC1760 Dua Smart Battery System Manager The LTC 1760 Smart Battery System Manager is a highyintegrated SMBus Leve 3 battery charger and seector intended for products using dua smart batteries. Three SMBus interfaces aow the LTC1760 to servo to the interna votage and currents measured by the batteries whie aowing an SMBus Host device to monitor either battery s status. Charging accuracy is determined by the battery s interna votage and current measurements, typicay better than ±0.2%. A proprietary PowerPath architecture supports simutaneous charging or discharging of both batteries. Typica battery run times are extended by up to 10%, whie charging times are reduced by up to 50%. The LTC1760 automaticay switches between power sources in ess than 10µs to prevent power interruption upon battery or wa adapter remova. The LTC1760 impements a eements of a version 1.1 Smart Battery System Manager except for the generation of composite battery information. An interna mutipexer ceany switches the SMBus Host to either of the two attached Smart Batteries without generating partia messages to batteries or SMBus Host. Thermistors on both batteries are automaticay monitored for temperature and disconnection information (SafetySigna). L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and PowerPath is a trademark of Anaog Devices, Inc. A other trademarks are the property of their respective owners. Protected by U.S. Patents incuding * ** Dua vs Sequentia Charging DC IN SafetySigna 1 SMBus 1 LTC1760 SYSTEM POWER SMBus (HOST) BATTERY CURRENT (ma) BAT1 CURRENT BAT1 CURRENT BAT2 CURRENT BAT2 CURRENT SEQUENTIAL DUAL 100 MINUTES TIME (MINUTES) SafetySigna 2 SMBus TA01 BATTERY TYPE: 10.8 Li-Ion (MOLTECH NI2020) REQUESTED CURRENT = 3A REQUESTED OLTAGE = 12.3 MAX CHARGER CURRENT = 4.1A 1760 TA03 1

2 ABSOLUTE MAXIMUM RATINGS (Note 1) DCIN, SCP, SCN, CLP, PLUS, SW to GND to 32 SCH1, SCH2 to GND to 28 BOOST to GND to 37 CSP, CSN, BAT1, BAT2 to GND to 28 LOPWR, DCDI to GND to 10 CC2, DDS to GND to 7 SDA1, SDA2, SDA, SCL1, SCL2, SCL, SMBALERT to GND to 7 MODE to GND to CC COMP1 to GND to 5 Maximum DC Current Into Pin SDA1, SDA2, SDA, SCL1, SCL2, SCL... ±3mA TH1A, TH2A... 5mA TH1B, TH2B µA Operating Junction Temperature Range (Note 6) C to 125 C Storage Temperature C to 150 C Lead Temperature (Sodering, 10 sec) C PIN CONFIGURATION TOP IEW PLUS BAT2 BAT1 SCN SCP GDCO GDCI GB1O GB1I SCH2 47 GCH2 46 GCH1 45 SCH1 44 TGATE 43 BOOST 42 SW 41 DCIN 40 CC GB2O 10 GB2I 11 LOPWR 12 SET 13 I TH 14 I SET 15 DCDI 16 SCL2 17 SCL 18 SCL1 19 DDS 20 SDA2 21 SDA 22 SDA1 23 GND BGATE 38 PGND 37 COMP1 36 CLP 35 CSP 34 CSN 33 LIMIT 32 I LIMIT 31 TH1B 30 TH1A 29 SMBALERT 28 TH2A 27 TH2B 26 MODE 25 CC2 FW PACKAGE 48-LEAD PLASTIC TSSOP T JMAX = 125 C, q JA = 110 C/W ORDER INFORMATION ( LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1760CFW#PBF LTC1760CFW#TRPBF LTC1760CFW 48-Lead Pastic TSSOP 0 C to 85 C LTC1760IFW#PBF LTC1760IFW#TRPBF LTC1760IFW 48-Lead Pastic TSSOP 40 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: Some packages are avaiabe in 500 unit rees through designated saes channes with #TRMPBF suffix. 2

3 ELECTRICAL CHARACTERISTICS LTC1760 The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C (Note 6). DCIN = 20, BAT1 = 12, BAT2 = 12, DDS = 3.3, CC2 = 5.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Suppy and Reference DCIN Operating Range DCIN Seected 6 28 I CH0 I CH1 DCIN Operating Current Not Charging (DCIN Seected) (Note 10) Charging (DCIN Seected) (Note 10) I CC2_AC1 CC2 Operating Current AC Present (Note 11) I CC2_AC0 AC Not Present (Note 11) Battery Operating otage Range Battery Seected, PowerPath Function Battery Seected, Charging Function (Note 2) I BAT Battery Drain Current Battery Seected, Not Charging, DCIN = 0 (Note 10) 175 µa FDC FB1 FB2 FSCN PLUS Diodes Forward otage: DCIN to PLUS BAT1 to PLUS BAT2 to PLUS SCN to PLUS I CC = 10mA I CC = 0mA I CC = 0mA I CC = 0mA m ULO Undervotage Lockout Threshod PLUS Ramping Down, Measured at PLUS to GND 3 5 CC CC Reguator Output otage LDR CC Load Reguation No Externa Connection Beyond Appications Shown Herein % Switching Reguator TOL otage Accuracy With Respect to otage Reported by Battery CHMIN < Requested otage < LIMIT I TOL Current Accuracy With Respect to Current Reported by Battery 4m/R SENSE < Requested Current < I LIMIT (Min) (Note 12) R ILIMIT = 0 (Short to GND) R ILIMIT = 10k ±1% R ILIMIT = 33k ±1% R ILIMIT = Open (or Short I LIMIT to CC2 ) f 0SC Reguator Switching Frequency khz f DO Reguator Switching Frequency in Low Duty Cyce 99% khz Dropout Mode DC MAX Reguator Maximum Duty Cyce % I MAX Maximum Current Sense Threshod ITH = m I SNS CA1 Input Bias Current CSP = CSN > µa CMSL CA1 Input Common Mode Low 0 CMSH CA1 Input Common Mode High DCIN 0.2 CL1 CL1 Turn-On Threshod m C-Grade (Note 6) I-Grade (Note 6) m m TG t r TG t r BG t r BG t f TGATE Transition Time: TGATE Rise Time TGATE Fa Time BGATE Transition Time BGATE Rise Time BGATE Fa Time C LOAD = 3300pF, 10% to 90% C LOAD = 3300pF, 10% to 90% C LOAD = 3300pF, 10% to 90% C LOAD = 3300pF, 10% to 90% ma ma ma µa ma ma ma ma ns ns ns ns 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C (Note 6). DCIN = 20, BAT1 = 12, BAT2 = 12, DDS = 3.3, CC2 = 5.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Trip Points TR DCDI/LOPWR Threshod DCDI or LOPWR Faing C-Grade (Note 6) I-Grade (Note 6) THYS DCDI/LOPWR Hysteresis otage DCDI or LOPWR Rising 30 m I BT DCDI/LOPWR Input Bias Current DCDI or LOPWR = na TSC Short-Circuit Comparator Threshod SCP SCN, CC 5 C-Grade (Note 6) I-Grade (Note 6) FTO Fast PowerPath Turn-Off Threshod DCDI Rising from CC OSD Overvotage Shutdown Threshod as a SET Rising from 0.8 unti TGATE and BGATE 107 % Percent of Programmed Charger otage Stop Switching DACs I RES I DAC Resoution Guaranteed Monotonic 10 Bits t IP t ILOW I DAC Puse Period: Norma Mode Wake-Up Mode Charging Current Granuarity R ILIMIT = 0 (Short I LIMIT to GND) R ILIMIT = 10k ±1% R ILIMIT = 33k ±1% R ILIMIT = Open (or Short I LIMIT to CC2 ) m m 15 µs ms I WAKE_UP Wake-Up Charging Current (Note 5) ma I LIMIT Charging Current Limit C-Grade (Note 6) R ILIMIT = 0 (Short I LIMIT to GND) R ILIMIT = 10k ±1% R ILIMIT = 33k ±1% R ILIMIT = Open (or Short I LIMIT to CC2 ) ma ma ma ma ma ma ma ma I-Grade (Note 6) R ILIMIT = 0 (Short I LIMIT to GND) R ILIMIT = 10k ±1% R ILIMIT = 33k ±1% R ILIMIT = Open (or Short I LIMIT to CC2 ) RES DAC Resoution Guaranteed Monotonic (5 < BAT < 25) 11 Bits STEP DAC Granuarity 16 m LIMIT Charging otage Limit (Note 7) R LIMIT = 0 (Short LIMIT to GND) R LIMIT = 10k ±1% R LIMIT = 33k ±1% R LIMIT = 100k ±1% R LIMIT = Open (or Short LIMIT to CC2 )(Note 13) 5 Charge MUX Switches t ONC GCH1/GCH2 Turn-On Time GCHX SCHX > 3, C LOAD = 3000pF 5 10 ms t OFFC GCH1/GCH2 Turn-Off Time GCHX SCHX < 1, from Time of 15 µs CSN < BATX 30m, C LOAD = 3000pF CON CH Gate Camp otage GCH1 I LOAD = 1µA GCH1 SCH GCH2 GCH2 SCH ma ma ma ma m m m m m 4

5 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C (Note 6). DCIN = 20, BAT1 = 12, BAT2 = 12, DDS = 3.3, CC2 = 5.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS COFF CH Gate Off otage GCH1 GCH2 TOC CH Switch Reverse Turn-Off otage BATX CSN, 5 BATX 28 C-Grade (Note 6) I-Grade (Note 6) I LOAD =10µA GCH1 SCH1 0.8 GCH2 SCH2 0.8 FC CH Switch Forward Reguation otage CSN BATX, 5 BATX m GCH1/GCH2 Active Reguation: GCHX SCHX = 1.5 I OC(SRC) I OC(SNK) Max Source Current Max Sink Current 2 2 µa µa CHMIN BATX otage Beow Which Charging is Inhibited (Note 14) PowerPath Switches t DLY Banking Period after ULO Trip Switches Hed Off 250 ms t PPB Banking Period after LOPWR Trip Switches in 3-Diode Mode 1 sec t ONPO GB1O/GB2O/GDCO Turn-On Time GS < 3, from Time of Battery/DC 5 10 µs Remova, or LOPWR Indication, C LOAD = 3000pF t OFFPO GB1O/GB2O/GDCO Turn-Off Time GS > 1, from Time of Battery/DC Remova, or LOPWR Indication, C LOAD = 3000pF 3 7 µs PONO POFFO TOP FP I OP(SRC) I OP(SNK) Output Gate Camp otage GB1O GB2O GDCO Output Gate Off otage GB1O GB2O GDCO PowerPath Switch Reverse Turn-Off otage PowerPath Switch Forward Reguation otage GDCI/GB1I/GB2I Active Reguation: Source Current Sink Current I LOAD = 1µA Highest ( BAT1 or SCP ) GB1O Highest ( BAT2 or SCP ) GB2O Highest ( DCIN or SCP ) GDCO I LOAD = 25µA Highest ( BAT1 or SCP ) GB1O Highest ( BAT2 or SCP ) GB2O Highest ( DCIN or SCP ) GDCO SCP BATX or SCP DCIN 6 SCP 28 C-Grade (Note 6) I-Grade (Note 6) BATX SCP or DCIN SCP 6 SCP 28 (Note 3) m m m m m t ONPI Gate B1I/B2I/DCI Turn-On Time GS < 3, C LOAD = 3000pF (Note 4) 300 µs t OFFPI Gate B1I/B2I/DCI Turn-Off Time GS > 1, C LOAD = 3000pF (Note 4) 10 µs PONI Input Gate Camp otage I LOAD = 1µA GB1I GB2I GDCI Highest ( BAT1 or SCP ) GB1I Highest ( BAT2 or SCP ) GB2I Highest ( DCIN or SCP ) GDCI POFFI Input Gate Off otage GB1I GB2I GDCI I LOAD = 25µA Highest ( BAT1 or SCP ) GB1I Highest ( BAT2 or SCP ) GB2I Highest ( DCIN or SCP ) GDCI µa µa 5

6 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C (Note 6). DCIN = 20, BAT1 = 12, BAT2 = 12, DDS = 3.3, CC2 = 5.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Thermistor Thermistor Trip COLD-RANGE to OER-RANGE Thermistor Trip IDEAL-RANGE to COLD-RANGE Thermistor Trip HOT-RANGE to IDEAL-RANGE Thermistor Trip UNDER-RANGE to HOT-RANGE Logic Leves SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input Low otage ( IL ) SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input High otage ( IH ) SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input Leakage Current SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input Leakage Current I PULLUP SCL1/SDA1/SCL2/SDA2 Pu-Up Current When Not Connected to SMBus Host SCL1/SDA1/SCL2/SDA2 Series Impedance to Host SMBus SCL/SDA Output Low otage ( OL ). LTC1760 Driving the Pin SCL1/SDA1/SCL2/SDA2 Puup Output Low otage ( OL ). LTC1760 Driving the Pin with Battery SMBus not Connected to Host SMBus SCL1/SDA1/SCL2/SDA2 Output Low otage ( OL ). LTC1760 Driving the Pin with Battery SMBus Connected to Host SMBus SCL/SCL1/SCL2/SDA/SDA1/ SDA2/ SMBALERT Power Down Leakage IL_DDS DDS Input Low otage ( IL ) IH_DDS DDS Input High otage ( IH ) DDS Operating otage DDS Operating Current C LOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130Ω ±1% R1B = R2B = 54900Ω ±1% C LOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130Ω ±1% R1B = R2B = 54900Ω ±1% C LOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130Ω ±1% R1B = R2B = 54900Ω ±1% C-Grade (Note 6) I-Grade (Note 6) C LOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130Ω ±1% R1B = R2B = 54900Ω ±1% kω kω kω kω Ω 0.8 v 2.1 v SDA, SCL, SDA1, SCL1, SDA2, SCL2 = µa SDA, SCL, SDA1, SCL1, SDA2, 5 5 µa SCL2 = 2.1 SCL1, SDA1, SCL2, SDA2 = µa CC2 = 4.85 and 5.55 (Current is Through Interna Series Resistor and Schottky to CC2 ) SDA1, SCL1, SDA2, SCL2 = Ω I PULLUP = 350µA 0.4 I PULLUP Interna to LTC I PULLUP = 350µA on Host Side 0.4 CC2 = 0, DDS = 0, SCL, SCL1, SCL2, SDA, SDA1, SDA2, SMBALERT = 5.5 SCL, SDA = DDS, DDS = 5 2 µa SMBALERT Output Low otage ( OL ) I PULLUP = 500µA 0.4 SMBALERT Output Pu-Up Current SMBALERT = µa IL_MODE MODE Input Low otage ( IL ) CC2 = 4.85 CC µa 6

7 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C (Note 6). DCIN = 20, BAT1 = 12, BAT2 = 12, DDS = 3.3, CC2 = 5.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IH_MODE MODE Input High otage ( IH ) CC2 = 4.85 CC2 0.7 MODE Input Current (I IH ) MODE = CC2 0.7, CC2 = µa MODE Input Current (I IL ) MODE = CC2 0.3, CC2 = µa Charger Timing t TIMEOUT Timeout for Wake-Up Charging and sec Controed Charging t QUERY Samping Rate Used by the LTC1760 to Update Charging Parameters 1 sec SMBus Timing SCL Seria-Cock High Period(t HIGH ) At I PULLUP = 350µA, C LOAD = 150pF (Note 8) 4 µs SCL Seria-Cock Low Period (t LOW ) At I PULLUP = 350µA, C LOAD = 150pF (Note 8) 4.7 µs SDA/SCL Rise Time (t r ) C LOAD = 150pF, RPU = 9.31k (Note 8) 1000 ns SDA/SCL Fa Time (t f ) C LOAD = 150pF, RPU = 9.31k (Note 8) 300 ns SMBus Acceerator Trip otage Range Start-Condition Setup Time (t SU:STA ) 4.7 µs Start-Condition Hod Time (t HD:STA ) 4 µs SDA to SCL Rising-Edge 250 ns Setup Time (t SU:DAT ) SDA to SCL Faing-Edge Hod Time, 300 ns Save Cocking in Data (t HD:DAT ) t TIMEOUT_ SMB The LTC1760 wi Reease the SMBus and Terminate the Current Master or Save Command if the Command is not Competed Before this Time ms Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: Battery votage must be adequate to drive gates of PowerPath P-channe FET switches. This does not affect charging votage of the battery, which can be zero vots during wake-up charging. Note 3: DCIN, BAT1, BAT2 are hed at 12 and GDCI, GB1I, GB2I are forced to SCP is set at 12 to measure source current at GDCI, GB1I and GB2I. SCP is set at 11.9 to measure sink current at GDCI, GB1I and GB2I. Note 4: Extrapoated from testing with C L = 50pF. Note 5: Accuracy dependent upon externa sense resistor and compensation components. Note 6: The LTC1760 is tested under pused oad conditions such that T J T A. The LTC1760C is guaranteed to meet specifications from 0 C to 70 C junction temperature. Specifications over the 40 C to 85 C operating junction temperature range are assured by design, characterization and correation with statistica process contros. The LTC1760I is guaranteed over the 40 C to 125 C operating junction temperature range. Note 7: Charger servos to the vaue reported by a otage() query. This is the interna ce votage measured by the battery eectronics and may be ower than the termina votage. Refer to Operation Section 3.7 for more information. Note 8: C LOAD is the combined capacitance on the host s SMBus connection and the seected battery s SMBus connection. Note 9: C LOAD_MAX is the maximum aowed combined capacitance on THxA, THxB and the battery s SafetySignax connections. Note 10: Does not incude current suppied by CC to CC2 (I CC2_AC1 or I CC2_AC0 ) Note 11: Measured with thermistors not present, R LIMIT and R ILIMIT removed and SMBALERT = 1. See Appications Information section: Cacuating IC Operating Current for exampe on how to cacuate tota IC operating current. Note 12: Requested currents beow 44m/R SENSE may not servo correcty due to charger offsets. The charging current for requested currents beow 4m/R SENSE wi be between 4m/R SENSE and (Requested Current 8mA). Refer to Appications Information: Setting Charger Output Current Limit for vaues of R SENSE. Note 13: This imit is greater than the absoute maximum for the charger. Therefore, there is no effective imitation for the votage when this option is seected. Note 14: Does not appy to Wake-Up Mode. 7

8 TYPICAL PERFORMANCE CHARACTERISTICS otage() Chargingotage() (m) Charging otage Accuracy Chargingotage() (m) Current() ChargingCurrent() (ma) Charging Current Accuracy ChargingCurrent() (ma) 4000 BATTERY CURRENT (ma) Dua Battery Charge Time vs Sequentia Battery Charging BAT1 CURRENT BAT1 CURRENT BAT2 CURRENT BAT2 CURRENT SEQUENTIAL DUAL 100 MINUTES TIME (MINUTES) 1760 G G02 BATTERY TYPE: 10.8 Li-Ion (MOLTECH NI2020) REQUESTED CURRENT = 3A REQUESTED OLTAGE = 12.3 MAX CHARGER CURRENT = 4.1A 1760 G03 BATTERY OLTAGE () Dua Charging Batteries with Different Charge State BAT2 OLTAGE BAT2 CURRENT BAT1 OLTAGE BAT1 CURRENT TIME (MINUTES) BAT1 INITIAL CAPACITY = 0% BAT2 INITIAL CAPACITY = 90% PROGRAMMED CHARGER CURRENT = 3A PROGRAMMED CHARGER OLTAGE = BATTERY CURRENT (ma) 1760 G04 BATTERY OLTAGE () Dua Battery Discharge Time vs Sequentia Battery Discharge (Li-Ion) 12.0 BAT OLTAGE DUAL 10.0 BAT2 OLTAGE BAT2 OLTAGE SEQUENTIAL BAT1 9.0 OLTAGE 11 MINUTES TIME (MINUTES) BATTERY TYPE: 10.8 Li-Ion (MOLTECH NI2020) LOAD CURRENT = 3A 1760 G05 BATTERY OLTAGE () Dua Battery Dischage Time vs Sequentia Battery Discharge (NiMH) BAT2 13 OLTAGE DUAL 12 BAT1 11 OLTAGE 10 BAT2 15 OLTAGE 14 SEQUENTIAL 13 BAT1 12 OLTAGE MINUTES TIME (MINUTES) BATTERY TYPE: 12 NiMH (MOLTECH NJ1020) LOAD: 33W 1760 G06 8

9 TYPICAL PERFORMANCE CHARACTERISTICS LTC1760 EFFICIENCY (%) Efficiency vs Charging Current Load Dump Load Reguation I OUT (A) BAT1 OLTAGE () BAT1 OUTPUT IN = 20 DAC = I DAC = 3000mA LOAD CURRENT = 1A T A = 25 C LOAD CONNECTED LOAD DISCONNECTED TIME (ms) BAT1 OLTAGE () IN = 20 DAC = I DAC = 4000mA T A = 25 C CHARGE CURRENT (ma) G G G PowerPath Switching 1 and 2 C LOAD = 20F I LOAD = 0.8A T A = 25 C 5 SMBus Acceerator Operation CC = 5 C LD = 200pF T A = 25 C LOAD OLTAGE () LOPWR THRESHOLD 0 LTC1760 R PULLUP = 15k TIME (µs) 1µs/DI 1960 G G11 PIN FUNCTIONS Input Power Reated SCN (Pin 4): PowerPath Current Sensing Negative Input. This pin shoud be connected directy to the bottom (output side) of the sense resistor, R SC, in series with the three PowerPath switch pairs, for detecting short-circuit current events. Aso powers the LTC1760 interna circuitry when a other sources are absent. SCP (Pin 5): PowerPath Current Sensing Positive Input. This pin shoud be connected directy to the top (switch side) of the sense resistor, R SC, in series with the three PowerPath switch pairs, for detecting short-circuit current events. GDCO (Pin 6): DCIN Output Switch Gate Drive. Together with GDCI, this pin drives the gate of the P-channe switch in series with the DCIN input switch. GDCI (Pin 7): DCIN Input Switch Gate Drive. Together with GDCO, this pin drives the gate of the P-channe switch connected to the DCIN input. 9

10 PIN FUNCTIONS GB1O (Pin 8): BAT1 Output Switch Gate Drive. Together with GB1I, this pin drives the gate of the P-channe switch in series with the BAT1 input switch. GB1I (Pin 9): BAT1 Input Switch Gate Drive. Together with GB1O, this pin drives the gate of the P-channe switch connected to the BAT1 input. GB2O (Pin 10): BAT2 Output Switch Gate Drive. Together with GB2I, this pin drives the gate of the P-channe switch in series with the BAT2 input switch. GB2I (Pin 11): BAT2 Input Switch Gate Drive. Together with GB2O, this pin drives the gate of the P-channe switch connected to the BAT2 input. CLP (Pin 36): The Positive Input to the Suppy Current Limiting Ampifier CL1. The threshod is set at 100m above the votage at the DCIN pin. When used to imit suppy current, a fiter is needed to fiter out the switching noise. Battery Charging Reated SET (Pin 13): The Tap Point of a Programmabe Resistor Divider which Provides Battery otage Feedback to the Charger. A capacitor from CSN to SET and from SET to GND provide necessary compensation and fitering for the votage oop. I TH (Pin 14): The Contro Signa of the Inner Loop of the Current Mode PWM. Higher I TH votage corresponds to higher charging current in norma operation. A capacitor of at east 0.1µF to GND fiters out PWM rippe. Typica fu-scae output current is 30µA. Nomina votage range for this pin is 0 to 2.4. I SET (Pin 15): A capacitor from I SET to GND is required to fiter higher frequency components from the deta-sigma I DAC. I LIMIT (Pin 32): An externa resistor (R ILIMIT ) is connected between this pin and GND. The vaue of the externa resistor programs the range and resoution of the programmed charger current. LIMIT (Pin 33): An externa resistor (R LIMIT )is connected between this pin and GND. The vaue of the externa resistor programs the range and resoution of the votage DAC. CSN (Pin 34): Current Ampifier CA1 Input. Connect this to the common output of the charger MUX switches. CSP (Pin 35): Current Ampifier CA1 Input. This pin and the CSN pin measure the votage across the charge current sense resistor, R SENSE, to provide the instantaneous current signas required for both peak and average current mode operation. COMP1 (Pin 37): The Compensation Node for the Ampifier CL1. A capacitor is required from this pin to GND if input current ampifier CL1 is used. At input adapter current imit, this node rises to 1. By forcing COMP1 to GND, ampifier CL1 wi be defeated (no adapter current imit). COMP1 can source 10µA. BGATE (Pin 39): Drives the gate of the bottom externa MOSFET of the battery charger buck converter. SW (Pin 42): PWM Switch Node. Connected to the source of the top externa MOSFET. Used as reference for top gate driver. BOOST (Pin 43): Suppy to Topside Foating Driver. The bootstrap capacitor is returned to this pin. otage swing at this pin is from a diode drop beow CC to (DCIN + CC ). TGATE (Pin 44): Drives the gate of the top externa MOSFET of the battery charger buck converter. SCH1 (Pin 45), SCH2 (Pin 48): Charger MUX N-Channe Switch Source Returns. These two pins are connected to the sources of the back-to-back switch pairs Q3/Q4 and Q9/Q10 (see Typica Appications). A sma pu-down current source returns these nodes to 0 when the switches are turned off. GCH1 (Pin 46), GCH2 (Pin 47): Charger MUX N-Channe Switch Gate Drives. These two pins drive the gates of the back-to-back switch pairs, Q3/Q4 and Q9/Q10, between the charger output and the two batteries (see Typica Appications). Externa Power Suppy Pins PLUS (Pin 1): Suppy. The PLUS pin is connected via four interna diodes to the DCIN, SCN, BAT1, and BAT2 pins. Bypass this pin with a 0.1µF capacitor and a 1µF capacitor (see Typica Appications for compete circuit). BAT1 (Pin 3), BAT2 (Pin 2): These two pins are the inputs from the two batteries for power to the LTC

11 PIN FUNCTIONS LOPWR (Pin 12): LOPWR Comparator Input from SCN Externa Resistor Divider to GND. If the votage at LOPWR pin is ower than the LOPWR comparator threshod, then system power has faied and power is autonomousy switched to a higher votage source, if avaiabe. DCDI (Pin 16): Externa DC Source Comparator Input from DCIN Externa Resistor Divider to GND. If the votage at DCDI pin is above the DCDI comparator threshod, then the AC_PRESENT bit is set and the wa adapter power is considered to be adequate to charge the batteries. If DCDI rises more than 1.8 above CC, then a of the power path switches are atched off unti a power is removed. A capacitor from DCDI to GND is recommended to prevent noise-induced fase emergency turn-off conditions from being detected. Refer to Section 8.3 and Typica Appication. DCIN (Pin 41): Suppy. Externa DC power source. A 0.1µF bypass capacitor must be connected to this pin as cose as possibe. No series resistance is aowed, since the adapter current imit comparator input is aso this pin. Interna Power Suppy Pins DDS (Pin 20): Power Suppy for SMBus Acceerators. Aso used in conjunction with MODE pin to modify the LTC1760 operating mode. GND (Pin 24): Ground for Low Power Circuitry. CC2 (Pin 25): Power Suppy is used Primariy to Power Interna Logic Circuitry. Must be connected to CC. PGND (Pin 38): High Current Ground Return for BGATE Driver. CC (Pin 40): Interna Reguator Output. Bypass this output with at east a 2µF to 4.7µF capacitor. Do not use this reguator output to suppy externa circuitry except as shown in the appication circuit. SBS Interface Pins SCL2 (Pin 17): SMBus Cock Signa to Smart Battery 2. Do not connect to an externa pu-up. The LTC1760 connects this pin to an interna pu-up (I PULLUP ) when required. LTC1760 SCL (Pin 18): SMBus Cock Signa to SMBus Host. Aso used to determine fashing rate for stand-aone charge indicators. Requires an externa puup to DDS (norma SMBus operating mode). Connected to interna SMBus acceerator. SCL1 (Pin 19): SMBus Cock Signa to Smart Battery 1. Do not connect to an externa pu-up. The LTC1760 connects this pin to an interna pu-up (I PULLUP ) when required. SDA2 (Pin 21): SMBus Data Signa to Smart Battery 2. Do not connect to an externa pu-up. The LTC1760 connects this pin to an interna pu-up (I PULLUP ) when required. SDA (Pin 22): SMBus Data Signa to SMBus Host. Aso used to indicate charging status of Battery 2. Requires an externa puup to DDS. Connected to interna SMBus acceerator. SDA1 (Pin 23): SMBus Data Signa to Smart Battery 1. Do not connect to an externa pu-up. The LTC1760 connects this pin to an interna pu-up (I PULLUP ) when required. MODE (Pin 26): Used in conjunction with DDS to aow SCL, SDA and SMBALERT to indicate charging status. May aso be used as a hardware charge inhibit. TH2B (Pin 27): Thermistor Force/Sense Connection to Smart Battery 2 SafetySigna. Connect to Battery 2 thermistor through resistor network shown in Typica Appication. TH2A (Pin 28): Thermistor Force/Sense Connection to Smart Battery 2 SafetySigna. Connect to Battery 2 thermistor through resistor network shown in Typica Appication. SMBALERT (Pin 29): Active Low Interrupt Pin. Signas SMBus Host that there has been a change of status in battery or AC presence. Open drain with weak current source pu-up to CC2 (with Schottky to aow it to be pued to 5 externay). Aso used to indicate charging status of Battery 1. TH1A (Pin 30): Thermistor Force/Sense Connection to Smart Battery 1 SafetySigna. Connect to Battery 1 thermistor through resistor network shown in Typica Appication. TH1B (Pin 31): Thermistor Force/Sense Connection to Smart Battery 1 SafetySigna. Connect to Battery 1 thermistor through resistor network shown in Typica Appication. 11

12 BLOCK DIAGRAM GB1I GB1O GB2I GB2O GDCI GDCO SWB1 DRIER SWB2 DRIER SWDC DRIER SHORT CIRCUIT + 100m 100Ω 5 4 SCP SCN DCIN CHARGE PUMP LIMIT DECODER CC2 10µA 32 I LIMIT 33 LIMIT GCH1 SCH ON 29 SMBALERT GCH2 SCH2 BAT1 BAT ON CSN AC_PRESENT SEQUENCER SMBus INTERFACE MODE DDS SCL SDA SCL1 PLUS 1 SCN CHARGE SDA1 SCL2 CC SDA2 CC GND CC REGULATOR SAFETY SIGNAL DECODER TH1A TH1B TH2A DCDI TH2B PowerPath CONTROLLER 10-BIT Σ CURRENT DAC 15 I SET LOPWR 12 + DCIN BOOST TGATE SW BGATE PGND BGATE OSCILLATOR LOW DROP DETECT CC T ON PWM LOGIC CSN 0 S Q R CA1 + + DCIN 100m + CL1 11-BIT Σ OLTAGE DAC SET + g m = 1.4m I CMP I RE CA2 + BUFFERED I TH 3m 0.8 3k 3k 40m + CSP-CSN 3kΩ CSP CSN CLP 36 g m = 0.4m Ω g m = 1.4m Ω EA + 400k COMP1 I TH BD 12

13 TABLE OF CONTENTS (For Operation Section) LTC Overview The SMBus Interface SMBus Interface Overview Description of Supported SMBus Functions BatterySystemState() (0 01) BatterySystemStateCont() (0 02) BatterySystemInfo() (0 04) LTC() (0 3C) BatteryMode() (0 03) otage() (0 09) Current() (0 0A) ChargingCurrent() (0 14) Chargingotage() (0 15) AarmWarning() (0 16) AertResponse() SMBus Dua Port Operation LTC1760 SMBus Controer Operation LTC1760 SMBALERT Operation Charging Agorithm Overview Wake-Up Charging Initiation Wake-Up Charging Termination Wake-Up Charging Current and otage Limits Controed Charging Initiation Controed Charging Termination Controed Charging Current Programming Current Limits When Charging A Singe Battery Current Limits When Charging Two Batteries (TURBO Mode Disabed) Current Limits When Charging Two Batteries (TURBO Mode Enabed) Controed Charging otage Programming System Power Management Agorithm and Battery Caibration Turning Off System Power Power-By Agorithm When No Battery is Being Caibrated Power-By Agorithm When a Battery is Being Caibrated Power-By Reporting Battery Caibration (Conditioning) Seecting a Battery to be Caibrated Initiating Caibration of Seected Battery Terminating Caibration of Seected Battery MODE Pin Operation Standaone Charge Indication Hardware Charge Inhibit Charging When SCL And SDA Are Low Charging With an SMBus Host Battery Charger Controer Charge MUX Switches Dua Charging PowerPath Controer Autonomous PowerPath Switching Short-Circuit Protection Emergency Turn-Off Power-Up Strategy The otage DAC Bock The Current DAC Bock

14 OPERATION 1 Overview (Refer to Bock Diagram and Typica Appication Figure) The LTC1760 is composed of an SMBus interface with dua port capabiity, a sequencer for managing system power and the charging and discharging of two batteries, a battery charger controer, charge MUX controer, PowerPath controer, a 10-bit current DAC (I DAC ) and 11-bit votage DAC ( DAC ). When couped with optiona system software for generating composite battery information, it forms a compete Smart Battery System Manager for charging and seecting two smart batteries. The battery charger is controed by the sequencer which uses a Leve 3 SMBus interface to read Chargingotage(), otage(), ChargingCurrent(), Current(), Aarm() and BatteryMode(). This information, together with thermistor measurements aows the sequencer to seect the charging battery and safey servo on votage and current. Charging can be accompished ony if the votage at DCDI indicates that sufficient votage is avaiabe from the input power source, usuay an AC adapter. The charge MUX, which seects the battery to be charged, is capabe of charging both batteries simutaneousy. The charge MUX switch drivers are configured to aow charger current to share between the two batteries and to prevent current from fowing in a reverse direction in the switch. The amount of current that each battery receives wi depend upon the reative capacity of each battery and the battery votage. This can resut in significanty shorter charging times (up to 50% for Li-Ion batteries) than sequentia charging of each battery. The sequencer aso seects which of the pairs of PFET switches wi provide power to the system oad. If the system votage drops beow the threshod set by the LOPWR resistor divider, then a of the output-side PFETs are turned on quicky. The input-side PFETs act as diodes in this mode and power is taken from the highest votage source avaiabe at the DCIN, BAT1, or BAT2 inputs. The input-side PowerPath switch driver that is deivering power then coses its input switch to reduce the power dissipation in the PFET buk diode. In effect, this system provides diode-ike behavior from the FET switches, without the attendant high power dissipation from diodes. The Host is informed of this 3-Diode mode status when it pos the PowerPath status register via the SMBus interface. High speed PowerPath switching at the LOPWR trip point is handed autonomousy. Simutaneous discharge of both batteries is supported. The switch drivers prevent reverse current fow in the switches and automaticay discharge both batteries into the oad, sharing current according to the reative capacity of the batteries. Simutaneous dua discharge can increase battery operating time by up to 10% by reducing osses in the switches and reducing interna battery osses associated with high discharge rates. 2 The SMBus Interface 2.1 SMBus Interface Overview The SMBus interface aows the LTC1760 to communicate with two batteries and the SMBus Host. The SMBus Interface supports true dua port operation by aowing the SMBus Host to be connected to the SMBus of either battery. The LTC1760 is abe to operate as an SMBus Master or Save device. The LTC1760 SMBUS address is 0 14 (8-bit format). References: Smart Battery System Manager Specification: Revision 1.1, SBS Impementers Forum. Smart Battery Data Specification: Revision 1.1, SBS Impementers Forum. Smart Battery Charger Specification: Revision 1.1, SBS Impementers Forum System Management Bus Specification: Revision 1.1, SBS Impementers Forum I 2 C-Bus and How to Use it: 1.0, Phiips Semiconductor. 14

15 OPERATION 2.2 Data Bit Definition of Supported SMBus Functions. Function LTC1760 SMBus Mode Access BatterySystemState() Save Read/ Write SMBus Address 7-bit: 0001_010b 8-bit: 0 14 Command Code Data Type 0 01 Status/ Contro Data Bit or Nibbe Definition/Aowed aues (See section 2.3 for Detais) D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 SMB_BAT4 SMB_BAT3 SMB_BAT2 SMB_BAT1 POWER_BY_BAT4 POWER_BY_BAT3 POWER_BY_BAT2 POWER_BY_BAT1 CHARGE_BAT4 CHARGE_BAT3 CHARGE_BAT2 CHARGE_BAT1 PRESENT_ BAT4 PRESENT_ BAT3 PRESENT_ BAT2 PRESENT_ BAT /1 0/ /1 0/ /1 0/ /1 0/1 BatterySystemStateCont() Save Read/ Write 7-bit: 0001_010b 8-bit: Status/ Contro CALIBRATE_BAT4 CALIBRATE_BAT3 CALIBRATE_BAT2 CALIBRATE_BAT1 CALIBRATE CHARGER_POR CHARGING_INHIBIT CALIBRATE_REQUEST CALIBRATE_REQUEST_SUPPORT POWER_NOT_GOOD AC_PRESENT BatterySystemInfo() Save Read 7-bit: 0001_010b 8-bit: 0 14 LTC() Save Read/ Write 7-bit: 0001_010b 8-bit: /1 0/1 0 0/1 0/1 0/1 0/1 1 0/1 0/ Status BATTERY SYSTEM REISION 0 3C Status/ Contro BATTERY SUPPORTED POWER_OFF TURBO LTC_ERSION3 LTC_ERSION2 LTC_ERSION1 LTC_ERSION0 BatteryMode() Master Read 7-bit: 0001_011b 8-bit: Status 0/ / CONDITION_FLAG 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 15

16 OPERATION Function LTC1760 Mode Access SMBus Address Current() Master Read 7-bit: 0001_011b 8-bit: 0 16 otage() Master Read 7-bit: 0001_011b 8-bit: 0 16 ChargingCurrent() Master Read 7-bit: 0001_011b 8-bit: 0 16 Chargingotage() Master Read 7-bit: 0001_011b 8-bit: 0 16 AarmWarning() Master Read 7-bit: 0001_010b 8-bit: 0 16 Command Code Data Type 0 0A aue 0 09 Status/ Contro 0 14 Status 0 15 Status/ Contro 0 16 Status Data Bit or Nibbe Definition/Aowed aues (See section 2.3 for Detais) D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 IA15 IA14 IA13 IA12 IA11 IA10 IA09 IA08 IA07 IA06 IA05 IA04 IA03 IA02 IA01 IA00 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 IR15 IR14 IR13 IR12 IR11 IR10 IR09 IR08 IR07 IR06 IR05 IR04 IR03 IR02 IR01 IR00 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 R15 R14 R13 R12 R11 R10 R09 R08 R07 R06 R05 R04 R03 R02 R01 R00 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 OER_CHARGED TERMINATE_CHARGE_ALARM TERMINATE_CHARGE_ OER_TEMP_ALARM TERMINATE_DISCHARGE_ALARM FULLY_DISCHARGED 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AertResponse() see (1) Save Read Byte 7-bit: 0001_100b 8-bit: 0 18 N/A Register ARA_ADD07 ARA_ADD06 ARA_ADD05 ARA_ADD04 ARA_ADD03 ARA_ADD02 ARA_ADD01 ARA_ADD00 (1) Read-byte format is returned as the interrupt address of the LTC

17 OPERATION 2.3 Description of Supported SMBus Functions The functions are described as foows: Function Name() (command code) Description: A brief description of the function. Purpose: The purpose of the function, and an exampe where appropriate. SMBus Protoco: Refer to Section 2.5 and to the SMBus specification for more detais. Input, Output or Input/Output: A description of the data suppied to, or returned by, the function. Whenever the LTC1760 encounters a vaid command with invaid data, it ACKs the command, and ignores the invaid data. For exampe, if an attempt is made to seect Battery 1 and 2 to simutaneousy communicate with the system host, the LTC1760 wi just ignore the request BatterySystemState() (0 01) Description: This function returns the present state of the LTC1760 and aows access to individua batteries. The information is broken into four nibbes that report: Which battery is communicating with the SMBus Host Which batteries, if any, or AC is powering the system Which batteries are connected to the Smart Charger Which batteries are present. The LTC1760 provides a mechanism to notify the system whenever there is a change in its state. Specificay, the LTC1760 provides the system with a notification whenever: A battery is added or removed (Poing or SMBALERT). AC power is connected or disconnected (Poing or SMBALERT). The LTC1760 autonomousy changes the configura-tion of the batteries suppying power (Poing ony). LTC1760 The LTC1760 autonomousy changes the configuration of the batteries being charged (Poing ony). Purpose: Used by the SMBus Host to determine the present state of the LTC1760 and the attached batteries. It aso may be used to determine the state of the battery system after the LTC1760 notifies the SMBus Host of a change via SMBALERT. SMBus Protoco: Read or Write Word. Input/Output: word Refer to Section 2.2 for bit mapping. SMB_BAT[4:1] Nibbe The read/write SMB_BAT[4:1] nibbe is used by the SMBus Host to seect with which individua battery to communicate or to determine with which individua battery it is communicating. For exampe, an appication that dispays the remaining capacity of a batteries woud write to this nibbe to individuay seect each battery in turn and get its capacity. Aowed vaues are: 0010b: SMBus Host is communicating with Battery b: SMBus Host is communicating with Battery 1. (Power On Reset aue) To change this nibbe, set ony one of the ower two bits of this nibbe high. A other vaues wi simpy be ignored. POWER_BY_BAT[4:1] Nibbe The read ony POWER_BY_BAT[4:1] nibbe is used by the SMBus Host to determine which batteries are powering the system. A writes to this nibbe wi be ignored. Aowed vaues are: 0011b: System powered by both Battery 2 and Battery 1 simutaneousy. 0010b: System powered by Battery 2 ony. 0001b: System powered by Battery 1 ony. 0000b: System powered by AC adapter ony. 17

18 OPERATION CHARGE_BAT[4:1] Nibbe The read ony CHARGE_BAT[4:1]nibbe is used by the SMBus Host to determine which, if any, battery is being charged. A writes to this nibbe wi be ignored. Aowed vaues are: 0011b: Both Battery 2 and Battery 1 being charged. 0010b: Ony Battery 2 is being charged. 0001b: Ony Battery 1 is being charged. 0000b: No battery being charged. An indication that mutipe batteries are being charged simutaneousy does not indicate that the batteries are being charged at the same rate or that they wi compete their charge at the same time. To actuay determine when an individua battery wi be fuy charged, use the SMB_BAT[4:1] nibbe to individuay seect the battery of interest and read the TimeToFu() vaue. PRESENT_BAT[4:1] Nibbe The read ony PRESENT_BAT[4:1]nibbe is used by the SMBus Host to determine how many and which batteries are present. A writes to this nibbe wi be ignored. Aowed vaues are: 0011b: Both Battery 2 and Battery 1 are present. 0010b: Ony Battery 2 is present. 0001b: Ony Battery 1 is present. 0000b: No batteries are present BatterySystemStateCont() (0 02) Description: This function returns additiona state information of the LTC1760 and provides a mechanism to prohibit charging. This command aso removes any requirement for the SMBus Host to communicate directy with the charger to obtain AC presence information. When the LTC1760 is used, access to the charger 8-bit address, 0 012, is bocked. Purpose: Used by the SMBus Host to retrieve additiona state information from the LTC1760 and the overa system 18 power configuration. It may aso be used by the system to prohibit any battery charging. SMBus Protoco: Read or Write Word. Input/Output: word - Refer to Section 2.2 for bit mapping AC_PRESENT Bit The read ony AC_PRESENT bit is used to show the user the status of AC avaiabiity to power the system. It may be used internay by the SMBus Host in conjunction with other information to determine when it is appropriate to aow a battery conditioning cyce. Whenever there is a change in the AC status, the LTC1760 asserts SMBALERT ow. In response, the system has to read this register to determine the actua presence of AC. The LTC1760 uses the DCDI pin to measure the presence of AC. Aowed vaues are: 1b: The LTC1760 has determined that AC is present. 0b: The LTC1760 has determined that AC is not present. POWER_NOT_GOOD Bit The read ony POWER_NOT_GOOD bit is used to show that the votage deivered to the system oad is inadequate. This is determined by the LOPWR comparator. The POWER_NOT_GOOD bit wi aso be set if the LTC1760 has detected a short circuit condition (see Section 8.2 ) or an emergency turn-off condition (see Section 8.3 ). Under either of these conditions the power paths wi be shut off even if battery or DC power is avaiabe. Aowed vaues are: 1b: The LTC1760 has determined that the votage deivered to the system oad is inadequate. 0b: The LTC1760 has determined that the votage deivered to the system oad is adequate. CALIBRATE_REQUEST_SUPPORT Bit The read ony CALIBRATE_REQUEST_SUPPORT bit is aways set high to indicate that the LTC1760 has a mechanism to determine when any of the attached batteries are in need of a caibration cyce.

19 OPERATION CALIBRATE_REQUEST Bit The read ony CALIBRATE_REQUEST bit is set whenever the LTC1760 has determined that one or both of the connected batteries need a caibration cyce. Aowed vaues are: 1b: The LTC1760 has determined that one or both batteries requires caibration. 0b: The LTC1760 has determined that neither battery require caibration. CHARGING_INHIBIT Bit The read/write CHARGING_INHIBIT bit is used by the SMBus Host to inhibit charging or to determine if charging is inhibited. This bit is aso set if the MODE pin is used to inhibit charging. Aowed vaues are: 1b: The LTC1760 wi not aow any battery charging to occur. 0b: The LTC1760 may charge batteries as needed, (Power On Reset aue). CHARGER_POR Bit The read/write CHARGER_POR bit is used to force a charger power on reset. Writing a 1 to this bit wi cause a charger power on reset with the foowing effects. Charging wi be turned off and wake-up charging wi be resumed. This is the same as if the batteries were removed and then reinserted. The three minute wake-up watchdog timer wi be restarted. Writing a 0 to this bit has no effect. A read of this bit aways returns a 0. CALIBRATE Bit The read/write CALIBRATE bit is used either to show the status of battery caibration cyces in the LTC1760 or to begin or end a caibration cyce. LTC1760 CALIBRATE_BAT[4:1] Nibbe The read/write CALIBRATE_BAT[4:1]nibbe is used by the SMBus Host to seect the battery to be caibrated or to determine which individua battery is being caibrated. Aowed read vaues are: 0010b: Battery 2 is being caibrated. CALIBRATE must be b: Battery 1 is being caibrated. CALIBRATE must be b: No batteries are being caibrated. Aowed write vaues are: 0010b: Seect Battery 2 for caibration. 0001b: Seect Battery 1 for caibration. 0000b: Aow LTC1760 to choose battery to be caibrated. A other vaues wi simpy be ignored. This provides a mechanism to update the other BatterySystemStateCont() bits without atering this nibbe BatterySystemInfo() (0 04) Description: The SMBus Host uses this function to determine the capabiities of the LTC1760. Purpose: Aows the SMBus Host to determine the number of batteries the LTC1760 supports as we as the specification revision impemented by the LTC1760. SMBus Protoco: Read Word Input/Output: word Refer to Section 2.2 for bit mapping. BATTERIES_SUPPORTED Nibbe The read ony BATTERIES_SUPPORTED nibbe is used by the SMBus Host to determine how many batteries the LTC1760 can support. The two-battery LTC1760 aways returns 0011b for this nibbe. 19

20 OPERATION BATTERY_SYSTEM_REISION Nibbe The read ony BATTERY_SYSTEM_REISION nibbe reports the version of the Smart Battery System Manager specification supported. LTC1760 aways returns 1000b for this nibbe, indicating ersion 1.0 without optiona PEC support LTC() (0 3C) Description: This function returns the LTC version nibbe and aows the user to perform expanded Smart Battery System Manager functions. Purpose: Used by the SMBus Host to determine the version of the LTC1760 and to program and monitor TURBO and POWER_OFF specia functions. SMBus Protoco: Read or Write Word. Input/Output: word Refer to Section 2.2 for bit mapping. POWER_OFF Bit This read/write bit aows the LTC1760 to turn off a power paths. Aowed vaues: 1b: A power paths are off. 0b: A power paths are enabed. (power on reset vaue). TURBO Bit This read/write bit aows the LTC1760 to enter TURBO charging mode. Refer to section 3.6. Aowed vaues: 1b: Turbo charging mode enabed. 0b: Turbo charging mode disabed. (Power On Reset aue). LTC_ersion[3:0] Nibbe This read ony nibbe aways returns 0001b as the LTC1760 version BatteryMode() (0 03) Description: This function is used by the LTC1760 to read the battery s Mode register. Purpose: Aows the LTC1760 to determine if a battery requires a conditioning/caibration cyce. SMBus Protoco: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Input/Output: word Refer to Section 2.2 for bit mapping. CONDITION_FLAG Bit The CONDITION_FLAG bit is set whenever the battery requires caibration. Aowed vaues: 1b: Battery requires caibration. (Aso known as a Condition Cyce Request). 0b: Battery does not require caibration otage() (0 09) Description: This function is used by the LTC1760 to read the actua ce-pack votage. Purpose: Aows the LTC1760 to determine the ce pack votage and cose the charging votage servo oop. SMBus Protoco: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer battery termina votage in mii-vots. Refer to Section 2.2 for bit mapping. Units: m. Range: 0 to 65,535 m. 20

21 OPERATION Current() (0 0A) Description: This function is used by the LTC1760 to read the actua current being suppied through the battery terminas. Purpose: Aows the LTC1760 to determine how much current a battery is receiving through its terminas and cose the charging current servo oop. SMBus Protoco: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: signed integer (2 s compement) charge/discharge rate in ma increments - positive for charge, negative for discharge. Refer to Section 2.2 for bit mapping. Units: ma. Range: 0 to 32,767 ma for charge or 0 to -32,768 ma for discharge ChargingCurrent() (0 14) Description: This function is used by the LTC1760 to read the Smart Battery s desired charging current. Purpose: Aows the LTC1760 to determine the maximum charging current. SMBus Protoco: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer maximum charger output current in ma. Refer to Section 2.2 for bit mapping. Units: ma. Range: 0 to 65,534 ma Chargingotage() (0 15) Description: This function is used by the LTC1760 to read the Smart Battery s desired charging votage. Purpose: Aows the LTC1760 to determine the maximum charging votage. SMBus Protoco: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer charger output votage in m. Refer to Section 2.2 for bit mapping. Units: m. Range: 0 to 65,534 m AarmWarning() (0 16) Description: This function is used by the LTC1760 to read the Smart Battery s Aarm register. Purpose: Aows the LTC1760 to determine the state of a appicabe aarm fags. SMBus Protoco: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer Refer to Section 2.2 for bit mapping. OER_CHARGED_ALARM Bit The read ony OER_CHARGED_ALARM bit is used by the LTC1760 to determine if charging may continue. Aowed vaues are: 1b: The LTC1760 wi not charge this battery. 0b: The LTC1760 may charge this battery if other conditions permit charging. TERMINATE_CHARGE_ALARM Bit The read ony TERMINATE_CHARGE_ALARM bit is used by the LTC1760 to determine if charging may continue. Aowed vaues are: 1b: The LTC1760 wi not charge this battery. 0b: The LTC1760 may charge this battery if other conditions permit charging. 21