Schedule. VLSI Design : Package 1

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1 Schedule /27/18 Chapter 5 (Memory devices: RAM, Clock skew) /04/18 Chapter 5 (Memory timing and clock, Testing) /11/18 Chapter 5 (Sequential machine, State graph) /18/18 (QZ1) Packaging (Flow) /25/18 Packaging (Reliability) /01/18 Midterm Examination 校慶 VLSI Design : Package 1

2 Packaging Functional: Signal and Power connections Make possible for the next level connections Provide adequate protection (mechanical and environmental) Electrical: Low parasitic Thermal Removal: Efficient heat removal Mechanical: Reliable and robust Economical: Cheap (material and manufacture throughput) VLSI Design : Package 2

3 Materials Metal -- Signal connection -- Heat conductivity Ceramic -- Expensive -- Physical characteristics Plastic -- Cheap -- Physical characteristics (heat ) VLSI Design : Package 3

4 Packaging Flow Wafer => Wafer Probe (WP) => Dicing => Bonding => Packaged Design Layout Masks Photolithographic Package Wafer Process Chips => Burn-in, Final Test (FT) VLSI Design : Package 4

5 Appearance ( DIE ) Lead Frame Chip Lead Frame VLSI Design : Package 5

6 Design Layout Masks Photolithographic Package Wafer Process Bonding Chips Wire Bonding Wire Substrate Die Pad Lead Frame VLSI Design : Package 6

7 TAB (Tape-Automated Bonding) Sprocket hole Film + Pattern Solder Bump Test pads Die Lead frame Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. Polymer film VLSI Design : Package 7

8 VLSI Design : Package 8

9 Requirement for Qualification Testing Items Conditions Criteria (Target) =================================================================================== High Temp. Operating Life 125 deg.c /V CC abs max hr Low Temp. Operating Life -40 deg.c /V CC abs max hr High Temp. Storage 150 deg.c hr Low Temp. Storage -65 deg.c [*3] hr Temp. Humidity with Bias [*1] 85 deg.c /85 %RH /V CC hr HAST [*1] 130 deg.c /85 %RH hr hr ) Temp. Cycling [*1] -65/150 deg.c r=0@100 cy (r=0@1,000 cy ) Heat Shock [*1] -65/150 deg.c r=0@15cy (r=0@100 cy ) Solderability 245 deg.c /5 sec more than 95 % soldering ESD Immunity HBM +/-2,000 V MM +/-200 V CDM +/-1,000 V as JEITA (+/-1,500 V ) Corner:+/-750 V, Other:+/-500 V as ESDA Latch-up Immunity PCIM +/-125 ma as JEITA&JEDEC [*4] (+/-150 ma ) PSOV V CC abs max. as JEITA&JEDEC Package Immunity [*2] No delamination & no cracking [*5] =================================================================================== [*1] Pre-conditioning : for SMD : Bake(125 deg.c /24 hr ) Soak(30 deg.c /70 %RH /240 hr ) Re-flow [*2] for THD : Soldering heat (260deg.C/10sec), immersed to stopper [*2] Re-flow profile : according to JEDEC profile, SMD only [*3] Renesas condition : -40 deg.c [*4] Renesas criterion : +/-100 ma [*5] Refer to next page VLSI Design : Package 9

10 Criteria for Package Immunity <<Top View>> <<Cross-section View>> Outer lead Inner lead Chip Wire Molding VLSI Design : Package 10 Acceptable delamination area

11 Cross-section Wafer backside grinding die Gold / Copper Wire Lead Frame Silver Epoxy Die Pad Coating: 10% Pb, 90% Ti Buffer for different thermal expansion coefficients VLSI Design : Package 11

12 Thermal Dissipation 15 ~ 20 % (with heat sink 40 ~ 75%) 5 ~ 10 % (about the same) 70 ~ 80 % (25 ~ 50%) VLSI Design : Package 12

13 Design Layout Masks Photolithographic Package Wafer Process Package and Heat Chips Package types: Plastic: Below 1 watt Ceramic: Below 5 watt Special: Up to 30 watt VLSI Design : Package 13

14 CIP / SIP 30 mil Min. 12mil Max 12 mil Min. PKG Thickness (Min): 2.05mm 80mil DIE 2 : 10mil DIE 1 : 10 mil 8 mil Min. L/F thickness : 0.15mm 6mil BLT 1 0.2~1.4 mil BLT 2 (1~2 mil) Might be different processes VLSI Design : Package 14

15 MCM (Multi-Chip Module) dies The module failed, if any die failed VLSI Design : Package 15

16 MCM Size and weight Better performance: Decrease loading of external signals Reduce packaging cost of individual chips Yield Problem: (will increase the cost) If Single chip faults: 5% MCM yield with 10 chips: (0.95) 10 = 60% Heat density problem VLSI Design : Package 16

17 Design Layout Masks Photolithographic Package Wafer Process Flip Chip Chips Die Solder bumps Interconnect layers Substrate VLSI Design : Package 17

18 COF D CL I A C E CL F G VLSI Design : Package 18

19 Soft PCB 穿戴式系統 VLSI Design : Package 19

20 COG VLSI Design : Package 20

21 Wafer Level Packaging VLSI Design : Package 21

22 WLP Dallas Semiconductor Wafer Level Package VLSI Design : Package 22

23 What is a 3D IC? Could be Heterogeneous Stacked 2D (Conventional) ICs VLSI Design : Package 23

24 VLSI Design : Package 24

25 Prepackaging Flow I VLSI Design : Package 25

26 Prepackaging (1) 於 wafer 正面貼上研磨膠紙避免刮傷或污染研磨 wafer 被面 VLSI Design : Package 26

27 Prepackaging (2) 撕下 wafer 正面研磨膠紙避免留下任何殘留於 wafer 被面貼上切割膠紙以避免切割時晶粒飛濺 VLSI Design : Package 27

28 Prepackaging (3) 於 wafer 正面切割 wafer 切割膠紙並未切斷照射 UV 軟化切割膠紙的黏性 VLSI Design : Package 28

29 Prepackaging Flow II VLSI Design : Package 29

30 Prepackaging (3) VLSI Design : Package 30

31 Glue Requirements Thickness: > 0.2mils 80% on each side and < 0.2mm Overflow < 2/3 of the die thickness Tilt < 2 mils Bubble area < 15% VLSI Design : Package 31

32 Example VLSI Design : Package 32

33 Die Cracking VLSI Design : Package 33

34 Reliability Different applications * Medical parts * Transportation components * 3C parts * Gifts, toys Testing items * function, timing * Thermal shock, shipping, vibration, humidity, chemical * Over Life time, burn-in VLSI Design : Package 34

35 Prepackaging- Bonding VLSI Design : Package 35

36 Gold Wire VLSI Design : Package 36

37 VLSI Design : Package 37

38 晶片邊緣與晶片座的間距 VLSI Design : Package 38

39 內部鋁墊與晶體邊緣的距離為避免金線與晶體邊緣短路, 最長線長應被考慮, 且與模流方向有關係 VLSI Design : Package 39

40 銲墊設計 VLSI Design : Package 40

41 金線弧高設定有接地線交錯鋁墊 VLSI Design : Package 41

42 Schedule /27/18 Chapter 5 (Memory devices: RAM, Clock skew) /04/18 Chapter 5 (Memory timing and clock, Testing) /11/18 Chapter 5 (Sequential machine, State graph) /18/18 (QZ1) Packaging (Flow) /25/18 Packaging (Reliability) /01/18 Midterm Examination 校慶 VLSI Design : Package 42

43 Midterm Examination Next Week!! 35% Please Bring Your Photo ID!! Covered Chapter 5 to Today s material Seats will be rearranged VLSI Design : Package 43

44 VLSI Design : Package 44

45 銲墊設計 VLSI Design : Package 45

46 VLSI Design : Package 46

47 Inner Lead Short CWT QFP64(14*14) VLSI Design : Package 47

48 Lead Frame Tape VLSI Design : Package 48

49 Lead Frame Tape VLSI Design : Package 49

50 耗材金線 99.99% Holding Clamps 熱壓版 Capillary 針頭 VLSI Design : Package 50

51 阻抗 VLSI Design : Package 51

52 Bonding Analysis VLSI Design : Package 52

53 Defects VLSI Design : Package 53

54 Defects VLSI Design : Package 54

55 Defects (Flip Chip) VLSI Design : Package 55

56 Post-packaging - Molding 175 degree C preheat VLSI Design : Package 56

57 Dejunk and Trimming Dam Bar Dejunk VLSI Design : Package 57

58 Forming VLSI Design : Package 58

59 Mark / Labling Ink Mark: Delivered the information including manufacture, product type, design team, revision, date, area, tracking code, or special codes Laser Mark: Used in tiny packages or for the environmental protection VLSI Design : Package 59

60 Pitch Center 2 center VLSI Design : Package 60

61 Bonding Options Wire Bonding: ~ 1000 connections TAB: 10 ~ couple 1000 connections Flip Chip: ~ connections VLSI Design : Package 61

62 Testing for Active/Passive Devices Active Devices: MOSs Transistors Related to function (and timing) Passive Devices: RLC Related to timing (and function) VLSI Design : Package 62

63 Design Layout Masks Photolithographic Package Wafer Process Types Chips DIP QFP SOP PGA PLCC VLSI Design : Package 63

64 VLSI Design : Package 64

65 P6: Processor + L2 cache VLSI Design : Package 65

66 Intel Itanium VLSI Design : Package 66

67 Design Layout Masks Photolithographic Package Wafer Process Chips CQFP, PQFP VLSI Design : Package 67 BGA

List of Acronyms VLSI Design : Package P-DIP PLCC QFP SOP SSOP TSOP SOJ LQFP TQFP Plactic Dual

WFBGA Ball Grid Array Thin & Fine-pitch Ball Grid Array Very-thin & Fine-pitch Ball Grid Array

Grid Array Multi Chip Module Ball Grid Array Land Grid Array Micro Chip Carrier Quad Flat

68 List of Acronyms VLSI Design : Package P-DIP PLCC QFP SOP SSOP TSOP SOJ LQFP TQFP Plactic Dual In-line Package Plastic Leaded Chip Carrier Quad Flat Pack Small Outline Package Shrink Small Outline Package Thin Small Outline Package Small Outline J-lead package Low-profile Quad Flat Pack Thin Quad Flat Pack BGA TFBGA VFBGA LBGA BCC COS BGA ubga MCM BGA LGA MCC QFN TCP WLCSP WFBGA Ball Grid Array Thin & Fine-pitch Ball Grid Array Very-thin & Fine-pitch Ball Grid Array Low-profile Ball Grid Array Bumped Chip Carrier Chip On Substrate Ball Grid Array Micro Ball Grid Array Multi Chip Module Ball Grid Array Land Grid Array Micro Chip Carrier Quad Flat No-lead Tape Carrier Package Wafer Level Chip Scale Package Very Very-thin & Fine-pitch Ball Grid Array 68

69 Different Packages TO: (before 70 s) ZIP: Zig-Zag In-Line Package SIP Single In-Line Package DIP: Dual In-Line Package (early 70 s) SOP: Small Outline Package SOJ: Small Outline J-lead PLCC: Plastic Leaded Chip Carrier QFP: Quad Flat Package (late 70 s) PGA: Pin Grid Array (mid 70 s) BGA: Ball Grid Array (mid 80 s) VLSI Design : Package 69

70 Thickness SOP/SOJ: 1.47/2.24/2.34 mm TSOP: 1.0mm PQFP: 2.0~3.4mm LQFP: 1.4mm TQFP: 1.0mm DIP: 3.3/3.8mm PGA/BGA: 0.8/0.9/1.17mm Mini BGA:0.7mm VLSI Design : Package 70

71 Cost Cost C-PGA P-PGA QFP Pin count VLSI Design : Package 71

72 Packaging Technologies VOLUME Thru Hole DIP Pin Grid Surface Mount QFP TSOP SOJ BGA Chip Scale CSP Wafer Level Stacked Die SiP YEAR VLSI Design : Package 72

73 IC Package 24L PDIP 48L PDIP PGA VLSI Design : Package 73

74 IC Package 48SOIP 84PLCC 208QFP VLSI Design : Package 74

75 IC Package 196BGA 432EBGA VLSI Design : Package 75

76 Different Technologies Through Hole Surface Mount CSP / WLP TSOP 25 mil pitch Limited by perimeter leads CSP/WLP Area array 0.8 mm to 0.5 mm Limited by substrate wiring DIP 100 mil pitch Limited by through hole spacing VLSI Design : Package 76

77 Driving Forces Mobile Computation: -- Miniaturization -- Weight Lightening -- Performance -- Larger dice -- Cost VLSI Design : Package 77

78 Delay Timing Packaging Delay Die Delay Process Tech VLSI Design : Package 78

79 Design Layout Masks Photolithographic Package Wafer Different Packaging Flow Process Chips Wafer Probe (WP) current => Dicing Bonding => Packaged => Burn-in Bonding => Packaged => Burn-in Bonding => Packaged => Burn-in Wafer Packaging => Wafer Burn-in => FT => Dicing developing, on going VLSI Design : Package 79

80 Design Layout Masks Photolithographic Package Wafer Process LC on the Package Chips VLSI Design : Package 80

81 Design Layout Masks Photolithographic Package Wafer Process RLC on the Package Chips Parameter Wirebound TAB Resistance 0.38mΩ 0.31mΩ Inductance 10nH 6.7nH Capacitance 0.21pF 0.11pF VLSI Design : Package 81

82 Design Layout Masks Photolithographic Package Wafer Electrical Characteristics Process Chips Basic characteristics Wire resistance, contact resistance Wire inductance Loading capacitance All elements of the package are included Noise imutation VLSI Design : Package 82

83 Assembly: Soldering 200 C 100 C Temp. Soak Pre-Heat + 2 ~ 3 C/sec 215 ~ 220 C Max. 120 S Max. 90 S Cool - 3 ~ 4 C/sec Time VLSI Design : Package 83

84 Flip Chip Failure Solder migration causes signals shortage or open VLSI Design : Package 84

85 Challenges Probe Density, Pin count (force and contact alignment) Testing Speed Electrical characteristics of probing pins Burn-in test OLT test Environment change Merging of wafer fabrication and packaging VLSI Design : Package 85

86 Midterm Examination Next Week!! 35% Please Bring Your Photo ID!! Covered Chapter 5 & Packaging Seats will be rearranged VLSI Design : Package 86

General Note #1 :Different kinds of IC Packages

2012/09/01 09:08 1/9 General Note #1 :Different kinds of IC s General Note #1 :Different kinds of IC s Click to expand Image Name Description & Examples Ball Grid Array aka BGA BGA packages are used to