Consideration on 100Gb/s C2M SerDes Equalizer
|
|
|
- Elaine Lucas
- 5 years ago
- Views:
Transcription
1 HSI-PR99-1 Consideration on 1Gb/s C2M SerDes Equalizer IEEE82.3ck May, 218 Hiroki Miyaoka, Toshiaki Sakai Socionext Inc. sakai_3ck_1a_518 1
2 Agenda HSI-PR Overview 2. Channel Simulation 2.1 Simulation Conditions 2.2 Channel for Simulation 2.3 Simulation Results 3. Conclusion sakai_3ck_1a_518 2
3 1. Overview HSI-PR99-1 n Feasibility of 1Gb/s C2M transmission with various channels and equalizer configurations. modulation : PAM4 # vendor module type IL (no note 1 TE OSFP -16.9dB micro-vias L2, bottom, Rx5 * dB micro-vias L2, top, Rx6 *1 3 Yamaichi "SFP"* -11.2dB no BGA footprint/breakout 4 Cisco QSFP -11.2dB "1dB" * dB "12dB" * dB "14dB" *2 * : enhanced characteristics SFP type module *1 : *2 : sakai_3ck_1a_518 3
4 HSI-PR Channel simulation 2.1 Simulation Conditions sakai_3ck_1a_518 4
5 2.1.1 Simulation Model HSI-PR99-1 victim aggressor symbol description Av, Afe, Ane Tx output amplitude : victim, FEXT, NEXT Rd single ended termination resistor Cd single ended device capacitance HFFE(f) Tx FFE transfer function S (tp), S (rp) PKG model Tx/Rx S () channel under test H Rx (f) Rx noise filter H CTLE (f) Rx CTLE transfer function η one-sided noise spec Add Dual-Dirac jitter, peak to peak Tx : before FFE Rx : considered as margin sakai_3ck_1a_518 5 σrj random jitter, RMS Tx : before FFE Rx : considered as margin
6 2.1.2 Simulation Set Up HSI-PR99-1 ü Static Channel Model Simulation ü Behavior model using MatLab ü PAM4 at 58.Gbd to see margin and other applications. (conservative) ü Jitter, noise and crosstalk are considered. ü Tx jitter, (DJ, RJ) included : Basically RJ is the same as 5G-PAM4 (conservative). ü Rx/CDR jitter (DJ, RJ) are considered as opening margin. (EW5, EH5) ü crosstalk noise in channel S-parameter ü Device noise (eta) is swept to see the effect. ü Device capacitance (Cd) = 1/6/3/fF ü Impedance are nominal : 5-ohm single ended ü T-spaced FFE ü Rx FFE parameters are set to minimize ISI. ü Rx FFE taps are swept to see effect. ü CTLE coefficients are optimized for each channel. (See back up slides.) ü PKG model is based on current design. item value unit modulation PAM4 pattern PRBS13Q baud rate 58 Gbd DJ_Tx 6 mui RJ_Tx 1 mui EOJ_Tx UI SNR_Tx 32.5 db Rt_Tx 5 ohm Tx_FFE 4/2 tap/pre Cd_Tx/Rx 1, 6, 3, ff Cp Tx/Rx extracted ff Rx FFE 5/, 25/ tap/pre Rx fr 3/4 fb Av.8 Vppd AVx 1.2 Vppd BER 1.E-5 eta 8.2E-9 V 2 /GHz DJ_Rx UI Rt_Rx 5 ohm sakai_3ck_1a_518 6
7 HSI-PR Channel simulation 2.2 Channel for Simulation sakai_3ck_1a_518 7
8 2.2 C2M : channel insertion loss HSI-PR99-1 Insertion Loss [db] CAUI-4 C2M (NRZ) Gbd PAM4 Frequency [GHz] x2 scaling 1GAUI-2 C2M (PAM4) Gbd CAUI-4 C2M 5GAUI-1 C2M "1GAUI-1 C2M" scaled 1GAUI-1 C2M (PAM4) Gbd If PAM4 modulation is selected, 1dB~12dB target insertion loss at Nyquist frequency ( GHz, scaled frequency) is an option. sakai_3ck_1a_518 8
9 HSI-PR Channel Configuration (#1/#2 TE Rx5/Rx6) TE : micro via OSFP Connector footprint is considered. No PKG footprint - With vias/footprint for 2.4mm connector No PKG footprint - With vias/footprint for 2.4mm connector added PKG model host (Tx) : 27mm PKG module (Rx) : 12mm PKG both design extracted No on-module AC coupling capacitors. sakai_3ck_1a_518 9
![2.2.1 Channel Characteristics (#1,TE Rx5) SDD21 SDD22-8.2dB HSI-PR99-1 S-parameter [db] -2-4 SDD11-12.2dB -16.9dB @29GHz scaled 1GAUI-1 C2M SDD21-6 PSXT -48.](/docs-images/93/111654931/images/10-1.jpg "2dB @29GHz -7 1 2 3 4 5 Frequency [GHz] TE : micro-vias L2 route bottom row victim, Rx5 http://www.ieee82.org/3/1gel/public/18_1/tracy_1gel_1a_118.pdf http://www.ieee82.org/3/1gel/public/tools/c2m/tracy_1gel_6_118.")
10 2.2.1 Channel Characteristics (#1,TE Rx5) SDD21 SDD22-8.2dB HSI-PR99-1 S-parameter [db] -2-4 SDD dB scaled 1GAUI-1 C2M SDD21-6 PSXT Frequency [GHz] TE : micro-vias L2 route bottom row victim, Rx5 sakai_3ck_1a_518 1
![2.2.1 Channel Characteristics (#2, TE Rx6) SDD21 SDD22-8.3dB HSI-PR99-1 S-parameter [db] -2-4 SDD11-16.8dB -16.3dB @29GHz scaled 1GAUI-1 C2M SDD21-6 PSXT -53.](/docs-images/93/111654931/images/11-1.jpg "6dB @29GHz -7 1 2 3 4 5 Frequency [GHz] TE : micro-vias L2 route top row victim, Rx6 http://www.ieee82.org/3/1gel/public/18_1/tracy_1gel_1a_118.pdf http://www.ieee82.org/3/1gel/public/tools/c2m/tracy_1gel_6_118.")
11 2.2.1 Channel Characteristics (#2, TE Rx6) SDD21 SDD22-8.3dB HSI-PR99-1 S-parameter [db] -2-4 SDD dB scaled 1GAUI-1 C2M SDD21-6 PSXT Frequency [GHz] TE : micro-vias L2 route top row victim, Rx6 sakai_3ck_1a_518 11
12 2.2.1 Channel Configuration (#3 Yamaichi) HSI-PR99-1 Enhanced SFP (small form factor pluggable) type connector (27mm PKG) (12mm PKG) No PKG footprint No vias Connector footprint with vias back-drilled,.254mm stub No PKG footprint No vias added PKG model host (Tx) : 27mm PKG module (Rx) : 12mm PKG both design extracted No on-module AC coupling capacitors. - On-die (receiver) AC coupling capacitors. sakai_3ck_1a_518 12
13 2.2.1 Channel Characteristics (#3 Yamaichi) - "enhanced SFP" HSI-PR99-1 Courtesy of Yamaichi Electronics Co., Ltd. SDD21 S-parameter [db] -2-4 SDD11-2.1dB SDD22-4.dB -6 PSXT scaled 1GAUI-1 C2M SDD21 PSXT Frequency [GHz] sakai_3ck_1a_518 13
14 2.2.1 Channel Configuration (#4,5,6 Cisco) HSI-PR99-1 QSFP SMT connector (27mm PKG) (12mm PKG) PKG footprint included Connector footprint is considered with vias. No PKG footprint - test fixture footprint and vias included No on-module AC coupling capacitors.(?) added PKG model host (Tx) : 27mm PKG module (Rx) : 12mm PKG both design extracted sakai_3ck_1a_
15 2.2.1 Channel Characteristics (#4, Cisco_1dB) QSFP56 SDD11-8.4dB HSI-PR99-1 Courtesy of Yamaichi Electronics Co., Ltd. SDD21 S-parameter [db] SDD dB PSXT scaled 1GAUI-1 C2M SDD Frequency [GHz] sakai_3ck_1a_518 15
16 2.2.1 Channel Characteristics (#5, Cisco_12dB) QSFP56 SDD11-8.4dB HSI-PR99-1 Courtesy of Yamaichi Electronics Co., Ltd. SDD21 S-parameter [db] SDD22-2.1dB PSXT scaled 1GAUI-1 C2M SDD Frequency [GHz] sakai_3ck_1a_518 16
17 2.2.1 Channel Characteristics (#6, Cisco_14dB) HSI-PR99-1 SDD11-7.9dB Courtesy of Yamaichi Electronics Co., Ltd. SDD21 S-parameter [db] SDD22-2.7dB PSXT scaled 1GAUI-1 C2M SDD Frequency [GHz] sakai_3ck_1a_518 17
![2.2.2 PKG Characteristics HSI-PR99-1 Designed PKG models are used. S-parameter [db] SDD21: -4.](/docs-images/93/111654931/images/18-1.jpg "81dB @28GHz SDD22: -11.")
![1dB @28GHz -1-2 -3-4 -5 SDD22 SDD11 28GHz SDD21 Frequency [GHz] simulated 27mm-trace 1 2 3 4 5 S-parameter](/docs-images/93/111654931/images/18-2.jpg "[db] -1-2 -3-4 SDD21: -2.4dB @28GHz SDD22: -12.")
18 2.2.2 PKG Characteristics HSI-PR99-1 Designed PKG models are used. S-parameter [db] SDD21: SDD22: SDD22 SDD11 28GHz SDD21 Frequency [GHz] simulated 27mm-trace S-parameter [db] SDD21: SDD22: SDD22 SDD11 SDD21 Frequency [GHz] simulated 12mm-trace -5 28GHz note : No xtalk is considered in these PKG models. 18 sakai_3ck_1a_518 18
19 HSI-PR Channel simulation 2.3 Simulation Results sakai_3ck_1a_518 19
20 2.3.1 Simulation Summary (channel, device cap Cd) HSI-PR99-1 EW5 [mui] Rx5_EW5 Rx6_EW5 Y_EW5 EW5 vs Cd #1 #2 #3 EW5 > 1mUI Cd [ff] EH5 [mv] Rx5_EH5 Rx6_EH5 Y_EH5 EH5 > 2mV #1 EH5 vs Cd #2 # Cd [ff] item unit #121 #128 #132 #136 #143 #148 #152 #156 #16 channel #1 TE/Rx5 #2 TE/Rx6 #3 Yamaichi Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 2
21 2.3.1 Simulation Summary (channel, device cap Cd) HSI-PR EW5 vs Cd EW5 > 1mUI EH5 vs Cd EW5 [mui] dB_EW5 12dB_EW5 14dB_EW sakai_3ck_1a_ dB_EH5 12dB_EH5 14dB_EH Cd [ff] item unit #164 #167 #172 #176 #183 #188 #192 #196 #23 #28 #212 #216 channel #4 Cisco_1dB #5 Cisco_12dB #6 Cisco_14dB Tx/Rx Cd ff EW 5 EH 5 Cd [ff] #6 #4 #5 EH5 [mv] EH5 > 2mV mid mui low mid mv low #4 #6 #5
22 2.3.1 Simulation Summary (more Rx FFE taps) HSI-PR99-1 EW5 [mui] 12 EW5 vs Rx_FFE_taps EH5 [mv] 8 EH5 vs Rx_FFE_taps EW5 > 1mUI #1 #2 Rx5_EW5 Rx6_EW #2 #1 EH5 > 2mV Rx5_EH5 Rx6_EH Rx FFE taps Rx FFE taps item unit #137 #138 #139 #14 #157 #158 #159 #16 #121 #122 #123 #124 #141 #142 #143 #144 Tx/Rx Cd ff 1 channel #1 TE/Rx5 #2 TE/Rx6 #1 TE/Rx5 #2 TE/Rx6 Rx FFE tap/pre 25/ 5/ EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 22
23 2.3.1 Simulation Summary (more Rx FFE taps) HSI-PR99-1 FFE tap coefficient Rx5_25 Rx6_25 Rx5_5 Rx6_5.4.2 bump-ball reflection Rx : 12mm PKG. -.2 c(-2) c(-1) c() c(1) ffe() ffe(1) ffe(2) ffe(3) ffe(4) ffe(5) ffe(6) ffe(7) ffe(8) ffe(9) ffe(1) ffe(11) ffe(12) ffe(13) ffe(14) ffe(15) ffe(16) ffe(17) ffe(18) ffe(19) ffe(2) ffe(21) ffe(22) ffe(23) ffe(24) -.4 Tx FFE taps Rx FFE taps - No major reflection is seen between bump and ball. - Reduction of Cd, Cp helps some, but not significant. sakai_3ck_1a_518 23
24 HSI-PR Conclusion sakai_3ck_1a_518 24
25 3. Conclusion (1/2) HSI-PR With #3 C2M channel, 58Gbd PAM4 transmission with channel seems feasible using 4-tap Tx FFE and 5-tap Rx FFE. (From host to module direction) - For 82.3ck C2M applications, will have some margin with this channel. Need further investigation. - Current model does not include PKG ball breakout effect. - From module to host direction, host Rx can have stronger equalizer (eg. more FFE taps), so it will not be a major issue. - For C2M module side receiver (Rx), equalization is quite tough, with limited number of taps, considering power and area constraints. 2. With other channel, openings become worse. - Need to reduce crosstalk, mainly. 3. PKG characteristics affect performance significantly. - IL : 8dB (5dB host, 3dB module), comparing to channel IL (13~15dB) - Need to improve. 25 sakai_3ck_1a_518 25
26 3. Conclusion (2/2) 4. Equalizer optimization in simulation is; 1 st : host Tx FFE 2 nd : module Rx CTLE/FFE - In actual implementation, following options may be required. (1) Feedback from module to host, to determine host Tx FFE coefficient. (2) Preset Tx FFE coefficient based on host channel characteristics, using simulation results 26 HSI-PR Performance, power and area in real Si implementation have to be considered. - It is a trade off issue both channel (including PKG) and SerDes design. 6. Further investigation needed. - Device parameters (Cd in COM) - Equalization - PKG parameters (Cp in COM) - Other Channel models, parameters sakai_3ck_1a_518 26
27 Thank you!
28 HSI-PR99-1 backup slides 28 sakai_3ck_1a_518 28
29 A1.1 Simulation Summary (#1, TE micro-via/rx5) HSI-PR99-1 EW5 [mui] item unit #121 #122 #123 #124 #125 #126 #127 #128 #129 #13 #131 #132 #133 #134 #135 #136 c(-2) Tx FFE c(-1) c() c(1) Tx/Rx Cd ff p1_hf p2_hf CTLE z_hf p_lf Rx z_lf ffe() ffe(1) FFE ffe(2) ffe(3) ffe(4) EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 EW5 vs Cd Cd [ff] Rx5_EW5 Rx6_EW5 EW5 > 1mUI 29 EH5 [mv] EH5 > 2mV EH5 vs Cd Rx5_EH5 Rx6_EH Cd [ff]
30 A1.2 Simulation Summary (#1, EW5, TE micro-via/rx5) HSI-PR99-1 EW5 > 1mUI EW5 [mui] EW5_ EW5_mid EW5_low Cd=1fF Cd=6fF EW5 Cd=3fF Cd=fF item unit #121 #122 #123 #124 #125 #126 #127 #128 #129 #13 #131 #132 #133 #134 #135 #136 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 3
31 A1.3 Simulation Summary (#1, EH5, TE micro-via/rx5) HSI-PR99-1 EH5 [mv] EH EH5_ EH5_mid EH5_low Cd=3fF Cd=fF 6 Cd=6fF 5 4 Cd=1fF EH5 > 2mV item unit #121 #122 #123 #124 #125 #126 #127 #128 #129 #13 #131 #132 #133 #134 #135 #136 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 31
32 A2.1 Simulation Summary (#2, TE micro-via/rx6) HSI-PR99-1 EW5 [mui] item unit #141 #142 #143 #144 #145 #146 #147 #148 #149 #15 #151 #152 #153 #154 #155 #156 c(-2) Tx FFE c(-1) c() c(1) Tx/Rx Cd ff p1_hf p2_hf CTLE z_hf p_lf Rx z_lf ffe() ffe(1) FFE ffe(2) ffe(3) ffe(4) EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 EW5 vs Cd Cd [ff] Rx5_EW5 Rx6_EW5 EW5 > 1mUI 32 EH5 [mv] EH5 > 2mV EH5 vs Cd Rx5_EH5 Rx6_EH Cd [ff]
33 A2.2 Simulation Summary (#2, EW5, TE micro-via/rx6) HSI-PR99-1 EW5 > 1mUI EW5 [mui] EW5_ EW5_mid EW5_low Cd=1fF Cd=6fF EW5 Cd=3fF Cd=fF item unit #141 #141 #142 #142 #143 #143 #144 #144 #145 #145 #146 #146 #147 #147 #148 #148 #149 #149 #15 #15 #151 #151 #152 #152 #153 #153 #154 #154 #155 #155 #156 #156 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 33
34 A2.3 Simulation Summary (#2, EH5, TE micro-via/rx6) HSI-PR99-1 EH5 [mv] 9 EH5 Cd=3fF Cd=fF 8 EH5_ EH5_mid Cd=6fF 7 EH5_low 6 Cd=1fF 5 4 EH5 > 2mV item unit #141 #142 #143 #144 #145 #146 #147 #148 #149 #15 #151 #152 #153 #154 #155 #156 #156 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 34
35 A3 Simulation Summary (#3, EW5, EH5, Yamaichi) HSI-PR99-1 item unit #16 #17 c(-2).6.7 c(-1) Tx FFE c().55.6 c(1) Tx/Rx Cd ff 1 12 Rx z_lf.3.3 ffe() p1_hf CTLE z_hf p2_hf p_lf ffe(1) FFE ffe(4) ffe(2) ffe(3) EW6 mid mui low EH6 mid mv 4 41 low EW5 mid mui low EH5 mid mv low EW4 mid mui low EH4 mid mv 82 8 low EW5 [mui] EH5 [mv] 35 EW5 Cd=1fF #16 #17 EH5 Cd=1fF #16 #17 EW5_ EW5_mid EW5_low EW5 > 1mUI EH5_ EH5_mid EH5_low EH5 > 2mV sakai_3ck_1a_518 35
36 A4.1 Simulation Summary (#4, Cisco 1dB) HSI-PR99-1 EW5 [mui] item unit #161 #162 #163 #164 #165 #166 #167 #168 #169 #17 #171 #172 #173 #174 #175 #176 c(-2) Tx FFE c(-1) c() c(1) Tx/Rx Cd ff p1_hf p2_hf CTLE z_hf p_lf Rx z_lf ffe() ffe(1) FFE ffe(2) ffe(3) ffe(4) EW5 mid mui low EH5 mid mv low dB_EW5 12dB_EW5 14dB_EW sakai_3ck_1a_518 EW5 vs Cd Cd [ff] EW5 > 1mUI EH5 [mv] EH5 > 2mV EH5 vs Cd 1dB_EH5 12dB_EH5 14dB_EH Cd [ff]
37 A4.2 Simulation Summary (#4, EW5, Cisco 1dB) HSI-PR99-1 EW5 > 1mUI EW5 [mui] EW5_ EW5_mid EW5_low Cd=6fF EW5 Cd=3fF Cd=fF 8 Cd=1fF item unit #161 #162 #163 #164 #165 #166 #167 #168 #169 #17 #171 #172 #173 #174 #175 #176 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 37
38 A4.3 Simulation Summary (#4, EH5, Cisco 1dB) HSI-PR99-1 EH5 [mv] 12 1 EH5_ EH5_mid EH5_low EH5 Cd=3fF Cd=fF 8 Cd=1fF Cd=6fF 6 4 EH5 > 2mV 2 item unit #161 #162 #163 #164 #165 #166 #167 #168 #169 #17 #171 #172 #173 #174 #175 #176 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 38
39 A5.1 Simulation Summary (#5, Cisco 12dB) HSI-PR99-1 EW5 [mui] item unit #181 #182 #183 #184 #185 #186 #187 #188 #189 #19 #191 #192 #193 #194 #195 #196 c(-2) Tx FFE c(-1) c() c(1) Tx/Rx Cd ff p1_hf p2_hf CTLE z_hf p_lf Rx z_lf ffe() ffe(1) FFE ffe(2) ffe(3) ffe(4) EW5 mid mui low EH5 mid mv low dB_EW5 12dB_EW5 14dB_EW sakai_3ck_1a_518 EW5 vs Cd Cd [ff] EW5 > 1mUI EH5 [mv] EH5 > 2mV EH5 vs Cd 1dB_EH5 12dB_EH5 14dB_EH Cd [ff]
![A5.2 Simulation Summary (#5, EW5, Cisco 12dB) HSI-PR99-1 EW5 [mui] 14 12 EW5_u pp EW5_ mid EW5 Cd=3fF Cd=fF EW5 > 1mUI 1 Cd=6fF 8 Cd=1fF 6 4](/docs-images/93/111654931/images/40-2.jpg "2 item unit #181 #182 #183 #184 #185 #186 #187 #188 #189 #19 #191 #192 #193 #194 #195 #196 Tx/Rx Cd ff 1 6 3 51 48 39 54 66 67 66 68 79 85 84")
40 A5.2 Simulation Summary (#5, EW5, Cisco 12dB) HSI-PR99-1 EW5 [mui] EW5_u pp EW5_ mid EW5 Cd=3fF Cd=fF EW5 > 1mUI 1 Cd=6fF 8 Cd=1fF item unit #181 #182 #183 #184 #185 #186 #187 #188 #189 #19 #191 #192 #193 #194 #195 #196 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 4
41 A5.3 Simulation Summary (#5, EH5, Cisco 12dB) HSI-PR99-1 EH5 [mv] 9 EH5 Cd=fF 8 7 EH5_ EH5_mid EH5_low Cd=6fF Cd=3fF 6 EW5 [mui] 5 4 Cd=1fF 3 EH5 > 2mV 2 1 item unit #181 #182 #183 #184 #185 #186 #187 #188 #189 #19 #191 #192 #193 #194 Tx/Rx Cd ff #195 # EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 41
42 A6.1 Simulation Summary (#6, Cisco 14dB) HSI-PR99-1 EW5 [mui] item unit #21 #22 #23 #24 #25 #26 #27 #28 #29 #21 #211 #212 #213 #214 #215 #216 c(-2) Tx FFE c(-1) c() c(1) Tx/Rx Cd ff p1_hf p2_hf CTLE z_hf p_lf Rx z_lf ffe() ffe(1) FFE ffe(2) ffe(3) ffe(4) EW5 mid mui low EH5 mid mv low dB_EW5 12dB_EW5 14dB_EW sakai_3ck_1a_518 EW5 vs Cd Cd [ff] EW5 > 1mUI EH5 [mv] EH5 > 2mV EH5 vs Cd 1dB_EH5 12dB_EH5 14dB_EH Cd [ff]
![A6.2 Simulation Summary (#6, EW5, Cisco 14dB) HSI-PR99-1 EW5 [mui] 14 EW5 12 EW5_ EW5_mid EW5 > 1mUI 1 8 EW5_low Cd=6fF Cd=3fF Cd=fF 6](/docs-images/93/111654931/images/43-1.jpg "Cd=1fF 4 2 item unit #21 #22 #23 #24 #25 #26 #27 #28 #29 #21 #211 #212 #213 #214 Tx/Rx Cd ff 1 6 3 #215 #216 14 19 53 61 51 49 68 68 68")
43 A6.2 Simulation Summary (#6, EW5, Cisco 14dB) HSI-PR99-1 EW5 [mui] 14 EW5 12 EW5_ EW5_mid EW5 > 1mUI 1 8 EW5_low Cd=6fF Cd=3fF Cd=fF 6 Cd=1fF 4 2 item unit #21 #22 #23 #24 #25 #26 #27 #28 #29 #21 #211 #212 #213 #214 Tx/Rx Cd ff #215 # EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 43
44 A6.3 Simulation Summary (#6, EH5, Cisco 14dB) HSI-PR99-1 EH5 [mv] 9 EH5 8 7 EH5_ EH5_mid EH5_low Cd=3fF Cd=fF 6 5 Cd=6fF 4 Cd=1fF 3 EH5 > 2mV 2 1 item unit #21 #22 #23 #24 #25 #26 #27 #28 #29 #21 #211 #212 #213 #214 #215 #216 Tx/Rx Cd ff EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 44
45 A7.1 Simulation Summary (Rx FFE taps, TE micro-via/rx5/rx6) HSI-PR99-1 item unit #137 #138 #139 #14 #157 #158 #159 #16 #121 #122 #123 #124 #141 #142 #143 #144 c(-2) Tx FFE c(-1) c() c(1) Tx/Rx Cd ff 1 channel TE/Rx5 TE/Rx6 TE/Rx5 TE/Rx6 p1_hf p2_hf CTLE z_hf p_lf z_lf tap/pre 25/ 5/ ffe() ffe(1) ffe(2) ffe(3) ffe(4) ffe(5) Rx ffe(6) ffe(7) ffe(8) ffe(9) ffe(1) FFE ffe(11) ffe(12) ffe(13) ffe(14) ffe(15) ffe(16) ffe(17) ffe(18) ffe(19) ffe(2) ffe(21) ffe(22) ffe(23) ffe(24) EW5 mid mui low EH5 mid mv sakai_3ck_1a_518 low
46 A7.2 Simulation Summary (EW5, Rx FFE taps, TE micro-via/rx5/rx6) HSI-PR99-1 EW5 [mui] Rx5, FFE 25/ 12 Rx6, FFE 25/ EW5 EW5_ EW5_mid EW5_low EW5 > 1mUI 1 8 Rx5, FFE 5/ Rx6, FFE 5/ item unit #137 #138 #139 #14 #157 #158 #159 #16 #121 #122 #123 #124 #141 #142 #143 #144 channel TE/Rx5 TE/Rx6 TE/Rx5 TE/Rx6 Rx FFE tap/pre 25/ 5/ EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 46
47 A7.3 Simulation Summary (EH5, Rx FFE taps, TE micro-via/rx5/rx6) HSI-PR99-1 EH5 [mv] 8 Rx5, FFE 25/ Rx6, FFE 25/ EH5 EH5_ EH5_mid EH5_low Rx5, FFE 5/ Rx6, FFE 5/ 4 EH5 > 2mV item unit #137 #138 #139 #14 #157 #158 #159 #16 #121 #122 #123 #123 #124 #124 #141 #141 #142 #142 #143 #143 #144 #144 channel TE/Rx5 TE/Rx6 TE/Rx5 TE/Rx6 Rx FFE tap/pre 25/ 5/ EW5 mid mui low EH5 mid mv low sakai_3ck_1a_518 47
48 B- Rx FFE output HSI-PR simulation results 4 log 1 (BER) bathtub curve log1(ber) Colors are corresponding to each line BER. Vdiff [mv] log 1 (BER) bathtub curve time [UI] 1UI = sakai_3ck_1a_518 48
49 B-1 Simulation Result (#121) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #121 #128 #132 #136 baud rate Gbd 58 type #1, TE/Rx5 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 49
50 B-2 Simulation Result (#128) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #121 #128 #132 #136 baud rate Gbd 58 type #1, TE/Rx5 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 5
51 B-3 Simulation Result (#132) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #121 #128 #132 #136 baud rate Gbd 58 type #1, TE/Rx5 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 51
52 B-4 Simulation Result (#136) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #121 #128 #132 #136 baud rate Gbd 58 type #1, TE/Rx5 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 52
53 B-5 Simulation Result (#143) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #143 #148 #152 #156 baud rate Gbd 58 type #2, TE/Rx6 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 53
![B-6 Simulation Result (#148) HSI-PR99-1 Vdiff [mv] 5 25-25 -5 log 1 (BER) -8-7 -6-5 -4-3 -2-1 -1 1 time [UI] 54-1 -2-3 -4-5 -6-7 -8 log1(ber) log 1 (BER) -1-2 -3-4 -5-6 item unit #143 #148 #152 #156](/docs-images/93/111654931/images/54-1.jpg "baud rate Gbd 58 type #2, TE/Rx6 IL no PKG*1 db 16.3 @29GHz w/ PKG *2 db 26.3 25.2 24.5 24.1 ICN mv.55.59.61.62 FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.")
54 B-6 Simulation Result (#148) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #143 #148 #152 #156 baud rate Gbd 58 type #2, TE/Rx6 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 54
55 B-7 Simulation Result (#152) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #143 #148 #152 #156 baud rate Gbd 58 type #2, TE/Rx6 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 55
56 B-8 Simulation Result (#156) HSI-PR99-1 Vdiff [mv] log 1 (BER) time [UI] log1(ber) log 1 (BER) item unit #143 #148 #152 #156 baud rate Gbd 58 type #2, TE/Rx6 IL no PKG*1 db w/ PKG *2 db ICN mv FFE tap/pre 4/2 Tx RJrms mui 1 SNR db 32.5 PKG trace mm 27/12 Tx/ Cd ff Rx Cp ff extracted CTLE HF/LF 2p-1z/1p-1z eta V 2 /GHz 8.2E-9 Rx fr x fb GHz 3/4 FFE tap/pre 5/ RJrms mui mid mui EW5 low EH5 mid mv low channel EW5 > 1mUI EH5 > 2mV *1 : raw *2 : fitted sakai_3ck_1a_518 56
57
100Gb/s C2M Channel Simulation
HSI-PR1-1 1Gb/s C2M Channel Simulation IEEE82.3ck July, 218 Hiroki Miyaoka, Toshiaki Sakai Socionext Inc. sakai_3ck_1a_718 1 Agenda HSI-PR1-1 1. Overview 2. C2M Channel Simulation 2.1 Simulation Conditions
Trace and Chassis Tolerances vs. COM Andy Zambell November 2018
Trace and Chassis Tolerances vs. COM Andy Zambell November 2018 zambell_3ck_01_1118 Page 1 Purpose The purpose of this presentation is to see how varying trace impedance and connector mating due to chassis
400GAUI-8 C2M TP1a Eye Measurement Data
400GAUI-8 C2M TP1a Eye Measurement Data Jane Lim, Cisco Pirooz Tooyserkani, Cisco 09/09/2017 IEEE P802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force. 1 Wei Yao Liehui Ren Matt Traverso Marco Mazzini Upen
Current COM spec is broken between channel and Rx (comment #32)
Current COM spec is broken between channel and Rx (comment #32) Yasuo Hidaka Fujitsu Laboratories of America, Inc. IEEE P802.3cd Task Force, New Orleans, LA, May 22-23, 2017 IEEE P802.3cd 50/100/200GbE
Comparison of Signaling and Equalization Schemes
Comparison of Signaling and Equalization Schemes NRZ, Duobinary, and PR4 Joe Caroselli and Cathy Liu High Speed Interface Systems Architecture LSI Logic March 15,2005 1 Introduction Overview of signaling
MultiGig RT Product Family Slot Pitch Density Data Rate RT lines/inch Gbps lines/inch Gbps RT lines/inch 6.50 Gbp
1 MultiGig RT Assembly! # # "$#! MultiGig RT Product Family Slot Pitch Density Data Rate RT1 0.8 113 lines/inch 3.125 Gbps 1.0 141 lines/inch 3.125 Gbps RT2 0.8 85 lines/inch 6.50 Gbps* 1.0 113 lines/inch
Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package
Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package Ozgur Misman, Mike DeVita, Nozad Karim, Amkor Technology, AZ, USA 1900 S. Price Rd, Chandler,
Allegro Sigrity SI / PI Overview
Allegro Sigrity SI / PI Overview Brad Griffin Allegro Product Marketing February, 2015 1 2012 Cadence Design Systems, Inc. All rights reserved. Agenda Allegro Sigrity Signal Integrity Solutions Allegro
IBIS Connector Models: Facts vs. Fiction
IBIS Connector Models: Facts vs. Fiction TecPreview Jim Nadolny Corey Kimble Slide 1 Outline Background Samtec Model Requests Simulation Tools Connector Models SPICE vs. IBIS vs. S-parameter Syntax differences
Optical Specifications of SMF PMDs Study. 400 Gb/s Ethernet Task Force IEEE Interim Meeting 8-10 September 2014 Ottawa, Canada Chris Cole
Optical Specifications of SMF PMDs Study 400 Gb/s Ethernet Task Force IEEE 802.3 Interim Meeting 8-10 September 2014 Ottawa, Canada Chris Cole Finisar Contributors Gilles Denoyer Bernd Huebner Jonathan
TIDA USB Type-C TM HDD with USB Power Delivery Reference Design. BERTScope USB 3.0 Receiver Test
Page 1 of8 Test Report December 2015 TIDA-00882 USB Type-C TM HDD with USB Power Delivery Reference Design BERTScope USB 3.0 Receiver Test RECEIVER TEST RESULTS 11/12/2015 08:51:18 Identification Name:
U/FTP vs F/UTP CAT6A LAN Cables June 2016
U/FTP vs F/UTP CAT6A LAN Cables June 2016 Preface Shielded cabling systems are strongly recommended for category 6A (Class EA) installations, but the user still has to choose between two optional shielding
Coreless Packaging Technology for High-performance Application
62 nd ECTC San Diego, CA: May 29 June 1, 2012 Coreless Packaging Technology for High-performance Application Corp Advanced LSI Assembly Product Department Analog LSI Bussiness Division Semiconductor Business
UNISONIC TECHNOLOGIES CO., LTD UC5301
UNISONIC TECHNOLOGIES CO., LTD UC5301 SWITCHED-CAPACITOR VOLTAGE INVERTERS DESCRIPTION The UTC UC5301 is an unregulated charge-pump voltage inverter. It can be used to generate a negative supply from positive
AMX8X5 Using Low-Cost Ceramic Capacitors for RTC Backup Power
1. Introduction This application note describes the use of low-cost capacitors as a backup power source for the real time clock (RTC) families. The ultra-low power consumption of the enables designers
100G PAM PMD Observations
100G PAM PMD Observations Next Generation 100Gb/s Ethernet Optics Study Group IEEE 802.3 Plenary Session Waikoloa, HI 12-15 March 2012 Chris Cole chris.cole@finisar.com Outline 100G PAM & LR4 Block Diagrams
Tyre Endurance/Low Pressure Test
Tyre Endurance/Low Pressure Test Test versions implemented by US DOT in 1960s (FMVSS 109) for use on passenger car tyres. Updated in June 2003 (FMVSS 139) to more closely represent real world worst-case
RV-1805-C3 Application Note
Application Note Date: January 2015 Revision N : 1.3 1/11 Headquarters: Micro Crystal AG Mühlestrasse 14 CH-2540 Grenchen Switzerland Tel. Fax Internet Email +41 32 655 82 82 +41 32 655 82 83 www.microcrystal.com
SPECIFICATION. Surface Acoustic Wave Filter. SMS-51-L-SFT FX-66 DATE June 30, 2014 WISOL. Byun, Kyung-Su. User WISOL CO., LTD.
SPECIFICATION Surface Acoustic Wave Filter USER USER PART No. SEMCO PART No. DOC. No. DATE June 30, 2014 REVISION Preliminary WISOL Kim, Kyung-Sik Byun, Kyung-Su Choi. Jae hyeong ISSUED BY APPROVED BY
Item: Type: SAW Resonator TO39, F11, F12. Optional
SPECIFICATION Item: Type: TO39, F11, F12 Optional Scope This specification shall cover the characteristics of 1-port SAW resonator. TO39 F11 F12 The 1-port is designed to be the frequency control element
Implications of. Digital Control. a High Performance. and Management for. Isolated DC/DC Converter. Technical Paper 003.
Implications of Digital Control and Management for a High Performance Isolated DC/DC Converter Technical Paper 003 March 2007 Digital control implemented in an isolated DC/DC converter provides equal or
SPECIFICATION. Surface Acoustic Wave Filter SFX897WZ102 WISOL. hong, Sung-Su. User WISOL CO., LTD.
SPECIFICATION Surface Acoustic Wave Filter USER USER PART No. WISOL PART No. DOC. No. SMS-51-L-SFT D0-67 DATE July 8, 2013 REVISION 001 WISOL Kim, Jong-Hwan hong, Sung-Su Chun, Hun-Chul ISSUED BY CHECKED
10GBASE-LRM over 300m of FDDI-grade Fiber
GBASE-LRM over m of FDDI-grade Fiber Experimental & Simulation Results Jonathan King Sudeep Bhoja Ottawa Sept. 4 Big Bear Networks, Inc. Outline System Simulations Description of Model Results (CL & OSL)
Meeting product specifications
Optimisation of a diesel hydrotreating unit A model based on operating data is used to meet sulphur product specifications at lower DHT reactor temperatures with longer catalyst life Jose Bird Valero Energy
A fully integrated 3 phase IGBT switching assembly with a very low loss DC Link Capacitor -- Ed Sawyer, SBE Inc. Scott Leslie, Powerex Inc.
A fully integrated 3 phase IGBT switching assembly with a very low loss DC Link Capacitor -- Ed Sawyer, SBE Inc. Scott Leslie, Powerex Inc. Thermal characteristics of the Power Ring shape SBE has conducted
Implications of Digital Control and Management for a High Performance Isolated DC/DC Converter
MPM-07:000199 Uen Rev A Implications of Digital Control and Management for a High Performance Isolated DC/DC Converter March 2007 Technical Paper Digital control implemented in an isolated DC/DC converter
1PPoDL system Requirements Discussion
1PPoDL system Requirements Discussion IEEE802.3bu Task Force Jan 2014 Indian Wells, CA Yair Darshan Microsemi ydarshan@microsemi.com Objectives Discussing 1PPoDL system Requirements based on objectives,
Implications of. Digital Control. a High Performance. and Management for. Isolated DC/DC Converter. Technical Paper 003.
Implications of Digital Control and Management for a High Performance Isolated DC/DC Converter Technical Paper 003 March 2007 Digital control implemented in an isolated DC/DC converter provides equal or
Features. Isolation PFM. Block Diagram
Features SMT Technology 2:1 Input Range Efficiency up to 85 I/O Isolation 00 Remote on/off Control Short Circuit Protection MTBF > 1,000,000 Hours RoHS Compliant MSL2 (Moisture Sensitivity Level) per IPC/JEDEC
2W, Low Cost DIP, Dual Output DC/DC Converters
2W, Low Cost DIP, Dual Output DC/DC s Key Features Low Cost 500 Isolation MTBF > 0,000 Hours mv P-P Ripple and Noise Input 12 Output {15 Temperature Performance -25] to +71] Short Circuit Protection UL
Development and Operational Advantages of a Solid State Circuit Breaker with Current Limiting
Development and Operational Advantages of a Solid State Circuit Breaker with Current Limiting Breaker Technology Operational Advantages Development Schedule Dave Richardson, Ph.D.,P.E. Powell Power Electronic
CX = CX-3 BX = BX-3 CXV2 = CX-3
CX-3/BX-3 PROGRAM PARAMETER CX = CX-3 BX = BX-3 CXV2 = CX-3 version2 "X" : unavailable "/" : reserved No. PARAMETERS DATA(Hex) : VALUE CX BX CXV2 00 PROGRAM NAME (Head) 20-7E : ' ' - '~' 11 PROGRAM NAME
INTELLIGENT DC MICROGRID WITH SMART GRID COMMUNICATIONS: CONTROL STRATEGY CONSIDERATION AND DESIGN
INTELLIGENT DC MICROGRID WITH SMART GRID COMMUNICATIONS: CONTROL STRATEGY CONSIDERATION AND DESIGN Presented by: Amit Kumar Tamang, PhD Student Smart Grid Research Group-BBCR aktamang@uwaterloo.ca 1 Supervisor
New SMA Launch Model. Michael s Work on the SMA Launch as of 2/04/2009
New SMA Launch Model Michael s Work on the SMA Launch as of 2/04/2009 Table of Contents The Latest Model Michael Enders recently received new information with regards to the viability of the SMA Launch
Rx antennas at IV3PRK: detuning the TX Antenna
Rx antennas at IV3PRK: detuning the TX Antenna Using the sectionalizing tower method by W8JI by Pierluigi Luis Mansutti IV3PRK In the 1 st part of my modeling study on the Flags upgrade, from the original
ELECTRONICS DIVISION. METRAL 2mm HIGH-SPEED CONNECTORS 1000 SERIES, 2000 SERIES, 4000 SERIES
ELECTRONICS DIVISION METRAL 2mm HIGH-SPEED CONNECTORS 1000 SERIES, 2000 SERIES, 4000 SERIES FCI: SETTING THE STANDARD FOR CONNECTORS With operations in 30 countries, FCI is a leading manufacturer of connects.
Experiment and Modeling Study on Battery Performance
, pp.4956 http://dx.doi.org/10.14257/astl.2016. Experiment and Modeling Study on Battery Performance Shuang Du a, Ruijuan Guo b, Shangyuan Sun c College of Engineering Technology, Jilin Agricultural University,
ISOLATED DC-DC Converter EC2SB SERIES APPLICATION NOTE
ISOLATED DC-DC Converter EC2SB SERIES APPLICATION NOTE Approved By: Department Approved By Checked By Written By Enoch Danny/ Tim Joyce Research and Development Department Jacky Jack Benny Quality Assurance
Detection of Braking Intention in Diverse Situations during Simulated Driving based on EEG Feature Combination: Supplement
Detection of Braking Intention in Diverse Situations during Simulated Driving based on EEG Feature Combination: Supplement Il-Hwa Kim, Jeong-Woo Kim, Stefan Haufe, and Seong-Whan Lee Detection of Braking
Solution-processed carbon nanotube thin-film complementary static random access memory
Solution-processed carbon nanotube thin-film complementary static random access memory Michael L. Geier, Julian J. McMorrow, Weichao Xu, Jian Zhu, Chris H. Kim, Tobin J. Marks, and Mark C. Hersam * *Corresponding
Motor/Drive Configuration
ZX900 Electrical Specifications Input Power Output Power Electrical specifications for the ZX900 series drive's input and output power are provided in this section. Voltage (Nominal) Voltage (Range) Frequency
Not for New Design 10 WATT WD DUAL LOW INPUT SERIES DC/DC CONVERTERS. Features
Features Universal 9 to 36 Volt Input Range Up to 10 Watts of PCB Mounted Power Efficiencies to > 80% Optional On/Off Control Pin Fully isolated, Filtered Design Low Noise Outputs Very Low I/O Capacitance,
Lithium Ion Battery Charger for Solar-Powered Systems
Lithium Ion Battery Charger for Solar-Powered Systems General Description: The is a complete constant-current /constant voltage linear charger for single cell Li-ion and Li Polymer rechargeable batteries.
Integrated Simulation Technologies Pvt Ltd
UHC System Sizing to Eliminate Engine Overheating when Grill and Radiator Fronts are Partially Blocked by Mud & Dirt Integrated Simulation Technologies Pvt Ltd Subir Mandal IST India GT-SUITE Conference
Harris IRT Enterprises Digital Resistance Tester Model XP
Harris IRT Enterprises Digital Resistance Tester Model 5012-06XP Specifications & Dimensions 2 Theory of Operation 3 Operator Controls & Connectors 4 Test Connections 5 Calibration Procedure 6-7 Options
SPECIFICATION. Part No. : GW
SPECIFICATION Part No. : GW.71.13 Product Name : 2.4GHz/.8GHz Dipole Antenna for ISM Band and WLAN IEEE 82.11a/b/g/h Feature : dbi High Performance Antenna RP-SMA(M) Hinged Antenna RoHS Compliant SPE-11-8-12/C
Comparison of Cat7 A / Class F A Channel and 802.3bq Link Segment Specification
Comparison of Cat7 A / Class F A Channel and 802.3bq Link Segment Specification Martin Rossbach, Nexans IEEE 802.3 25GBASE-T Study Group Waikoloa, USA July 2015 Content Comparison of Class F A Channel
Silvertel. Ag Features. 2. Description. Power-Over-Ethernet Module. IEEE802.3af compliant. Small SIL and SMT package available
Silvertel V2.2 Jan 2015 Datasheet Ag9700 Pb 1. Features IEEE802.3af compliant Small SIL and SMT package available Low cost, with minimal external components required Input voltage range 36V to 57V Short-circuit
GT-Suite Users Conference
GT-Suite Users Conference Thomas Steidten VKA RWTH Aachen Dr. Philip Adomeit, Bernd Kircher, Stefan Wedowski FEV Motorentechnik GmbH Frankfurt a. M., October 2005 1 Content 2 Introduction Criterion for
QSFP Copper Module Direct Attach Cable Assembly &Cage
Qualification Test Report 501-60067 12Mar. 2012 Rev. 1 QSFP Copper Module Direct Attach Cable Assembly& Qualification Test Report QSFP Copper Module Direct Attach Cable Assembly & Tyco Electronics. (Shanghai)
Numerical Simulation of the Thermoelectric Model on Vehicle Turbocharged Diesel Engine Intercooler
Research Journal of Applied Sciences, Engineering and Technology 6(16): 3054-3059, 013 ISSN: 040-7459; e-issn: 040-7467 Maxwell Scientific Organization, 013 Submitted: January 1, 013 Accepted: January
Diesel % Market Share
PCWG-P-03-023 The AA Motoring Trust: Incentives for a Low Carbon UK Car Fleet The move towards a Low Carbon cars in the UK is both feasible and very worthwhile: it will though need positive and effective
Application Note AN-1203
Application Note AN-1203 Application Note, explaining the overload/short circuit power dissipation, Remote Sense and output filtering of ARE100XXS/D By Abhijit D. Pathak, Juan R. Lopez International Rectifier,
E280 DIAMETER FRAMES
E28 DIAMETER FRAMES MODEL NUMBER CODE...E28 FRAME To construct a motor listing, select the combination of features required, and put all the coded information in the proper sequence. Please account for
Silver T E L E C O M. 1. Features. 2. Description. IEEE802.3af compliant. Small SIL package size - 56mm (L) x 14mm (H) Low output ripple and noise
Silver T E L E C O M V2.0 Aug 2008 Pb. Features IEEE802.3af compliant Small SIL package size - 56mm (L) x 4mm (H) Low output ripple and noise Input voltage range 36V to 57V Only one low cost external decoupling
Introduction: Supplied to 360 Test Labs... Battery packs as follows:
2007 Introduction: 360 Test Labs has been retained to measure the lifetime of four different types of battery packs when connected to a typical LCD Point-Of-Purchase display (e.g., 5.5 with cycling LED
Linear Guides Series OSP-P
Linear Guides Series OSP-P NEW NEW Contents Description Data Sheet No. Page Overview.4.E 3-3 Plain bearing guide SLIDELINE.4.E 33-34 Roller guide POWERSLIDE.4.3E 35-38 Ball bushing guide GUIDELINE.4.4E
Lateral Protection Device
V.5 Informal document GRSG-113-11 (113th GRSG, 10-13 October 2017, agenda item 7.) Lateral Protection Device France Evolution study on Regulation UNECE n 73 1 Structure Accidentology analysis Regulation
Atlas ESR and ESR + Equivalent Series Resistance and Capacitance Meter. Model ESR60/ESR70. Designed and manufactured with pride in the UK.
GB60/70-9 Atlas ESR and ESR + Equivalent Series Resistance and Capacitance Meter Model ESR60/ESR70 Designed and manufactured with pride in the UK User Guide Peak Electronic Design Limited 2004/2016 In
Laboratory Tests, Modeling and the Study of a Small Doubly-Fed Induction Generator (DFIG) in Autonomous and Grid-Connected Scenarios
Trivent Publishing The Authors, 2016 Available online at http://trivent-publishing.eu/ Engineering and Industry Series Volume Power Systems, Energy Markets and Renewable Energy Sources in South-Eastern
EB Series Eighth - Brick Up to 100 Watt DC-DC Converter
FEATURES DOSA Standard Form, Fit & Function Industry standard 1/8th brick footprint 4:1 input voltage range: 9-36 or 18 75Vin ROHS II Directive 2011/65/EU Compliant No minimum load required -40 0 C to
INCREASING ENERGY EFFICIENCY BY MODEL BASED DESIGN
INCREASING ENERGY EFFICIENCY BY MODEL BASED DESIGN GREGORY PINTE THE MATHWORKS CONFERENCE 2015 EINDHOVEN 23/06/2015 FLANDERS MAKE Strategic Research Center for the manufacturing industry Integrating the
Transmitted by the expert from Germany
Overview Transmitted by the expert from Germany Informal document No. GRRF-62-17 (62nd GRRF, 25-28 September 2007, agenda item 9(f)) TPMS Motivations Principles of tire pressure monitoring systems (TPMS)
Robustness Analysis in Vehicle Ride Comfort
Mercedes-Benz Research and Development India Robustness Analysis in Vehicle Ride Comfort Ragish Kalathil, Johannes Schaffner, Srikanth Kethu Date: 3 rd December, 2012 Mercedes-Benz Research and Development
25 to 30 Watt XW Single Series DC/DC Converters
Features 4: Input Voltage Range Low Noise, Highly Regulated Efficiencies to 4 at Full Load No Derating to C Case Temperature Six-Sided Continuous Shielded, Low Thermal Gradient Copper Case Minimum Input
Revision 4 May 23, 2018
Kalsi Seals Handbook Chapter C16 Plastic lined Kalsi Seals Revision 4 May 23, 2018 Individual chapters of the Kalsi Seals Handbook are periodically updated. To determine if a newer revision of this chapter
PU SERIES 1W UNREGULATED
PU SERIES 1W UNREGULATED FEATURES IN LINE PACKAGE 1W UNREGULATED POWER 100% BURN IN HIGH EFFICIENCY INTERNAL SMD TECHNOLOGY NO HEATSINK REQUIRED UL 94V-0 PACKAGE MATERIAL CUSTOM SOLUTIONS AVAILABLE RoHS
SP6644/6645 Evaluation Board Manual
SP6644/6645 Evaluation Board Manual Easy Evaluation for the SP6644/6645 Single or Dual Cell Alkaline to 3.3V Output Provides up to 150mA output current for 2-Cell Input High Efficiency: 92% µsoic Package
Presenters: Mr. Moresh Kolhe Mr. Babu Bhondave Mahindra & Mahindra (AFS) Copyright 2012 Mahindra & Mahindra Ltd. All rights reserved.
Presenters: Mr. Moresh Kolhe Mr. Babu Bhondave Mahindra & Mahindra (AFS) 1 Overview of Presentation Introduction. Objective. PST valve model using Simulink-Simscape. Results and Summary Summary 2 Introduction
Experimental Verification of the Implementation of Bend-Twist Coupling in a Wind Turbine Blade
Experimental Verification of the Implementation of Bend-Twist Coupling in a Wind Turbine Blade Authors: Marcin Luczak (LMS), Kim Branner (Risø DTU), Simone Manzato (LMS), Philipp Haselbach (Risø DTU),
Linear Guides Pneumatic linear drive Series OSP - P Adaptive modular system The Ortman System Plus OSP provides a comprehensive range of linear guides
PNEUMATIC GROUP Guides ORTMAN SYSTEM PLUS LINEAR GUIDES FOR OSP-P 19 Linear Guides Pneumatic linear drive Series OSP - P Adaptive modular system The Ortman System Plus OSP provides a comprehensive range
TRANSMISSION LOSS MINIMIZATION USING ADVANCED UNIFIED POWER FLOW CONTROLLER (UPFC)
TRANSMISSION LOSS MINIMIZATION USING ADVANCED UNIFIED POWER FLOW CONTROLLER (UPFC) Nazneen Choudhari Department of Electrical Engineering, Solapur University, Solapur Nida N Shaikh Department of Electrical
VT2+: Further improving the fuel economy of the VT2 transmission
VT2+: Further improving the fuel economy of the VT2 transmission Gert-Jan Vogelaar, Punch Powertrain Abstract This paper reports the study performed at Punch Powertrain on the investigations on the VT2
Linear Guides Series OSP-P
Linear Guides Series OSP-P NEW Contents Description Page Overview 31-32 Plain bearing guide SLIDELINE 33-34 Roller guide POWERSLIDE 35-38 Aluminium roller guide PROLINE 39-40 Recirculating ball bearing
Output Voltage Current. Input Current Ripple. Efficiency (typ.) Load VDC VDC ma ma ma(typ.) ma(typ.) ma(typ.) μf % 2.
FEATURES Industrial Standard 2" X 1" Package Wide 2:1 Input Voltage Range Fully Regulated Output Voltage High Efficiency up to 88% I/O Isolation 1500 VDC Operating Ambient Temp. Range -40 to 85 Overload
Early Stage Vehicle Concept Design with GT-SUITE
1/18 Early Stage Vehicle Concept Design with GT-SUITE Katsuya Minami Honda R&D Co., Ltd., Automotive R&D Center, Japan Benefits of 1D-Simulation 2/18 How each component is operating during legislative
An High Voltage CMOS Voltage Regulator for automotive alternators with programmable functionalities and full reverse polarity capability
L. Fanucci, G. Pasetti University of Pisa P. D Abramo, R. Serventi, F. Tinfena Austriamicrosystems P. Tisserand, P. Chassard, L. Labiste - Valeo An High Voltage CMOS Voltage Regulator for automotive alternators
BEHAVIOUR OF ELECTRIC FUSES IN AUTOMOTIVE SYSTEMS UNDER INTERMITTENT FAULT
BEHAVIOUR OF ELECTRIC FUSES IN AUTOMOTIVE SYSTEMS UNDER INTERMITTENT FAULT B. Dilecce, F. Muzio Centro Ricerche FIAT, Orbassano (Torino), Italy A. Canova, M. Tartaglia Dipartimento Ingegneria Elettrica
S24SP series 40W Single Output DC/DC Converter
4W Single Output DC/DC Converter FEATURES Efficiency up to 92.8% Wide input range, 9V-36V Package with Industry Standard Pinout Package Dimension: Without heat sink 5.8 x25.4 x1.2mm (2. x1. x.4 ) With
BOARD LEVEL RELIABILITY OF FINE PITCH FLIP CHIP BGA PACKAGES FOR AUTOMOTIVE APPLICATIONS
As originally published in the SMTA Proceedings BOARD LEVEL RELIABILITY OF FINE PITCH FLIP CHIP BGA PACKAGES FOR AUTOMOTIVE APPLICATIONS Laurene Yip, Ace Ng Xilinx Inc. San Jose, CA, USA laurene.yip@xilinx.com
MP-5200 Series. Application. Features. Applicable Literature. Electronic Hydraulic Actuator General Instructions
TAC 1354 Clifford Avenue P. O. Box 2940 Loves Park, IL 61132-2940 www.tac.com MP-5200 Series Electronic Hydraulic Actuator General Instructions Application The MP-5200 Series actuators are for the electronic
LOCAL VERSUS CENTRALIZED CHARGING STRATEGIES FOR ELECTRIC VEHICLES IN LOW VOLTAGE DISTRIBUTION SYSTEMS
LOCAL VERSUS CENTRALIZED CHARGING STRATEGIES FOR ELECTRIC VEHICLES IN LOW VOLTAGE DISTRIBUTION SYSTEMS Presented by: Amit Kumar Tamang, PhD Student Smart Grid Research Group-BBCR aktamang@uwaterloo.ca
Efficiency (typ.) (Range) Output Voltage Current. Input Current Load VDC VDC ma ma ma(typ.) ma(typ.) ma(typ.
FEATURES 2"x 1"x 0.4" Metal Package Wide 2:1 Input Range High Efficiency up to % Operating Ambient Temp. Range 40 C to 80 C Short Circuit Protection I/O-isolation 1500 VDC Input Filter meets EN 55022,class
Design-Technology Co-Optimization for 5nm Node and Beyond
Design-Technology Co-Optimization for 5 Node and Beyond Semicon West 26 Victor Moroz July 2, 26 Why Scaling? When What scales? When does it end? 965 999 2 Moore s Law (Fairchild): Double transistor density
TAK CHEONG. MMSZ5221BW through MMSZ5267BW. Green Product. 500mW SOD-123 SURFACE MOUNT Flat Lead Surface Mount Plastic Package Zener Voltage Regulators
500mW SOD-123 SURFACE MOUNT Flat Lead Surface Mount Plastic Package Zener Voltage Regulators Absolute imum Ratings Symbol Parameter Value Units P D Power Dissipation 500 mw T STG Storage Temperature Range
WLTP. Proposal for a downscaling procedure for the extra high speed phases of the WLTC for low powered vehicles within a vehicle class
WLTP Proposal for a downscaling procedure for the extra high speed phases of the WLTC for low powered vehicles within a vehicle class Technical justification Heinz Steven 06.04.2013 1 Introduction The
EKM Series Motors. For Aerospace & Defense Applications
EKM Series Motors For Aerospace & Defense Applications EKM Series Motors Table of Contents Introduction........................................................................................ 4 Introduction
Silvertel. Ag5510. PoE Ultra Module. 1. Features. 2. Description. 60 Watt Output Power. Very small size. High efficiency DC/DC converter
V1.1 August 2016 Datasheet Silvertel 1. Features 60 Watt Output Power Very small size High efficiency DC/DC converter Wide adjustable output voltage range 1500V isolation (input to output) Input voltage
150 WATT HEW SINGLE SERIES DC/DC CONVERTERS
Features Description The 4:1 Input Voltage 150 W single HEW Series of DC/DC converters provide precisely regulated dc outputs. The output voltage is fully isolated from the input, allowing the output to
OPTIMIZATION STUDIES OF ENGINE FRICTION EUROPEAN GT CONFERENCE FRANKFURT/MAIN, OCTOBER 8TH, 2018
OPTIMIZATION STUDIES OF ENGINE FRICTION EUROPEAN GT CONFERENCE FRANKFURT/MAIN, OCTOBER 8TH, 2018 M.Sc. Oleg Krecker, PhD candidate, BMW B.Eng. Christoph Hiltner, Master s student, Affiliation BMW AGENDA
NON-ISOLATED DC/DC CONVERTERS 4.5V-32V Input 1.2V-5.0V/3A Output
NONISOLATED DC/DC CONVERTERS Input 1.2V5.0V/3A Output x7ah03h Series NonIsolated Remote On/Off High Input Under Voltage Lockout High Power Density OCP/SCP Excellent Thermal Performance Low Cost Description
Linear Guides Series OSP-E
Linear Guides Series OSP-E NEW Contents Description Data Sheet No. Page Overview 1.40.020E 101-102 Plain Bearing SLIDELINE 1.40.021E 103-104 Roller Guide POWERSLIDE 1.40.022E 105-108 Aluminium Roller Guide
Experimental Investigation of Effects of Shock Absorber Mounting Angle on Damping Characterstics
Experimental Investigation of Effects of Shock Absorber Mounting Angle on Damping Characterstics Tanmay P. Dobhada Tushar S. Dhaspatil Prof. S S Hirmukhe Mauli P. Khapale Abstract: A shock absorber is
Available online at ScienceDirect. Procedia Engineering 129 (2015 ) International Conference on Industrial Engineering
Available online at www.sciencedirect.com ScienceDirect Procedia Engineering 129 (2015 ) 201 206 International Conference on Industrial Engineering Simulation of lithium battery operation under severe
Twin and Single Inline Fans. Offers a range of flexible installation and application options, including auto-changeover on the Twin range
Twin and Single Inline Fans Offers a range of flexible installation and application options, including auto-changeover on the Twin range 2 Version 3.1 Breathing Buildings Inline Box Fans Demand Control
How to Develop Qualification Programs for Lead Free Products
How to Develop Qualification Programs for Lead Free Products by Mike Silverman Managing Partner Ops A La Carte mikes@opsalacarte.com www.opsalacarte.com (408) 472-3889 Abstract There are significant reliability
DLD6440 Protocol Converter
DLD6440 Protocol Converter Installation and Operations Manual Model Number: DLD6440 Description: PTZ Control Code Converter Table of Contents Page INTRODUCTION 3 Features 3 Applications 3 Accessories 3
HM8202. The HM8202 is available in the SOP-8L package. Charging Docks Handheld Instruments Portable Computers
Standalone Li-Ion Switch Mode Battery Charger Features Input Supply Range: 9V ~ 14V End-Charge-Current Detection Output Constant Switching Frequency for Minimum Noise Automatic Battery Recharge Automatic
How to Implement xdrive Designs
How to Implement xdrive Designs The xdrive is a unique all-in-one LED driver and dimmer combination designed to fit into a standard recessed electrical box for use with constant-voltage dimmable lighting
Reed Switch Life Characteristics under Different Levels of Capacitive Loading
Reed Switch Life Characteristics under Different Levels of Capacitive Loading June 14, 2004 Stephen Day VP Engineering Coto Technology Summary Life tests were run on four types of Coto Technology reed