Comparison of Signaling and Equalization Schemes
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1 Comparison of Signaling and Equalization Schemes NRZ, Duobinary, and PR4 Joe Caroselli and Cathy Liu High Speed Interface Systems Architecture LSI Logic March 15,2005 1
2 Introduction Overview of signaling schemes NRZ, Duobinary, and PR4 Review of simulator and parameters Presentation of results March 15,2005 2
3 NRZ, Duobinary, and PR4 Overview March 15,2005 3
4 NRZ Signaling Trying to Removing All ISI Through Equalization Our primary equalization goal has been to eliminate intersymbol interference (ISI). A combination of a TX FIR filter and a DFE in the Rx are used to mitigate the ISI. The goal of removing ISI is to make detection possible with a reasonable complexity. March 15,2005 4
5 Duobinary Ideal versus Channel Pulse Response 1+D Channel Samples at time 0 and 1 are 1 0 everywhere else. Appears to be a reasonable fit for channels at this data rate. March 15,2005 5
6 Partial Response Class IV Pulse Response Does not resemble our channel pulse response. March 15,2005 6
7 Frequency Response Comparison NRZ and Duobinary Ideal NRZ equalization target is flat spectrum. NRZ requires a lot of high frequency boost. Duobinary s 1+D equalization target has a null at the Nyquist frequency. It is a better match to the channel at high frequencies and consequently requires less high frequency boost. March 15,2005 7
8 Frequency Response Comparison NRZ, Duobinary, and PR4 Has nulls at both DC and Nyquist Null at DC may match DCnull in AC coupled systems, but PR-4 s DC null is much deeper. Equalizing to PR4 results in throwing away the signal in the low frequency range where the SNR is strongest. March 15,2005 8
9 Duobinary Ideal Eye Diagram No transitions from highest to lowest signal levels in adjacent bits. Notice that slicer value that results in highest jitter tolerance is not the slicer level that results in best noise tolerance. March 15,2005 9
10 PR4 Eye Diagram Horizontal eye opening in ideal eye diagram is reduced compared to 1+D target. Any signal level can transition to any other signal level in adjacent bit. Even in ideal case, without MLSD, eye exhibits very little tolerance to jitter. March 15,
11 Simulator Review March 15,
12 Three System Modeling Approach Three System Model Approach Analytic Simulator (Architecture Determination) Semi-Analytic Simulator (BER, Statistical Eye) Bit By Bit Simulator (Eye Diagrams, Jitter Tolerance, Frequency Offset, Timing, Loop Convergence) Complexity Speed Ease of Modification March 15,
13 Analytic Model Includes Intersymbol Interference Tx Jitter Electronics (White) Noise Crosstalk Does Not Include Receiver Sensitivity Duty Cycle Distortion Other Sources of DJ March 15,
14 Required SNR SNR Required at Slicer for BER SNR = d σ 2 min 2 Pr err 1 2 erfc 2 SNR 2 Approximately 24dB is required for an error rate of March 15,
15 Overview of Simualtions Equalization architectures with a linear FIR feedforward (FF) filter in the TX, and a decision feedback (FB) equalizer in the Rx are compared. The number of taps in the feedforward and feedback equalizers are varied. The effect of one near-end crosstalk aggressor is considered. With Tyco and Intel data sets, worst case NEXT corresponding to that data set is used. With Molex and Xilinx data sets, modeled NEXT from Anderson is used. A simple RC model with pole at 0.75*baud rate is used for the transmitter. Mellitz capacitor-like package model included on both transmitter and receiver. March 15,
16 Parameters Used Only DJ is from ISI No DCD, PJ included 0.010UI σ RJ added Not more than 13.4ps peak-to-peak RJ at 8.5Gbps data rate with probability Not more than 15.6ps peak-to-peak RJ max at 8.5Gbps data rate with probability Signal-To-Electronics Noise Ratio 45dB Crosstalk added as noted Ideal receiver sensitivity assumed March 15,
17 Description of Results SNR at optimal sampling point is shown. No measurement of horizontal eye opening is presented. x-axis shows number of feedback taps used Each line represents a different number of feedforward (FF) equalizer taps used in the TX Each color represents a different signaling scheme. Crosstalk is assumed to occur at the same frequency as the signal. The worst case crosstalk phase at the ideal sampling point is selected. All tap values are ideal. March 15,
18 Summary of Results March 15,
19 March 15, SNR Comparison Intel Backplanes Intel T Intel T Intel T Intel M Intel M Intel B Intel B Intel B1 PR4 5FF+5DFE PR4 5FF+3DFE PR4 3FF+5DFE PR4 3FF+3DFE DB 4FF+5DFE DB 4FF+3DFE DB 3FF+5DFE DB 3FF+3DFE NRZ 3FF+5DFE BP
20 March 15, SNR Comparison Tyco Backplanes Tyco Tyco Tyco Tyco Tyco Tyco Tyco 1 PR4 5FF+5DFE PR4 5FF+3DFE PR4 3FF+5DFE PR4 3FF+3DFE DB 4FF+5DFE DB 4FF+3DFE DB 3FF+5DFE DB 3FF+3DFE NRZ 3FF+5DFE BP
21 SNR Comparison Molex and Xilinx Backplanes BP NRZ 3FF+5DFE DB 3FF+3DFE DB 3FF+5DFE DB 4FF+3DFE DB 4FF+5DFE PR4 3FF+3DFE PR4 3FF+5DFE PR4 5FF+3DFE PR4 5FF+5DFE MoL ex i MoL ex i MoL ex i MoL ex i Mole x o Mole x o Mole x o Mole x o Ande rson March 15,
22 Required Number of DFE Taps To Achieve 24dB SNR Tyco Backplanes BP NRZ DB PR4 3 tap FF 4 tap FF 5 tap FF Tyco 1 <=1 3 6 Tyco 2 <= Tyco Tyco4 <=1 2 4 Tyco 5 <=1 <=1 <=1 Tyco March 15,
23 Required Number of DFE Taps To Achieve 24dB SNR Intel Backplanes BP NRZ DB PR4 3 tap FF 4 tap FF 5 tap FF Intel B Intel B Intel B Intel M Intel M Intel T Intel T >100 Intel T20 >100 >100 >100 March 15,
24 Required Number of DFE Taps To Achieve 24dB SNR Molex and Xilinx Backplanes BP NRZ DB PR4 3 tap FF 4 tap FF 5 tap FF Molex i Molex i Molex i Molex i Molex o2 <= Molex o3 <= Molex o4 <= Molex o5 <= Anderson 8 20 >100 March 15,
25 Selected Results March 15,
26 Results Tyco 1 Backplane 40 Tyc o SNR at Slicer(dB) 25 NRZ: 1 pre + 0 post FIR FF 20 NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF 15 DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF 10 DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF 5 PR4: 1 pre + 2 post FIR FF PR4: 1 pre + 3 post FIR FF 10 2 PR4: 2 pre + 3 post FIR FF Number of Feedback Taps March 15,
27 Results Tyco 5 Backplane 40 Tyc o SNR at Slicer(dB) 25 NRZ: 1 pre + 0 post FIR FF 20 NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF 15 DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF 10 DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF PR4: 1 pre + 3 post FIR FF 10 2 PR4: 2 pre + 3 post FIR FF Number of Feedback Taps March 15,
28 Results Tyco 6 Backplane 40 Tyc o SNR at Slicer(dB) 25 NRZ: 1 pre + 0 post FIR FF 20 NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF 15 DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF 10 DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF PR4: 1 pre + 3 post FIR FF 10 2 PR4: 2 pre + 3 post FIR FF Number of Feedback Taps March 15,
29 Results Intel B1 Backplane 40 Intel B SNR at Slicer(dB) NRZ: 1 pre + 0 post FIR FF NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF 15 NRZ: 2 pre + 3 post FIR FF DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF 10 DB: 1 pre + 3 post FIR FF DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF 10 2 PR4: 1 pre + 3 post FIR FF Number of Feedback Taps PR4: 2 pre + 3 post FIR FF March 15,
30 Results Intel M1 Backplane 40 Intel M SNR at Slicer(dB) 25 NRZ: 1 pre + 0 post FIR FF 20 NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF 15 DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF 10 DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF PR4: 1 pre + 3 post FIR FF 10 2 PR4: 2 pre + 3 post FIR FF Number of Feedback Taps March 15,
31 Results Intel T1 Backplane 40 Intel T SNR at Slicer(dB) NRZ: 1 pre + 0 post FIR FF NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF 15 NRZ: 2 pre + 3 post FIR FF DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF 10 DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF 5 PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF 10 2 Number of Feedback Taps PR4: 1 pre + 3 post FIR FF PR4: 2 pre + 3 post FIR FF March 15,
32 Results Intel T12 Backplane SNR at Slicer(dB) NRZ: 1 pre + 0 post FIR FF NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF PR4: 1 pre + 3 post FIR FF PR4: 2 pre + 3 post FIR FF Intel T Number of Feedback Taps March 15,
33 Results Intel T20 Backplane SNR at Slicer(dB) NRZ: 1 pre + 0 post FIR FF NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF PR4: 1 pre + 3 post FIR FF PR4: 2 pre + 3 post FIR FF Intel T Number of Feedback Taps March 15,
34 Results Molex Inbound 2 Backplane 40 Molex Inbound SNR at Slicer(dB) 25 NRZ: 1 pre + 0 post FIR FF 20 NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF NRZ: 2 pre + 3 post FIR FF 15 DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF DB: 1 pre + 3 post FIR FF 10 DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF 5 PR4: 1 pre + 3 post FIR FF PR4: 2 pre + 3 post FIR FF 10 2 Number of Feedback Taps March 15,
35 Results Molex Outbound 2 Backplane 40 Molex Outbound SNR at Slicer(dB) NRZ: 1 pr e + 0 post FIR FF NRZ: 1 pr e + 1 post FIR FF NRZ: 1 pr e + 2 post FIR FF NRZ: 1 pr e + 3 post FIR FF 15 NRZ: 2 pr e + 3 post FIR FF DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF 10 DB: 1 pre + 3 post FIR FF DB: 2 pre + 3 post FIR FF PR4: 1 pr e + 0 post FIR FF PR4: 1 pr e + 1 post FIR FF PR4: 1 pr e + 2 post FIR FF 10 2 PR4: 1 pr e + 3 post FIR FF Number of Feedback Taps PR4: 2 pr e + 3 post FIR FF March 15,
36 Results Xilinx Backplane 40 Anderson SNR at Slicer(dB) NRZ: 1 pre + 0 post FIR FF NRZ: 1 pre + 1 post FIR FF NRZ: 1 pre + 2 post FIR FF NRZ: 1 pre + 3 post FIR FF 15 NRZ: 2 pre + 3 post FIR FF DB: 1 pre + 0 post FIR FF DB: 1 pre + 1 post FIR FF DB: 1 pre + 2 post FIR FF 10 DB: 1 pre + 3 post FIR FF DB: 2 pre + 3 post FIR FF PR4: 1 pre + 0 post FIR FF 5 PR4: 1 pre + 1 post FIR FF PR4: 1 pre + 2 post FIR FF 10 2 PR4: 1 pre + 3 post FIR FF Number of Feedback Taps PR4: 2 pre + 3 post FIR FF March 15,
37 Conclusions NRZ almost always outperformed Duobinary for similar equalization complexity. PR4 consistently performed worse than NRZ and Duobinary for similar complexity and does not appear to be appropriate for this application. Intel T1 backplanes are tremendously challenging to handle. March 15,
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