Enabling Shift-Left through FV Methodologies on Intel Graphics Designs

Transcription

1 Enabling Shift-Left through FV Methodologies on Intel Graphics esigns M, Achutha KiranKumar V Aarti Gupta Bindumadhava S S Aishwarya Accellera Systems Initiative 1

2 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail Some Myths about FV Some BKMs Accellera Systems Initiative 2

3 Brief History of FV in Intel Graphics Started with atapath formal through STE, on a standard FPU design ~286 bugs found on the next generation design Strong and main tool for finding bugs on all next generation designs Increased the gamut of formal offerings on simple control path designs Started on simple problems and gained the confidence of designers and management Accellera Systems Initiative 3

4 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail Some Myths about FV Some BKMs Accellera Systems Initiative 4

5 Formal Activities at a glance atapath FV STE C2TL Formal TL2TL FV Clock-gating Timing Fix Chicken-Bit Formal Property Verification Connectivity Analysis Formal Scoreboards Low Power Verification Accellera Systems Initiative 5

6 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail atapath FV TL2TL FV Control Path FV Some Myths about FV Some BKMs Accellera Systems Initiative 6

7 Symbolic Trajectory Evaluation (STE) A hybrid between a symbolic simulator and a symbolic model checker Used primarily for checking designs with large datapaths Combines 3-valued simulation (0, 1, X) with symbolic simulation (using variables instead of fixed values) Accellera Systems Initiative 7 Three valued simulation Symbolic three valued simulation Standard Simulationbased verification STE Symbolic simulation

8 STE Infrastructure Accellera Systems Initiative 8

9 C2TL Formal Specification in C++/SystemC Target eep rooted arithmetic algorithms An industry standard tool to verify C2TL equivalence Some complexity reducing techniques to deploy Accellera Systems Initiative 9

10 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail atapath FV TL2TL FV Control Path FV Some Myths about FV Some BKMs Accellera Systems Initiative 10

11 TL2TL Formal Equivalence Ascertains mathematically that assuming the inputs to the previous design (SPEC) and the changed design(impl) are same, the end results should always match ASSUME: SAME INPUTS If incremental changes are intended to change the functionality; constrain to disable the new functionality Changed esign Original esign Original esign Incremental Changes O/Ps Are Outputs equal? O/Ps Accellera Systems Initiative 11

12 TL2TL FV Applications Chicken Bit Additions Timing Fixes Logic edistribution Critical Path eduction Chicken Bit Accellera Systems Initiative 12

13 TL2TL FV Applications Chicken bit fixes potentially broke the sanctity Previous TL Used as Spec TL with bug fix and chicken bit Chicken bit disabled Accellera Systems Initiative 13

14 TL2TL FV Applications Improved Power saving => Aggressive Clock gating TL with Clock gating isabled TL with Clock gating Enabled Accellera Systems Initiative 14

15 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail atapath FV TL2TL FV Control Path FV Some Myths about FV Some BKMs Accellera Systems Initiative 15

16 Assertion based Formal Property Verification Connectivity Analysis Low Power Verification Solutions Application specific methodologies Control Path FV Accellera Systems Initiative 16

17 esign Exploration Use Properties to explore the design Simple Cover properties to give a higher confidence on the design Formal Test bench even before V comes up Safer esign turned in for validation Accellera Systems Initiative 17

18 Formal Scoreboards CLK1 VALI_IN ATA_IN CONSTAIN UT with Large ata- Path Symbolic Sequence CLK2 VALI_OUT ATA_OUT CHECK Infinite number of I/P sequences => a set of SYMBOLIC SEQUENCES [Bochra El-Meray, Jörg Müller, Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal atapath Scoreboards, VCon 2013] All symbolic sequences together enough to validate the data-integrity Accellera Systems Initiative 18

19 Complexity esolution Techniques ivide and Conquer Careful Logic Carving Inputs Pruning Case Splitting Intermediate equivalence esign Abstractions Block A Block B Block C Block Block E Accellera Systems Initiative 19

20 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail Some Myths about FV Some BKMs Accellera Systems Initiative 20

21 Some Myths about FV we busted Only Phds do FV 90% FV engrs non-phs FV is hard Choose the right problem to solve oesn t have coverage ight set of apps available Takes Long time Tricks available to close fast Only good to write proofs Various apps bring closer Only for verification esign Exploration Can retire simulation ecommend co-existence Not needed if I have 100% V Can help in faster closure Accellera Systems Initiative 21

22 Wish list Still the barrier is high need right education Challenges in pockets to convince the teams that FV is No second fiddle Need to penetrate/convince Management/uarch/ Senior esigners Faster Formal Testbench bring up From the V testbench Faster and guaranteed convergence Today 60% of our work is in fighting convergence Accellera Systems Initiative 22

23 Agenda Brief History of FV in Intel Graphics Quick Glance at all FV Activities FV Activities in etail Some Myths about FV Some BKMs Accellera Systems Initiative 23

24 Some BKMs Start simple and be nimble esults speak more about the efficiency of formal Quality of the bug rather than the quantity of bugs FV is time taking but a sure solution for most of the problems If we cant achieve all at one time, better divide and conquer FV completion is not a linear function over time. Most of the times, it is a step function. Be patient. egular updates to management in a perceivable format helps all through the chain understand the progress. Last but not the least, You need strong management Will Accellera Systems Initiative 24

25 Q & A Accellera Systems Initiative 25