64CH COMMON DRIVER FOR DOT MATRIX LCD

Transcription

1 64 OON DIVE FO DOT ATIX D INTODUTION The (TQFP type: S6B2107) is an D driver SI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver TQFP type: S6B2108). The is fabricated by low power OS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver). FEATUES Dot matrix D common driver with 64 channel output 64-bit shift register at internal D driver circuit Internal timing generator circuit for dynamic display Selection of master/slave mode Applicable D duty: 1/48, 1/64, 1/96, 1/128 Power supply voltage: + 5V ± 10% D driving voltage: 8V - 17V ( - ) Interface Driver ontroller OON SEGENT Other S6B0108 PU igh voltage OS process 100QFP / 100TQFP or bare chip available 1

2 64 OON DIVE FO DOT ATIX D BOK DIAGA bit 4- evel Driver 64 bit Bi-Directional Shift egister DIO1 P S Data Shift Direction & Phase Selection ontrol ircuit DIO2 2 OS Timing Generator ircuit F K1 V SS DS1 DS2 S FS 2

3 64 OON DIVE FO DOT ATIX D 3 PIN ONFIGUATION 100 QFP VEE VDD DIO1 FS DS1 DS2 S V SS S K1 F P DIO VEE 2

4 64 OON DIVE FO DOT ATIX D PAD DIAGA (IP AYOUT FO TE 100QFP) DIO1 FS DS1 DS2 S V SS S K1 F P DIO Y (0, 0) X hip size: PAD size: Unit : µm VEE VEE There is the mark on the center of the chip. 4

5 64 OON DIVE FO DOT ATIX D PAD ENTE OODINATES (100QFP) Pad Number Pad Name oordinate Pad Number Pad Name oordinate Pad Number Pad Name oordinate X Y X Y X Y DS S VSS S K F P DI VEE VEE VDD DI FS DS

6 64 OON DIVE FO DOT ATIX D TQFP (S6B2107) S6B2107 (100 TQFP) DIO2 P F K1 S VSS S DS2 DS1 FS DIO

7 64 OON DIVE FO DOT ATIX D PAD DIAGA (IP AYOUT FO TE 100-TQFP) Y (0, 0) X hip size: 3850 X 100 PAD size: 100 X 100 Unit : µ m VEE VEE VDD 25 DIO1 FS DS1 DS2 S V SS S K1 F P DIO2 2 There is the mark S6B2107 on the center of the chip. 7

8 64 OON DIVE FO DOT ATIX D PAD ENTE OODINATES (100-TQFP) Pad Number Pad Name oordinate Pad Number Pad Name oordinate Pad Number Pad Name oordinate X Y X Y X Y S VSS S K F P DIO VEE VEE VDD DIO FS DS DS

9 64 OON DIVE FO DOT ATIX D PIN DESIPTION Table 1. Pin Description Pin Number QFP (TQFP) 28(25) 40(37) 23(20), 58(55) Symbol I/O Description V SS Power For internal logic circuit (+5V ± 10%) GND ( = 0 V) For D driver circuit 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52),,,, Power Bias supply voltage terminals to drive D. Slelect evel Non-Select evel (), () (), () and ( &, &, & ) should be connected by the same voltage. 42(39) S Input Selection of master/slave mode - aster mode (S = 1) DIO1, DIO2, 2 and is output state. - Slave mode (S = 0) S = 1 DIO1 is input state (DIO2 is output state) S = 0 DIO2 is input state (DIO1 is output state) 2 and are input state. 39(36) S Input Selection of data shift direction. S Data Shift Direction DIO DIO2 DIO DIO1 49(46) P Input Selection of shift clock (2) phase. P Shift lock (2) Phase Data shift at the rising edge of 2 Data shift at the falling edge of 2 30(27) FS Input Selection of oscillation frequency. - aster mode When the frame frequency is 70 z, the oscillation frequency should be fosc = 430kz at FS = 1( ) fosc = 215kz at FS = 0(V SS ) - Slave mode onnect to. 9

10 64 OON DIVE FO DOT ATIX D Table 1. Pin Description (ontinued) Pin Number QFP (TQFP) 31(28) 32(29) Symbol I/O Description DS1 DS2 Input Selection of display duty. - aster mode DS1 DS2 Duty 1/48 1/64 1/96 33(30) 35(32) 37(34) 1/128 - Slave mode onnect to Oscillator - aster mode: Use these terminals as shown below. f f Open External Open - Slave mode: Stop the oscillator as shown below. Open Open 44(41) 43(40) K1 Output Operating clock output for the S6B aster mode: connection to K1 and of the S6B Slave mode: open 46(43) F Output Synchronous frame signal. - aster mode: connection to F of the S6B Slave mode: open 47(44) Input/ Output 52(49) 2 Input / Output Alternating signal input for D driving. - aster mode: output state onnection to of the S6B Slave mode: input state onnection to the controller Data shift clock - aster mode: output state onnection to of the S6B Slave mode: input state onnection to shift clock terminal of the controller. 10

11 64 OON DIVE FO DOT ATIX D 29(26) 50(47) DIO1 DIO2 Input/ Output Data input/output pin of internal shift register. S DS2 DIO1 DIO2 Output Output Output Output Input Output Output Input 11

12 64 OON DIVE FO DOT ATIX D Table 1. Pin Description (ontinued) Pin Number QFP (TQFP) 22-1(19-1) (100-56) Symbol I/O Description 1-64 Output ommon signal output for D driving. Data Out V 1 V 4 V 5 V 0 34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50) No connection AXIU ABSOUTE IIT haracteristic Symbol Value Unit Note Operating voltage -0.3 to +7.0 V (1) Supply voltage to +0.3 V (4) Driver supply voltage V B -0.3 to +0.3 V (1), (2) V D -0.3 to +0.3 V (3), (4) Operating temperature T OP -30 to Storage temperature T STG -55 to NOTES: 1. Based on V SS = 0V 2. Applies to input terminals and I/O terminals at high impedance. (Except (), (), () and ()) 3. Applies to (), (), () and (). 4. Voltage level: = = = =. 12

13 64 OON DIVE FO DOT ATIX D EETIA AATEISTIS D AATEISTIS ( = +5V ± 10%, V SS = 0V, - =8-17V, TA = ) haracteristic Symbol ondition in Typ ax Unit Note Input Voltage igh V I V (1) ow V I V SS Output igh V O I O = -0.4mA V (2) voltage ow V O I O = 0.4mA Input leakage current I KG V IN = -V SS µa (1) OS frequency On resistance (VDIV- i) f OS ON Operating current I DD1 Supply current I DD2 I EE Operating f op1 f = 47kΩ ± 2% f = 20pf ± 5% - = 17V oad current = ± 150µA aster mode 1/128 Duty Slave mode 1/128 Duty aster mode 1/128 Duty aster mode External clock kz KΩ ma (3) µa (4) (5) kz Frequency f op2 Slave mode NOTES: 1. Applies to input terminals FS, DS1, DS2,, S, S and P and I/O terminals DIO1, DIO2, and 2 in the input state. 2. Applies to output terminals K1, and F and I/O terminals DIO1, DIO2, and 2 in the output state. 3. This value is specified at about the current flowing through V SS. Internal oscillation circuit: f = 47kΩ, f = 20pF. Each terminal of DS1, DS2, FS, S and S is connected to and out is no load. 4. This value is specified at about the current flowing through V SS. Each terminal of DS1, DS2, FS, S, P and is connected to, and S is connected to V SS. 2,, DIO1 is external clock. 5. This value is specified at about the current flowing through. Don t connect to V D (-). 13

14 64 OON DIVE FO DOT ATIX D A AATEISTIS ( = 5V ± 10%, TA = ) aster ode (S =, P =, f = 20pF, f = 47kW) t W t W t W DIO1 (S = ) DIO2 (S = V SS ) t su t D t su t D DIO2 (S = ) DIO1 (S = V SS ) t D t DF F t D t D t F t tw1 K1 t W1 t D12 t D21 t W2 t F t 14

15 64 OON DIVE FO DOT ATIX D aster ode haracteristic Symbol in Typ ax Unit Data setup time t SU µs Data hold time t D Data delay time t D F delay time t DF -2-2 delay time t D low level width t W high level width t W K1 low level width t W ns low level width t W K1 high level width t W high level width t W K1- phase difference t D K1 phase difference t D K1, rise/fall time t /t F

16 64 OON DIVE FO DOT ATIX D Slave ode (S = V SS ) 2 (PK2 = V SS ) t F t t W1 0.7V DD 0.3 t W1 t SU t W2 t W 2 (PK2 = ) DIO1 (S = ) DIO2 (S = V SS ) Input Data t t t t D F t DIO1 (S = ) DIO2 (S = V SS ) Onput Data haracteristics Symbol in Typ ax Unit Note 2 low level width t W ns P = V SS 2 high level width t W ns P = V SS 2 low level width t W ns P = 2 high level width t W ns P = Data setup time t SU ns Data hold time t D ns Data delay time t D ns (NOTE) Output data hold time t ns 2 rise/fall time t /t F ns NOTE: onnect load = 30pF Output 30pF 16

17 64 OON DIVE FO DOT ATIX D FUTIONA DESIPTION Oscillator The Oscillator generates 2,, F of the, and K1 and of the S6B0108 by the oscillation resister and capacitor. When selecting the master/slave mode, the oscillation circuit is as following: aster ode: In the master mode, use these terminals as shown below. f f 47KΩ 20pF Internal Oscillation Open External lock External lock Open Slave ode: In the slave mode, stop the oscillator as shown below. Open Open Timing Generation ircuit It generates 2,, F, K1 and by the frequency from the oscillation circuit. Selection of aster/slave (/S) ode - When /S is, it generates 2,, F, K1 and internally. - When /S is, it operates by receiving and 2 from the master device. Frequency Selection (FS) To adjust F frequency by 70z, the oscillation frequency should be as follows: FS Oscillation Frequency f OS = 430kz f OS = 215kz In the slave mode, it is connected to. 17

18 64 OON DIVE FO DOT ATIX D Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 DS2 DUTY 1/48 1/64 1/96 1/128 Data Shift & Phase Select ontrol Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the 2 according to P. P Phase Selection Data shift on rising edge of 2 Data shift on falling edge of 2 Data Shift Direction Selection When /S is connected to, DIO1 and DIO2 terminal is only output. When /S is connected to V SS, it depends on the S. S S DIO1 DIO2 Direction of Data Output Output 1 64 Output Output 64 1 Input Output DIO DIO2 Output Input DIO DIO1 18

19 64 OON DIVE FO DOT ATIX D TIING DIAGA 1/48 DUTY TIING (ASTE ODE) ondition: DS1 =, DS2 =, S = (), P = K F DIO1 ( DIO2 ) 1 ( 48 ) 2 ( 47 ) ( 2 ) 48 ( 1 ) DIO2 ( DIO1 ) elation of 2 & DIO1 ( DIO2 ) 2 DIO1 ( DIO2 ) 19

20 64 OON DIVE FO DOT ATIX D 1/128 DUTY TIING (ASTE ODE) ondition: DS1 =, DS2 =, S = (), P = K F DIO1 ( DIO2 ) 1 ( 128 ) 2 ( 127 ) 127 ( 2 ) 128 ( 1 ) DIO2 ( DIO1 ) elation of 2 & DIO1 ( DIO2 ) 2 DIO1 (DIO2) 20

21 64 OON DIVE FO DOT ATIX D 1/48 DUTY TIING (SAVE ODE) ondition: P =, S = () DIO1 ( DIO2 ) 1 ( 48 ) 2 ( 47 ) 47 ( 2 ) 48 ( 1 ) DIO2 ( DIO1 ) 21

22 64 OON DIVE FO DOT ATIX D POWE DIVE IUIT / 1 / 1 V2 2 V3 To S6B / 1 V / elation of Duty & Bias Duty Bias DIV 1/48 1/8 2 = 41 1/64 1/9 2 = 51 1/96 1/11 2 = 71 1/128 1/12 2 = 81 When duty factor is 1/48, the value of 1 & 2 should satisfy. 1/(41 + 2) = 1/ kΩ, 2 = 12kΩ 22

23 64 OON DIVE FO DOT ATIX D APPIATION IUIT 1/128 duty Segment driver (S6B0108) interface circuit 15 / V2/ V3/ / S3 S2B S1B S6B0108 DB0 -DB7 STB E /W S F K1 V SS S 1 - S 64 SEG128 S 1 - S 64 / V2/ V3/ S3 S2B S6B0108 S1B DB0 -DB7 STB E /W S V SS F K1 D Panel / V2/ V3/ / / / V2/ V3/ / S3 S2B S1B S6B0108 DB0 -DB7 STB E /W S F K1 V SS S 1 - S 64 SEG1 O1 O128 S 1 - S 64 S3 S2B S6B0108 S1B DB0 -DB7 STB E /W S V SS F K1 15 S /W E 15 STB DB0 - DB7 S1B S2B S3 5 PU S FS S V SS 64 V 0/ V 1/ V 4/ V 5/ DIO1 DIO2 DS1 2 DS2 (master) P K1 F open open DIO2 2 V 0/ 64 V 1/ P V 4/ FS V 5/ DS1 (slave) KS2 V SS S K1 F S open open open open open V 0 V 1 V 2 V 3 V 4 V 5 23