MACH 5 CPLD Family. Fifth Generation MACH Architecture

Transcription

1 MACH 5 CPLD Family Fifth Generation MACH Architecture Includes MACH 5A Family Advance Information FEATURES High logic densities and s for increased logic integration 18 to 51 macrocell densities 68 to 56 s Wide selection of density and combinations to support most application needs 6 macrocell density options 8 options Up to 5 options per macrocell density Up to 6 density & options for each package Performance features to fit system needs 5.5 ns t PD Commercial,.5 ns t PD Industrial 18 MHz f CNT Four programmable power/speed settings per block Flexible architecture facilitates logic design Multiple levels of switch matrices allow for performance-based routing 100% routability and pin-out retention Synchronous and asynchronous clocking, including dual-edge clocking Asynchronous product- or sum-term set or reset to 64 output enables Functions of up to product terms Advanced capabilities for easy system integration 3.3-V & 5-V JEDEC-compliant operations JTAG (IEEE ) compliant for boundary scan testing 3.3-V & 5-V JTAG in-system programming PCI compliant (-5/-6/-/-10/-1 speed grades) Safe for mixed supply voltage system design Programmable pull-up or Bus-Friendly Inputs & s Individual output slew rate control Hot socketing Programmable security bit Advanced EE CMOS process provides high performance, cost effective solutions Supported by Vantis DesignDirect software for rapid logic development Supports HDL design methodologies with results optimized for Vantis Flexibility to adapt to user requirements Software partnerships that ensure customer success Vantis and Third-party hardware programming support Lattice/VantisPRO (formerly known as MACHPRO ) software for in-system programmability support on PCs and Automated Test Equipment Programming support on all major programmers including Data, BP Microsystems, Advin, and System General Publication# 0446 Rev: G Amendment/0 Issue Date: November 1998

2 Note: 1. M5-xxx is for 5-V devices. M5LV-xxx is for 3.3-V devices. Table 1. MACH 5 Device Features 1 M5-18 M5-19 M5-56 M5-0 M5-384 M5-51 Feature M5LV-18 M5LV-56 M5LV-0 M5LV-384 M5LV-51 Supply Voltage (V) Maximum User Pins t PD (ns) t SS (ns) t COS (ns) f CNT (MHz) Static Power (ma) JTAG-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PCI-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Feature M5A3-18 M5A5-18 Notes: 1. All information on MACH 5A devices is Advance Information. Please contact a Vantis sales representative for details on availability.. M5A5-xxx is for 5-V devices M5A3-xxx is for 3.3-V devices. GENERAL DESCRIPTION Table. MACH 5A Device Features 1, M5A3-19 M5A5-19 M5A3-56 M5A5-56 M5A3-0 M5A3-384 M5A3-51 Supply Voltage (V) Maximum User Pins t PD (ns) t SS (ns) t COS (ns) f CNT (MHz) Static Power (ma) TBD TBD TBD TBD TBD TBD TBD TBD TBD JTAG-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes PCI-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes The MACH 5 family consists of a broad range of high-density and high- Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, JTAG testability, and advanced clocking options (Tables 1 and ). Both the MACH 5 and the MACH 5A families offer 5-V (M5-xxx and M5A5-xxx) and 3.3-V (M5LV-xxx and M5A3-xxx) operation. Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on EECMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Tables 3 and 4). The 5.5, 6.5,.5, 10, and 1-ns devices are compliant with the PCI Local Bus Specification. MACH 5 Family

3 Device Note: 1. C = Commercial grade, I = Industrial grade Table 3. MACH 5 Speed Grades Speed Grade M5-18 C C, I C, I C, I I M5LV-18 C C,I C, I C, I I M5-19 C C, I C, I C, I I M5-56 C C, I C, I C, I I M5LV-56 C C, I C, I C, I I M5-0 C C, I C, I C, I I M5LV-0 C C, I C, I C, I I M5-384 C C, I C, I C, I I M5LV-384 C C, I C, I C, I I M5-51 C C, I C, I C, I I M5LV-51 C C, I C, I C, I I Device Table 4. MACH 5A Speed Grades Speed Grade M5A3-18 C C, I C, I C, I I M5A5-18 C C, I C, I C, I I M5A3-19 C C, I C, I C, I I M5A5-19 C C, I C, I C, I I M5A3-56 C C, I C, I C, I I M5A5-56 C C, I C, I C, I I M5A3-0 C (Note ) C (Note ) C, I (Note ) C, I C, I I M5A3-384 C (Note ) C (Note ) C, I (Note ) C, I C, I I M5A3-51 C (Note ) C, I (Note ) C, I C, I I Notes: 1. C = Commercial grade, I = Industrial grade. All information on MACH 5A devices is Advance Information. Please contact a Vantis sales representative for details on availability.. The 5 and 6 commercial and industrial speed grades are under development for M5A3-0, M5A3-384, and M5A3-51. Please contact a Vantis sales representative for details on availability. With Vantis unique hierarchical architecture, the MACH 5 family provides densities up to 51 macrocells to support full system logic integration. Extensive routing resources ensure pinout retention as well as high utilization. It is ideal for PAL block device integration and a wide range of other applications including high-speed computing, low-power applications, communications, and embedded control. At each macrocell density point, Vantis offers several and package options to meet a wide range of design needs (Tables 5 and 6). MACH 5 Family 3

4 Table 5. MACH 5 Package and Options 1 M5-18 M5-19 M5-56 Package M5LV-18 M5LV pin TQFP 68, 4* 68 68, 4* 100-pin PQFP pin TQFP 104* 104* 144-pin PQFP Note: 1. The options indicated with a * are only available for the LV devices. M5-0 M5LV-0 M5-384 M5LV-384 M5-51 M5LV-51 0-pin PQFP pin PQFP pin PQFP ball BGA ball BGA 56 Package M5A3-18 M5A5-18 Table 6. MACH 5A Package and Options 1 M5A3-19 M5A5-19 M5A3-56 M5A pin PQFP pin TQFP pin TQFP M5A3-0 M5A3-384 M5A pin PQFP pin PQFP ball BGA ball BGA 56 Note: 1. All information on MACH 5A devices is Advance Information. Please contact a Vantis sales representative for details on availability. Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today s complex designs. safety features allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system programmable through a JTAG-compliant interface. Vantis offers software design support for MACH devices in both the MACHXL and DesignDirect development systems. The DesignDirect development system is the Vantis implementation software that includes support for all Vantis CPLD, FPGA and SPLD devices. This system is supported under Windows 95, 98 and NT as well as Sun Solaris and HPUX. DesignDirect software is designed for use with design entry, simulation and verification software from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 0 0 input netlists, generates JEDEC files for Vantis PLDs and creates industry standard EDIF, Verilog, VITAL compliant VHDL and SDF simulation netlists for design verification. DesignDirect software is also available in product configurations that include VHDL and Verilog synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided. 4 MACH 5 Family

5 FUNCTIONAL DESCRIPTION The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the segments together. The only logic difference between any two MACH 5 devices is the number of segments. Therefore, once a designer is familiar with one device, consistent performance can be expected across the entire family. All devices have four clock pins available which can also be used as logic inputs. Block: MCs CLK 4 Segment: 4 Blocks Block Interconnect Segment Interconnect Figure 1. MACH 5 Block Diagram 0446G-001 The MACH 5 PAL blocks consist of the elements listed below (Figure ). While each PAL block resembles an independent PAL device, it has superior control and logic generation capabilities. cells Product-term array Register control generator Output enable generator The s associated with each PAL block have a path directly back to that PAL block called local feedback. If the is used in another PAL block, the interconnect feeder assigns a block interconnect line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide connections between any two signals in a device. The block feeder assigns block interconnect lines and local feedback lines to the PAL block inputs. MACH 5 Family 5

6 OE Block Feeder Block Interconnect Local Feedback Product-term Array Logic Alocator Input Register Path s Interconnect Feeder Figure. PAL Block Structure 0446G-00 PRODUCT-TERM ARRAY AND LOGIC ALLOCATOR The product-term array uses the same sum-of-products architecture as Vantis PAL devices and consists of inputs (plus their complements) and 64 product terms arranged in clusters. A cluster is a sum-of-products function with either 3 of 4 product terms. Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or four product terms, but a given cluster can only be steered to one macrocell (Table ). If only three product terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation and/or polarity control. The wide logic allocator is comprised of all of the individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the MACH 5 device allows for the implementation of large equations (up to product terms) with only one pass through the logic array. Table. Product Term Steering Options for PT Clusters and Macrocell Available Clusters Macrocell Available Clusters M 0 C 0, C 1, C, C 3, C 4 M 8 C 5, C 6, C, C 8, C 9, C 10, C 11, C 1 M 1 C 0, C 1, C, C 3, C 4, C 5 M 9 C 6, C, C 8, C 9, C 10, C 11, C 1, C 13 M C 0, C 1, C, C 3, C 4, C 5, C 6 M 10 C, C 8, C 9, C 10, C 11, C 1, C 13, C 14 M 3 C 0, C 1, C, C 3, C 4, C 5, C 6, C M 11 C 8, C 9, C 10, C 11, C 1, C 13, C 14, C 15 M 4 C 0, C 1, C, C 3, C 4, C 5, C 6, C M 1 C 8, C 9, C 10, C 11, C 1, C 13, C 14, C 15 M 5 C 1, C, C 3, C 4, C 5, C 6, C, C 8 M 13 C 9, C 10, C 11, C 1, C 13, C 14, C 15 M 6 C, C 3, C 4, C 5, C 6, C, C 8, C 9 M 14 C 10, C 11, C 1, C 13, C 14, C 15 M C 3, C 4, C 5, C 6, C, C 8, C 9, C 10 M 15 C 11, C 1, C 13, C 14, C 15 6 MACH 5 Family

7 The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be configured as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell. Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In order to use this option, these macrocells must be accessed via the pins associated with macrocells 3 and 1, respectively. Once the macrocell is used as an input register, it cannot be used for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The pins associated with macrocells 0 and 15 can still be used as input pins. Although the pins for macrocells 3 and 1 are used to connect to the input registers, these macrocells can still be used as buried macrocells to drive device logic via the matrix. Logic Allocator Bus Macrocell 5-8 Clusters/ MC D Q Prog. Polarity Mode Selection Figure 3. Macrocell Diagram 0446G-003 The control generator provides four configurable clock lines and three configurable set/reset lines to each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can be independently selected by any flip-flop within a block. The clock lines can be configured to provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks, and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks and one sum-term clock, are available per PAL block. Positive or negative edge clocking is available as well as advanced clocking features such as complementary and biphase clocking. Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful in applications such as fast data paths. A biphase clock line clocks flip-flops on both the positive and negative edges of the clock. The configuration options for the four clock lines per PAL block are as follows: Clock Line 0 Options Global clock (0, 1,, or 3) with positive or negative edge clock enable Product-term clock (A*B*C) Sum-term clock (A+B+C) Clock Line 1 Options Global clock (0, 1,, or 3) with positive edge clock enable MACH 5 Family

8 Global clock (0, 1,, or 3) with negative edge clock enable Global clock (0, 1,, or 3) with positive and negative edge clock enable (biphase) Clock Line Options Global clock (0, 1,, or 3) with clock enable Clock Line 3 Options Complement of clock line (same clock enable) Product-term clock (if clock line does not use clock enable PT (0:3) PINCLK (0:3) MUX 4TO1 IN (0) IN (1) IN () OUT IN (3) U1 F0 F1 PT0 CLKIN Clock Enable MUX TO1 N (0) OUT N (1) F0 MUX TO1 /CLK F0 CLK0 PT (0:) PT0 SET0/RST MUX 4TO1 IN (0) IN (1) IN () OUT IN (3) U F0 F1 PT1 PT /CLK CLK OUT CLKEN1 BIPHASE CLKEN CLK1 PT1 MUX TO1 PT1 OUT /PT1(ST) F0 SET1/RST MUX 4TO1 IN (0) IN (1) IN () OUT IN (3) U3 F0 F1 MUX TO1 CLKIN Clock Enable CLK PT MUX TO1 PT OUT /PT F0 SET/RST/LE Block Sets/Reset 0, LE PT3 MUX TO1 /CLK PTCLK CLK3 F0 Block Clocks G-004 Figure 4. Clock 0446G-005 Figure 5. Set/Reset The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all. All three lines can be configured for product term set/reset and two of the three lines can be configured as sum term set/reset and one of the lines can be configured as product-term or sumterm latch enable. While the set/reset signals are generated in the control generator, whether that signal sets or resets a flip-flop is determined within the individual macrocell. The same signal can set one flip-flop and reset another. PT or /PT can also be used as a latch enable for macrocells configured as latches. 8 MACH 5 Family

9 OE There is one output enable (OE) generator per PAL block that generates two product-term driven output enables. Each cell is simply an output buffer. Each cell within the PAL block can choose to be permanently enabled, permanently disabled, or choose one of the two product term output enables per PAL block (Figure 6). Output Enable Internal Feedback External Feedback Figure 6. Output Enable and Cell 0446G-006 MACH 5 Family 9

10 MACH 5 TIMING MODEL The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, t BUF, is defined as the time it takes to go through the output buffer to the pad. If a signal goes to the internal feedback rather than to the pad, the parameter designator is followed by an i. By adding t BUF to this internal parameter, the external parameter is derived. For example, t PD = t PDi + t BUF. A diagram representing the modularized MACH 5 timing model is shown in Figure. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters. (External Feedback) (Internal Feedback) COMB/DFF/ LATCH IN INPUT REG/ INPUT LATCH t SIR (S/A) t HIR (S/A) t SIL t HIL t SRR t CES t CEH t CO (S/A) i t PDILi t GOAi t SRi Q t BLK t SEG t PL1 t PL t PL3 t PT t S (S/A) t H (S/A) t SAL t HAL t SRR t CES t CEH CE t PDi t CO (S/A) i t PDLi t GOAi t SRi SR Q t BUF t EA t ER t SLW OUT CE SR PIN CLK Figure. MACH 5 Timing Model 0446G MACH 5 Family

11 MULTIPLE AND DENSITY OPTIONS The MACH 5 family offers six macrocell densities in a number of options. This allows designers to choose a device close to their logic density and requirements, thus minimizing costs. For the same package type, every density has the same pin-out. With proper design considerations, a design can be moved to a higher or lower density part as required. JTAG BOUNDARY SCAN TESTABILITY All MACH 5 devices have JTAG boundary scan cells and are compliant to the JTAG standard, IEEE This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. JTAG IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 5 devices provide in-system programming (ISP) capability through their JTAG ports. This capability has been implemented in a manner that insures that the JTAG port remains compliant to the IEEE standard. By using JTAG as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. MACH 5 devices can be programmed across the commercial temperature and voltage range. Vantis provides its free PC-based Lattice/VantisPRO software to facilitate in-system programming. Lattice/ VantisPRO software takes the JEDEC file output produced by Vantis design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, Lattice/VantisPRO software can output files in formats understood by common automated test equipment. This equipment can then be used to program MACH 5 devices during the testing of a circuit board. For more information about in-system programming, refer to the separate document entitled MACH ISP Manual. PCI COMPLIANT MACH 5(A) devices in the -5/-6/-/-10/-1 speed grades are compliant with the PCI Local Bus Specification version.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above because of their 5-V input tolerant feature. MACH 5 devices provide the speed, drive, density, output enables and s for the most complex PCI designs. MACH 5 Family 11

12 SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1 Both the 3.3-V and 5-V MACH 5 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the 3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixedvoltage design capability. Note: 1. Except for M5-18, M5-19, and M5-56. Please refer to Application Note titled Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices. PULL-UP OR BUS-FRIENDLY INPUTS AND S All MACH 5 devices have inputs and s which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is a good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level 1. For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book. All MACH 5A devices have a programmable bit that configures all input and s with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and s are weakly pulled up. For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book. POWER MANAGEMENT There are 4 power/speed options in each MACH 5 PAL block (Table 8). The speed and power tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. In large designs, there may be several different speed requirements for different portions of the design. PROGRAMMABLE SLEW RATE Table 8. Power Levels High Speed/High Power Medium High Speed/Medium High Power Medium Low Speed/Medium Low Power Low Speed/Low Power 100% Power 6% Power 40% Power 0% Power Each MACH 5 device has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. 1 MACH 5 Family

13 POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. HOT SOCKETING MACH 5A devices are well-suited for those applications that require hot socket capability. Hot socketing a device requires that the device, when powered-down, can tolerate active signals on the s and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH device be minimal on active signals. MACH 5 Family 13

14 MACH 5 PAL BLOCK Output Enable Output Enable M 0 Macro cell Cell M 1 Macro cell Cell M Macro cell Cell M 3 Macro cell Cell 0 C 0 M 4 Macro cell Cell C 1 C M 5 Macro cell Cell C 3 Switch Matrix C 4 C 5 C 6 C C 8 Logic Allocator M 6 M M 8 Macro cell Macro cell Macro cell Cell Cell Cell C 9 C 10 C 11 M 9 Macro cell Cell C 1 C 13 M 10 Macro cell Cell 63 C 14 C 15 M 11 Macro cell Cell M 1 Macro cell Cell M 13 Macro cell Cell M 14 Macro cell Cell M 15 Macro cell Cell CLK 0446G MACH 5 Family

15 BLOCK DIAGRAM M5(LV)-18/XXX, M5A(3,5)-18/XXX SEGMENT 0 Block A/ 0-15 Block D/ 0-15 I 0, 1 Block Interconnect Block B/ 0-15 Block C/ 0-15 CLK0 CLK1 CLK CLK3 4 S E G M E N T I N T E R C O N N E C T Block A/ 0-15 Block D/ 0-15 I, 3 Block Interconnect Block B/ 0-15 Block C/ 0-15 SEGMENT G-00 MACH 5 Family 15

16 BLOCK DIAGRAM M5-19/XXX, M5A(3,5)-19/XXX Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 I 0 Block Interconnect I, I 3 Block Interconnect CLK0 CLK1 CLK CLK3 4 SEGMENT 0 SEGMENT Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 S E G M E N T I N T E R C O N N E C T Block A/ 0-15 Block D/ 0-15 I 1 Block Interconnect Block B/ 0-15 Block C/ 0-15 SEGMENT G-008 MACH 5 Family

17 BLOCK DIAGRAM M5(LV)-56/XXX, M5A(3,5)-56/XXX Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect I 0 Block Interconnect I 3 Block C/ 0-15 Block B/ 0-15 Block B/ 0-15 Block C/ 0-15 S E G M E N T I N T E R C O N N E C T Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect I 1 Block Interconnect I CLK0 CLK1 CLK CLK3 4 Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 SEGMENT 0 SEGMENT 3 SEGMENT 1 SEGMENT 0446G-009 MACH 5 Family 1

18 BLOCK DIAGRAM M5(LV)-0/XXX, M5A3-0/XXX SEGMENT 0 SEGMENT 4 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect Block Interconnect I 0 Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 S E G M E N T I N T E R C O N N E C T CLK0 CLK1 CLK 4 CLK3 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 I 1 Block Interconnect I Block Interconnect I 3 Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 SEGMENT 1 SEGMENT SEGMENT G MACH 5 Family

19 BLOCK DIAGRAM M5(LV)-384/XXX, M5A3-384/XXX I 0 SEGMENT 0 SEGMENT 5 SEGMENT 4 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect I 3 Block Interconnect Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 S E G M E N T I N T E R C O N N E C T Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 CLK0 CLK1 CLK CLK3 I 1 Block Interconnect Block Interconnect I Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 SEGMENT 1 SEGMENT SEGMENT G-011 MACH 5 Family 19

20 BLOCK DIAGRAM M5(LV)-51/XXX, M5A3-51/XXX Continued CLK0 CLK1 CLK CLK3 I 0 4 SEGMENT 0 SEGMENT Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 S E G M E N T Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 I 1 Block Interconnect Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 SEGMENT 1 SEGMENT 0446G-01 0 MACH 5 Family

21 BLOCK DIAGRAM M5(LV)-51/XXX, M5A3-51/XXX SEGMENT 6 SEGMENT 5 Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect I 3 Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 I N T E R C O N N E C T Block A/ 0-15 Block D/ 0-15 Block A/ 0-15 Block D/ 0-15 Block Interconnect I Block Interconnect Block B/ 0-15 Block C/ 0-15 Block B/ 0-15 Block C/ 0-15 SEGMENT 3 SEGMENT 4 Continued 0446G-013 MACH 5 Family 1

22 ABSOLUTE MAXIMUM RATINGS M5 and M5A5 Storage Temperature C to +150 C Device Junction Temperature (Note 1) C or +150 C Supply Voltage with Respect to Ground V to +.0 V DC Input Voltage V to 5.5 V Static Discharge Voltage V Latchup Current (-40 C to +85 C) ma Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (T A ) Operating in Free Air C to +0 C Supply Voltage ( ) with Respect to Ground V to +5.5 V Industrial (I) Devices Ambient Temperature (T A ) Operating in Free Air C to +85 C Supply Voltage ( ) with Respect to Ground V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 5-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Typ Max Unit Output HIGH Voltage I OH = -3. ma, = Min, V IN = V IH or V IL.4 V (For M5-0, M5-384, M5-51, M5A5-18, V M5A5-19, M5A5-56 Devices) OH I OH = 0 ma, = Max, V IN = V IH or V IL 3.3 V Output HIGH Voltage I OH = -3. ma, = Min, V IN = V IH or V IL.4 V (For M5-18, M5-19, M5-56 Devices) I OH = -.5 ma, = 5.5 V, V IN = V IH or V IL 3.6 V V OL Output LOW Voltage (Note ) I OL = + ma, = Min, V IN = V IH or V IL 0.5 V V IH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 3).0 V V IL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 3) 0.8 V I IH Input HIGH Leakage Current V IN = 5.5, = Max (Note 4) 10 µa I IL Input LOW Leakage Current V IN = 0, = Max (Note 4) -10 µa I OZH Off-State Output Leakage Current HIGH V OUT = 5.5, = Max, V IN = V IH or V IL (Note 4) 10 µa I OZL Off-State Output Leakage Current LOW V OUT = 0, = Max, V IN = V IH or V IL (Note 4) -10 µa I SC Output Short-Circuit Current V OUT = 0.5 = Max, V IN = V IH or V IL (Note 5) ma Note: for M5-18, M5-19 and M5-56 devices. 130 for M5-0, M5-384, M5-51 and all M5A5-xxx devices.. Total I OL between ground pins should not exceed 64 ma. 3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 4. pin leakage is the worst case of I IL and I OZL or I IH and I OZH. 5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. MACH 5 Family

23 ABSOLUTE MAXIMUM RATINGS M5LV and M5A3 Storage Temperature C to +150 C Device Junction Temperature C Supply Voltage with Respect to Ground V to V DC Input Voltage V to 5.5 V Static Discharge Voltage V Latchup Current (-40 C to +85 C) ma Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (T A ) Operating in Free Air C to +0 C Supply Voltage ( ) with Respect to Ground V to +3.6 V Industrial (I) Devices Ambient Temperature (T A ) Operating in Free Air C to +85 C Supply Voltage ( ) with Respect to Ground V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 3.3-V DC CHARACTERISITICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Description Min Max Unit V OH Output HIGH Voltage = Min I OH = -100 µa -0. V V IN = V IH or V IL I OH = 3. ma.4 V V V OL Output LOW Voltage CC = Min I OL = 100 µa 0. V V IN = V IH or V IL I OH = ma (Note 1) 0.5 V V IH Input HIGH Voltage V OUT V OH Min or V OUT V OL Max (Note ) V V IL Input LOW Voltage V OUT V OH Min or V OUT V OL Max (Note ) V I IH Input HIGH Leakage Current V IN = 3.6, = Max (Note 3) 10 µa I IL Input LOW Leakage Current V IN = 0, = Max (Note 3) -10 µa I OZH Off-State Output Leakage Current HIGH V OUT = 3.6, = Max, V IN = V IH or V IL (Note 3) 10 µa I OZL Off-State Output Leakage Current LOW V OUT = 0, = Max, V IN = V IH or V IL (Note 3) -10 µa I SC Output Short-Circuit Current V OUT = 0.5 = Max, V IN = V IH or V IL (Note 4) ma Notes: 1. Total I OL between ground pins should not exceed 64 ma.. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 3. pin leakage is the worst case of I IL and I OZL or I IH and I OZH. 4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second. MACH 5 Family 3

24 M5(LV) TIMING PARAMETERS OVER OPERATING RANGES Min Max Min Max Min Max Min Max Min Max Min Max Unit Combinatorial Delay: t PDi Internal combinatorial propagation delay ns t PD Combinatorial propagation delay ns Registered Delays: t SS Synchronous clock setup time ns t SA Asynchronous clock setup time ns t HS Synchronous clock hold time ns t HA Asynchronous clock hold time ns t COSi Synchronous clock to internal output ns t COS Synchronous clock to output ns t COAi Asynchronous clock to internal output ns t COA Asynchronous clock to output ns Latched Delays: t SAL Latch setup time ns t HAL Latch hold time ns t PDLi Transparent latch internal ns t PDL Propagation delay through transparent latch ns t GOAi Gate to internal output ns t GOA Gate to output ns Input Register Delays: t SIRS Input register setup time using a synchronous clock ns t SIRA Input register setup time using an asynchronous clock ns t HIRS Input register hold time using a synchronous clock ns t HIRA Input register hold time using an asynchronous clock ns Input Latch Delays: t SIL Input latch setup time ns t HIL Input latch hold time ns t PDILi Transparent input latch ns Output Delays: t BUF Output buffer delay ns t SLW Slow slew rate delay ns t EA Output enable time ns t ER Output disable time ns 4 MACH 5 Family

25 M5(LV) TIMING PARAMETERS OVER OPERATING RANGES 1 (CONTINUED) Power Delays: t PL1 Power level 1 delay (Note ) t PL Power level delay (Note ) t PL3 Power level 3 delay (Note ) Min Max Min Max Min Max Min Max Min Max Min Max 4.0 (5.0) 6.0 (9.0) 9.0 (1.5) 4.0 (5.0) 6.0 (9.0) 9.0 (1.5) 4.0 (5.0) 6.0 (9.0) 9.0 (1.5) 4.0 (5.0) 6.0 (9.0) 9.0 (1.5) 4.0 (5.0) 6.0 (9.0) 9.0 (1.5) 4.0 (5.0) 6.0 (9.0) 9.0 (1.5) Additional Cluster Delay: t PT Product term cluster delay ns Interconnect Delays: t BLK Block interconnect delay ns t SEG Segment interconnect delay ns Reset and Preset Delays: t SRi Asynchronous reset or preset to internal register output ns t SR Asynchronous reset or preset to register output ns t SRR Reset and set register recovery time ns t SRW Asynchronous reset or preset width ns Clock Enable Delays: t CES Clock enable setup time ns t CEH Clock enable hold time ns Width: t WLS Global clock width low (Note 3) ns t WHS Global clock width high (Note 3) ns t WLA Product term clock width low ns t WHA Product term clock width high ns t GWA Gate width low (for low transparent) or high (for high transparent) ns t WIR Input register clock width low or high ns Unit ns ns ns MACH 5 Family 5

26 M5(LV) TIMING PARAMETERS OVER OPERATING RANGES 1 (CONTINUED) Frequency: f MAX f MAXA f MAXI External feedback, PAL block level. Min of 1/(t WLS + t WHS ) or 1/(t SS + t COS ) Internal feedback, PAL block level. Min of 1/(t WLS + t WHS ) or 1/(t SS +t COSi ) No feedback PAL block level. Min of 1/(t WLS + t WHS ) or 1/(t SS + t HS ) External feedback, PAL block level. Min of 1/(t WLA + t WHA ) or 1/(t SA + t COA ) Internal feedback, PAL block level. Min of 1/(t WLA + t WHA ) or 1/(t SA +t COAi ) No feedback, PAL block level. Min of 1/(t WLA + t WHA ) or 1/(t SA + t HA ) Maximum input register frequency 1/(t SIRS +t HIRS ) or 1/( x t WICW ) Min Max Min Max Min Max Min Max Min Max Min Max MHz MHz MHz MHz MHz MHz MHz Notes: 1. See Switching Test Circuits in the General Information Section of the Vantis 1999 Data Book.. Numbers in parentheses are for M5-18, M5-19, and M If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (f MAX /). Unit 6 MACH 5 Family

27 M5A(3,5) TIMING PARAMETERS OVER OPERATING RANGES Min Max Min Max Min Max Min Max Min Max Min Max Unit Combinatorial Delay: t PDi Internal combinatorial propagation delay ns t PD Combinatorial propagation delay ns Registered Delays: t SS Synchronous clock setup time ns t SA Asynchronous clock setup time ns t HS Synchronous clock hold time ns t HA Asynchronous clock hold time ns t COSi Synchronous clock to internal output ns t COS Synchronous clock to output ns t COAi Asynchronous clock to internal output ns t COA Asynchronous clock to output ns Latched Delays: t SAL Latch setup time ns t HAL Latch hold time ns t PDLi Transparent latch internal ns t PDL Propagation delay through transparent latch ns t GOAi Gate to internal output ns t GOA Gate to output ns Input Register Delays: t SIRS Input register setup time using a synchronous clock ns t SIRA Input register setup time using an asynchronous clock ns t HIRS Input register hold time using a synchronous clock ns t HIRA Input register hold time using an asynchronous clock ns Input Latch Delays: t SIL Input latch setup time ns t HIL Input latch hold time ns t PDILi Transparent input latch ns Output Delays: t BUF Output buffer delay ns t SLW Slow slew rate delay ns t EA Output enable time ns t ER Output disable time ns Power Delays: t PL1 Power level 1 delay ns t PL Power level delay ns t PL3 Power level 3 delay ns Additional Cluster Delay: t PT Product term cluster delay ns MACH 5 Family

28 M5A(3,5) TIMING PARAMETERS OVER OPERATING RANGES 1 (CONTINUED) Interconnect Delays: t BLK Block interconnect delay 0, 384 and ns t SEG Segment interconnect delay 0, 384, and ns t BLK Block interconnect delay 18, 19 and ns t SEG Segment interconnect delay 18, 19 and ns Reset and Preset Delays: t SRi Asynchronous reset or preset to internal register output ns t SR Asynchronous reset or preset to register output ns t SRR Reset and set register recovery time ns t SRW Asynchronous reset or preset width ns Clock Enable Delays: t CES Clock enable setup time ns t CEH Clock enable hold time ns Width: t WLS Global clock width low (Note ) ns t WHS Global clock width high (Note ) ns t WLA Product term clock width low ns t WHA Product term clock width high ns t GWA Gate width low (for low transparent) or high (for high transparent) ns t WIR Input register clock width low or high ns Frequency: f MAX f MAXA f MAXI External feedback, PAL block level Min of 1/(t WLS + t WHS ) or 1/(t SS + t COS ) Internal feedback, PAL block level Min of 1/(t WLS + t WHS ) or 1/(t SS +t COSi ) No feedback, PAL block level Min of 1/(t WLS + t WHS ) or 1/(t SS + t HS ) External feedback, PAL block level Min of 1/( t WLA + t WHA ) or 1/(t SA + t COA ) Internal feedback, PAL block level Min of 1/(t WLA + t WHA ) or 1/(t SA +t COAi ) No feedback, PAL block level Min of 1/(t WLA + t WHA ) or 1/(t SA + t HA ) Maximum input register frequency 1/(t SIRS +t HIRS ) or 1/( x t WICW ) Min Max Min Max Min Max Min Max Min Max Min Max MHz MHz MHz MHz MHz MHz MHz Notes: 1. See Switching Test Circuit in the General Information Section of the Vantis 1999 Data Book.. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (f MAX /) Unit 8 MACH 5 Family

29 CAPACITANCE 1 Parameter Symbol Parameter Description Test conditions Typ Unit C IN I/CLK pin V IN =.0 V 3.3 V or 5 V, 5 C, 1 MHz 1 pf C pin V OUT =.0 V 3.3 V or 5 V, 5 C, 1 MHz 10 pf Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where these parameters may be affected. I CC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected typical pattern is a -bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the application note entitled MACH 5 Power in the Application Notes section of the Vantis 1999 Data Book. I CC CURVES AT HIGH /LOW POWER MODES = 5 V or 3.3 V, T A = 5 C M5(LV)-51 high power M5(LV)-384 high power I CC (ma) M5(LV)-0 high power M5LV-56 high power M5(LV)-51 low power M5(LV)-384 low power M5(LV)-0 low power M5LV-56 low power M5LV-18 low power M5LV-18 high power Frequency (MHz) 0446G-048 Figure 8. I CC Curves at High/Low Power Modes MACH 5 Family 9

30 = 5 V, T A = 5 C M5-56 high power 500 M5-19 high power I CC (ma) M5-18 high power M5-56 low power M5-19 low power M5-18 low power Frequency (MHz) 0446G-049 Figure 9. I CC Curves at High/Low Power Modes 30 MACH 5 Family

31 100-PIN PQFP CONNECTION DIAGRAM Top View 100-Pin PQFP (68 ) M5(LV)-18 M5A(3,5)-18 0A13 0A1 0A11 0A8 0A 0A 0D 0D3 0D4 0D 0D8 0D11 0D1 0D13 M5(LV)-18 M5A(3,5)-18 M5-19 M5A(3,5)-19 M5(LV)-56 M5A(3,5)-56 0A 0A6 0A5 0A 0A1 0A0 0A 0A6 0A5 0A 0A1 0A0 A0 A1 A A3 A4 A5 A6 A 3A0 3A1 3A 3A3 3A4 3A5 3A6 3A M5-19 M5A(3,5)-19 M5(LV)-56 M5A(3,5)-56 0A14 0B1 0B 0B 1B 1B 1B1 1B13 1A14 0A1 0B1 0B 0B 1B 1B 1B1 1B13 1A1 0A1 0B1 0B 0B 1B 1B 1B1 1B13 1A1 TDI I0/CLK0 I1/CLK TCK TDO I3/CLK3 I/CLK TMS 3A1 3B13 3B1 3B11 3B8 3B 3B4 3B3 3B B B3 B4 B B8 B11 B1 B13 A1 A1 B13 B1 B11 B8 B B4 B3 B C C3 C4 C C8 C11 C1 C13 D1 0D14 0C13 0C1 0C11 0C8 0C 0C4 0C3 0C 1C 1C3 1C4 1C 1C8 1C11 1C1 1C13 1D M5(LV)-56 M5A(3,5)-56 1A 1A6 1A5 1A 1A1 1A0 A0 A1 A A3 A4 A5 A6 A M5(LV)-56 M5A(3,5)-56 M5-19 M5A(3,5)-19 1A 1A6 1A5 1A 1A1 1A0 D0 D1 D D3 D4 D5 D6 D M5-19 M5A(3,5)-19 M5(LV)-18 M5A(3,5)-18 1A13 1A1 1A11 1A8 1A 1A 1D 1D3 1D4 1D 1D8 1D11 1D1 1D13 M5(LV)-18 M5A(3,5) G-0 Pin Designations CLK = Clock = Ground I = Input = Input/Output NC = No Connect = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) MACH 5 Family 31

32 100-PIN TQFP CONNECTION DIAGRAM Top View 100-Pin TQFP (68 ) M5(LV)-18 0A13 0A1 0A11 0A8 0A 0A 0D 0D3 0D4 0D 0D8 0D11 0D1 0D13 M5(LV)-18 M5-19 0A 0A6 0A5 0A 0A1 0A0 A0 A1 A A3 A4 A5 A6 A M5-19 M5(LV)-56 0A 0A6 0A5 0A 0A1 0A0 3A0 3A1 3A 3A3 3A4 3A5 3A6 3A M5(LV) TDI I0/CLK0 I1/CLK TCK NC NC NC A14 0B1 0B 0B 1B 1B 1B1 1B13 1A14 0A1 0B1 0B 0B 1B 1B 1B1 1B13 1A1 0A1 0B1 0B 0B 1B 1B 1B1 1B13 1A1 TDO I3/CLK3 I/CLK TMS 3A1 3B13 3B1 3B11 3B8 3B 3B4 3B3 3B B B3 B4 B B8 B11 B1 B13 A1 A1 B13 B1 B11 B8 B B4 B3 B C C3 C4 C C8 C11 C1 C13 D1 0D14 0C13 0C1 0C11 0C8 0C 0C4 0C3 0C 1C 1C3 1C4 1C 1C8 1C11 1C1 1C13 1D14 M5(LV)-56 1A 1A6 1A5 1A 1A1 1A0 A0 A1 A A3 A4 A5 A6 A M5(LV)-56 M5-19 1A 1A6 1A5 1A 1A1 1A0 D0 D1 D D3 D4 D5 D6 D M5-19 M5(LV)-18 1A13 1A1 1A11 1A8 1A 1A 1D 1D3 1D4 1D 1D8 1D11 1D1 1D13 M5(LV) G-01 Pin Designations CLK = Clock = Ground I = Input = Input/Output NC = No Connect = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) MACH 5 Family

33 100-PIN TQFP CONNECTION DIAGRAM Top View 100-Pin TQFP (4 ) M5LV-18 M5A(3,5)-18 0A13 0A1 0A11 0A10 0A9 0A8 0A 0A 0D1 0D 0D3 0D4 0D 0D8 0D11 0D1 0D13 M5LV-18 M5A(3,5)-18 M5A(3,5)-19 0A11 0A10 0A 0A6 0A5 0A 0A1 0A0 0D1 A0 A1 A A3 A4 A5 A6 A M5A(3,5)-19 M5LV-56 M5A(3,5)-56 0A 0A6 0A5 0A 0A1 0A0 0D11 0D1 3D1 3A0 3A1 3A 3A3 3A4 3A5 3A6 3A M5LV-56 M5A(3,5) TDI I0/CLK0 I1/CLK TCK /O /O A14 0B1 0B 0B 1B 1B 1B1 1B13 1A14 0A1 0B1 0B 0B 1B 1B 1B1 1B13 1A1 0A1 0B1 0B 0B 1B 1B 1B1 1B13 1A1 TDO I3/CLK3 I/CLK TMS 3A1 3B13 3B1 3B11 3B8 3B 3B4 3B3 3B B B3 B4 B B8 B11 B1 B13 A1 A1 B13 B1 B11 B8 B B4 B3 B C C3 C4 C C8 C11 C1 C13 D1 0D14 0C13 0C1 0C11 0C8 0C 0C4 0C3 0C 1C 1C3 1C4 1C 1C8 1C11 1C1 1C13 1D14 M5LV-56 M5A(3,5)-56 1A 1A6 1A5 1A 1A1 1A0 1D11 1D1 D1 A0 A1 A A3 A4 A5 A6 A M5LV-56 M5A(3,5)-56 M5A(3,5)-19 1A8 1A 1A6 1A5 1A 1A1 1A0 1D3 D0 D1 D D3 D4 D5 D6 D D11 M5A(3,5)-19 M5LV-18 M5A(3,5)-18 1A13 1A1 1A11 1A10 1A8 1A 1A 1A1 1D 1D3 1D4 1D 1D8 1D10 1D11 1D1 1D13 M5LV-18 M5A(3,5) G-018 Pin Designations CLK = Clock = Ground I = Input = Input/Output NC = No Connect = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 3 D 15 Macrocell (0-15) PAL Block (A-D) Segment (0-3) MACH 5 Family 33

34 34 MACH 5 Family 144-PIN PQFP CONNECTION DIAGRAM Top View 144-Pin PQFP TDI I0/CLK0 I1/CLK TCK 0A8 0A9 0A10 0A11 0A1 0B1 0B5 0B 1B 1B5 1B1 1B13 1A1 1A11 1A10 1A9 1A8 0A1 0A13 0A14 0B1 0B5 0B 0B1 0B0 1B0 1B1 1B 1B5 1B1 1B13 1A14 1A13 1A1 0A14 0B1 0B10 0B 0B6 0B5 0B 0B1 1B1 1B 1B5 1B6 1B 1B10 1B1 1B13 1A14 M5(LV)-18 M5(LV)-56 M5(LV)-56 M5(LV)-56 M5(LV)-56 M5-19 M5-19 M5-19 M5-19 M5(LV)-18 M5(LV)-18 M5(LV) A 1A6 1A5 1A 1A1 1D3 1D4 1D 1D8 1D11 1D1 D1 D11 D8 D D4 D3 A1 A A3 A4 A5 A6 A 1A11 1A10 1A8 1A 1A6 1A5 1A 1D 1D3 1D4 1D 1D8 1D11 1D1 1D13 D D3 D4 D5 D6 D D8 D10 D11 1A13 1A1 1A11 1A10 1A8 1A 1A6 1A5 1A 1A1 1A0 1D0 1D1 1D 1D3 1D4 1D5 1D6 1D 1D8 1D10 1D11 1D1 1D A 0A6 0A5 0A 0A1 0D3 0D4 0D 0D8 0D11 0D1 3D1 3D11 3D8 3D 3D4 3D3 3A1 3A 3A3 3A4 3A5 3A6 3A 0A11 0A10 0A8 0A 0A6 0A5 0A 0D 0D3 0D4 0D 0D8 0D11 0D1 0D13 A A3 A4 A5 A6 A A8 A10 A11 0A13 0A1 0A11 A10 0A8 0A 0A6 0A5 0A 0A1 0A0 0D0 0D1 0D 0D3 0D4 0D5 0D6 0D 0D8 0D10 0D11 0D1 0D TDO I3/CLK3 I/CLK TMS 3A8 3A9 3A10 3A11 3A1 3B13 3B1 3B11 3B8 3B5 3B4 3B3 3B B B3 B4 B5 B8 B11 B1 B13 A1 A11 A10 A9 A8 A1 A13 A14 B13 B1 B11 B8 B5 B4 B3 B B1 B0 C0 C1 C C3 C4 C5 C8 C11 C1 C13 D14 D13 D1 0D14 0C13 0C1 0C11 0C10 0C8 0C 0C6 0C5 0C4 0C3 0C 0C1 1C1 1C 1C3 1C4 1C5 1C6 1C 1C8 1C10 1C11 1C1 1C13 1D G D 15 CLK = Clock = Ground I = Input = Input/Output NC = No Connect = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Pin Designations Macrocell (0-15) PAL Block (A-D) Segment (0-3)