Trigger/Timing Logic Unit (TLU) for AIDA Beam-Test

Transcription

1 Trigger/Timing Logic Unit (TLU) for AIDA Beam-Test David Cussans, AIDA Kick-Off, February 2011

2 Outline Exiting EUDET JRA1 TLU Aims for Mini-AIDA-TLU (mtlu) Specification Schedule Cost Aims for AIDA-TLU (atlu) Use of atlu as Beam-Interface (BIF) Summary 2 David Cussans, AIDA Kick-Off, Feb 2011

3 EUDET JRA1 TLU Designed to give a simple but flexible interface to trigger/timing signals at EUDET JRA1 beam-telescope Produces triggers from beam scintillators. EUDET-Memo David Cussans, AIDA Kick-Off, Feb 2011

4 JRA1 TLU Interface Different triggering modes: No handshake (trigger pulses high) Trigger-Busy handshake Trigger Data handshake 4 David Cussans, AIDA Kick-Off, Feb 2011

5 JRA1 TLU Interface Triggers can be vetoed by DUT raising TRIGGER_CLOCK line. Can be combined with simple trigger/busy handshake for dead-time free readouts that send a continuous stream of data. Send buffer almost full signal. Time-stamp stored for each trigger. 5 David Cussans, AIDA Kick-Off, Feb 2011

6 AIDA TLU Existing EUDET will continue to work and have compatible DUT interface. Need a new TLU Increased trigger rate: Move to one-trigger-perparticle for LHC detectors. FPGA system available for lifetime of AIDA Cheaper to produce TLUs for integration in home labs. 6 David Cussans, AIDA Kick-Off, Feb 2011

7 AIDA Mini-TLU (mtlu) Want to produce a prototype to test out ideas This mini-tlu will be cheaper and easier to produce than existing TLU Use new connector standard (FMC), increase lifetime. Enthusiastically adopted by CERN: 11 FMC projects already 7 David Cussans, AIDA Kick-Off, Feb 2011

8 AIDA mtlu specification Double-Width FMC with single LPC connector. Use e.g. Xilinx SP601 to host. 139mm 75mm 8 David Cussans, AIDA Kick-Off, Feb 2011

9 AIDA mtlu Front Panel Four PMT inputs (Lemo-00) One clock I/O (2- pole Lemo-00) One GPIO (Lemo-00) Two DUT (HDMI) 9 David Cussans, AIDA Kick-Off, Feb 2011

10 AIDA mtlu Interface Four PMT Inputs (Lemo-00) 10 Use ADCMP551 fast comparator. <1ns propagation, ~ 100ps dispersion with amplitude. Threshold by DAC. +/-5V range. Two DUT interfaces (HDMI) Wanted to use RJ45 (compatibility), but won't fit on FMC Dongles for conversion to LVDS/RJ45 or TTL/LEMO David Cussans, AIDA Kick-Off, Feb 2011

11 AIDA mtlu Interface Use clock circuitry inside FPGA to receive or generate clocks. Communication to DAQ by Gigabit Ethernet Use IPBus firmware developed for LHC. Will need a host to convert packets into EUDAQ format, but could be main DAQ PC 11 David Cussans, AIDA Kick-Off, Feb 2011

12 Versions of mtlu Different levels of build Assembled into box ( beam-test ready ) Assembled onto metal plate ( IKEA ) Approximate cost ~ 1000 each. FMC only - provide own FPGA ( Aldi ) Manufacture own from design files Aiming for hardware ~ April David Cussans, AIDA Kick-Off, Feb 2011

13 Beam Interface Prototype Requirement for CALICE beam-interface (BIF) for beam-test. Can use mtlu as prototype BIF 13 HDMI connector physically compatible with DIF-LDA link. Full atlu as a BIF Hardware should work but BIF-specific firmware needed. David Cussans, AIDA Kick-Off, Feb 2011

14 Full AIDA TLU Approximate specification: Twelve PMT inputs Six DUT inputs Low jitter clock generation Will need FPGA board with FMC-HPC (high pin count) connector. Firmware almost identical to mtlu. 14 David Cussans, AIDA Kick-Off, Feb 2011

15 Summary Work under-way to produce a AIDA mini-tlu Aiming for early release Low(er) cost way of integrating to EUDAQ at home lab. Fully specify atlu in light of mtlu experience Can use same hardware (and probably most of the firmware) as a Beam-Interface (BIF) 15 David Cussans, AIDA Kick-Off, Feb 2011

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