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1 KOREAN R&D ON THE 6-PULSE CONVERTER UNIT FOR ITER AC/DC CONVERTERS SOFE J. S. Oh 1), J. Choi 1), J. H. Suh 1), H. Liu 2), S. Lee 2), H. Park 2), W. Jung 2), S. Jo 2), H. Tan 3), J. Tao 3), P. Fu 4) 1) ITER Korea, National Fusion Research Institute, Republic of Korea 2) Dawonsys Corp., Republic of Korea 3) ITER Organization, France 4) Academy of Sciences Institute of Plasma Physics, China
2 ITER AC/DC Converters 1
3 ITER Coil Power Supply System French Power Transmission Grid (400 kv, 500 MW) RPC SYSTEM RPC 3 x 250 MVA SYSTEM AC DC Fast Discharge Unit 66 kv 3 x 300 MVA CS SYSTEM AC DC TF SYSTEM AC DC Switching Network Unit Fast Discharge Unit Fast Discharge Unit CC SYSTEM 22 kv AC DC CN/KO RF 2
4 Block Diagram of Coil Power Supplies Building 32 DL1 TC TF CC CC CC CCT1 CCT2 CCT3 CCS1 CCS2 CCS3 CCS CCS CCS Building 33 DL2 CS CS CS3U 1 2 CS CS CS2U 3 CS CS CS1U VS VS VS VS VS VS CS CS CS CS CS1L CS2L 4 CS CS CS3L 5 RPC1 RPC2 RPC3 6 Building 38/39 KO-DA CN-DA Phase-2 CCB1 CCB2 CCB3 CC CC CC CS VS TC CC CCS Total 1.35 kv/45 ka, 6 ea(+6ea) 1.35 kv/55 ka/, 14 ea(+2ea) 1.35 kv/22.5 ka, 2ea(+4ea) 0.7 kv/68 ka, 1 ea 0.1 kv/10 ka, 6 ea 0.45 kv/10 ka, 3 ea 32 ea (+12ea: Phase-2) 3
5 AC/DC Converter Building 31 m x 149 m HVAC Interconnecting Bus Bars 13m 11m 7m Installation Corridors Main DC Bus Converter Bars Reactors HV Transformer 4
6 KOREAN R&D ON ITER AC/DC Converters 5
7 Korean Package No. Item Set Input Max On-load Output Voltage Max Current 1 TF Converter 1 66kV/50Hz ±650V, ±160V 68kA 2 CS Converters 6 66kV/50Hz ±1050V ±45kA 3 VS Converters 2 66kV/50Hz ±1050V ±22.5kA 4 CCU/L Converters 6 22kV/50Hz ±65V ±10kA 5 CCS Converters 3 22kV/50Hz ±325V ±10kA 6 Dummy Load mH, 45kA(30s)/55kA(20s)/68kA(14s)/7.75kA 7 Master Controller 1 Integrated Controller of Coil Power Supply System 9 Spare 1 For Converters, Master Controllers, Transformers 10 Technical Support during Commissioning 6
8 Project Schedule and R&D Plan Key Milestone PCR-187 ( 10.9) PA ( 11.3) Contract ( 11.7) 1st Delivery ( 14.5) Building Last Delivery ( 16.12) SAT ( 18.2) 1 st Plasma ( 19.11) Procurement Schedule CD CA PD FD Manufacturing/FAT Installation SAT Integrated Test R&D R&D-1 R&D-2 Master Controller Master Controller Group 1 (CC/VS/DL) Group 2 (CS/TF) PA: Procurement Arrangement CD: Concept Design CA: Contract Award PD: Preliminary Design FD: Final Design MD: Manufacturing Design FAT: Factory Acceptance Test SAT: Site Acceptance Test PD FD/MD(1) CC/VS/DL FD/MD(2) Industry Works FAT CS / TF CC / VS FAT FAT CS INSTALL. FAT SAT 7
9 R&D-1 and R&D-2 R&D-1 R&D-2 R&D-1 R&D-2 8
10 AC/DC Converter R&D-1 9
11 R&D-1: Issues Mechanical Structure Clamping Design Current Sharing of Parallel Devices Fault Suppression Capability (FSC) 10
12 R&D-1: Design PARAMETERS 6 Pulse Converter Rating Maximum Fault Current Number of Thyristors per arm Thyristor Type Max. Load Voltage: 1.55 kv DC Current: ka Converter Capacity: 24 MVA 175 ka (FDR2001) inches Thyristor Peak Forward/Reverse Voltage 5.2 kv 11
13 R&D-1: Mechanical Structure AC Bus AC Bus DC Bus AC Bus DC Bus DC Bus DC Bus AC Bus AC Bus DC Bus DC Bus DC Bus Mechanical Structure for AC/DC Bus Bar 12
14 R&D-1: Clamping Design Single-side clamping design (left) and pressure distribution (right) Thyristor Clamping Pressure 110kN±15% (9~12.18MPa) 115 mm (Diameter) Double-side clamping design (left) and pressure distribution (right) 13
15 R&D-1: Fabricated Unit 3D Design Fabricated Unit Single Phase Thyristor Rectifier (1:6 Scale) Size: 2.1(W)x1.5(D)x2.7(H) m Weight: 2.5 ton 14
16 Current Imbalance Factor R&D-1: Current Sharing A A: Current Imbalance of 1.5 at rated value B: Current Imbalance of 1.1 at FSC value B Peak Current (ka) B: Detail Waveform of FSC condition 15
17 R&D-1: FSC Test Ferraz Fuse 1550 V, 2800 A, 17.8 MA 2 s Measured Data - Arc Voltage : 2.24 kv - I 2 t (melting) = 6.25 MA 2 s - I 2 t (total) = 9.11 MA 2 s - Breaking Current = 83.5 ka - Pre-arc RMS Current = 44.1 ka - Melting time = 3.2 ms - Clearing time = 5.1 ms Thyristor I 2 t = MA 2 s Thyristor Surge Current > 100 ka 16
18 AC/DC Converter R&D-2 17
19 R&D-2: Issues Current Sharing Improvement Structural Design for Full Scale Unit Rated Current Test for 6-Pulse Converter Installation and Maintenance 18
20 R&D-2: Design Parameters 6 Pulse Converter Rating Max. Load Voltage: 1.35 kv DC Current: 25 ka Converter Capacity: 32 MVA FSC Level 150 ka (DC terminal short) No. of Thyristors per arm 9+1 Thyristor Type Thyristor Peak Forward/Reverse Voltage 5 inches 5.2 kv 19
21 R&D-2: Current Sharing Improvement 9 ka Transformer for Test [9 ka, CH1~8: 200 A/div, CH9~10: 2 ka/div] 21 ka [21 ka, CH1~8: 500 A/div, CH9~10: 5 ka/div] 20
22 R&D-2: Structural Design for Full Scale Unit Integrated 2 layers (2009) ~2.5x1.5x3.9m Stacked 2 Layers (2010) ~4x3x6m Horizontal Layer (2011) ~2.8x4x3m For Ease of Fabrication and Maintenance! 21
23 R&D-2: Structural Cooling Design AC Bus Bar Cooling Path DC Bus Bar Cooling Path 22
24 R&D-2: Structural Seismic Analysis Mode 1 Mode 2 Natural Frequency (Mode 1) = Hz > 1.3 (6~7Hz) 23
25 R&D-2: Structural EM Force EM 500 ka F I d 1 I 2 L (σ max =20 MPa, δ max =0.35 mm) Max. Stress at Tie Rod = 20 MPa < MPa 24
26 R&D-2: Fabricated Converter Module Full Scale 6-Pulse Converter Unit 25
27 R&D-2: Rate Current Test Circuit 26
28 R&D-2: Rated Current Test Configuration 30 ka Current Test Configuration of 6-Pulse Converter Unit 27
29 Current [A] Current [A] Current [A] Current [A] Current [A] Current [A] R&D-2: Rated Current Test Result data1 data2 data3 data4 data5 data6 data7 data8 data9 data CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH Time [sec.] 1250 < R phase Current> Time [sec.] 1250 < S Phase Current> Time [sec.] 1250 < T Phase Current> % % % % % % Channel < R Phase Imbalance> Channel < S Phase Imbalance> Channel < T Phase Imbalance> 28
30 R&D-2: Installation Plan 29
31 R&D-2: Maintenance Plan 30
32 KOREAN R&D ON THE CONVERTER CONTROLLER FOR ITER AC/DC CONVERTERS WED Poster SP
33 ITER Converter Controller R&D Circulation Current Simulation and Test Double DSP interrupt timing T3 1msec T1 80μsec T2 260μsec 1 khz Fast Control Test 32
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