Standalone Linear Li-Ion Charger with Thermal Regulation. Features. Applications

Transcription

1 Standalne Linear Li-In Charger with Thermal Regulatin General Descriptin The is a cmplete linear charger fr single cell lithium-in batteries. With small TDFN-10 package and few external cmpnents, is well suited fr prtable applicatins. In additin, the is specifically designed t wrk within USB pwer specificatins. N external sense resistr and blcking dide are required. Charging current can be prgrammed externally with a single resistr. The built-in thermal regulatin facilitates charging with maximum pwer withut risk f verheating. The always precnditins the battery with 1/10 f the prgrammed charge current at the beginning f a charge cycle, after it verifies that the battery can be fast-charged. The autmatically terminates the charge cycle when the charge current drps t 1/10th the prgrammed value after the final flat vltage is reached. Features Prgrammable charge current up t 1.2A N MOSFET, sense resistr r blcking dide required Cmplete linear charger in TDFN-10 fr single cell li-in batteries Thermal regulatin maximizes charge rate withut risk f verheating Thermistr input fr temperature qualified charging Charges single cell Li-in batteries directly frm USB prt. Preset 4.2V charge vltage with ±1% accuracy Autmatic recharge Charge status indicatr C/10 charge terminatin Battery reverse leakage current less than 1uA Applicatins The features 13.5V maximum rating vltage fr AC adapter, and it prvides the charge current up t 1.2A. Other features include battery temperature mnitring, reverse current prtectin, shutdwn mde, charging current mnitr, under vltage lckut, autmatic recharge and status indicatr. Wireless handsets Hand-held instruments Prtable infrmatin appliances Revisin: 1.2 1/19

2 Typical Applicatin Circuit 3.7V Li-In Battery Pack ACIN = 4.5V~13.5V 1k 1k ACIN 1 1uF CHG_SB TS ENB 1uF 1uF PGOODB ISETA GND RSET Cmplete Charger Cycle V BAT I BAT 2.9V Precharge Threshld Prgrammed Charge Current 4.05V Recharge Threshld V Iset 1/10 Prgrammed Charge Current Fast Charge Phase Fast Charge Phase Cnstant Vltage Phase Standby Phase Re-charge Phase Revisin: 1.2 2/19

3 Cnnectin Diagrams Order infrmatin -42FF10NRR 42 Output vltage FF10 TDFN-10 Package NRR RHS & Halgen free package Rating: -40 t 85 C Package in Tape & Reel Tp View Order, Marking & Packing Infrmatin Package Prduct ID. Marking Packing TDFN-10-42FF10NRR EMP Tracking Cde Tape & Reel 5Kpcs PIN1 DOT Revisin: 1.2 3/19

4 Pin Functins Name TDFN-10 Functin Psitive Input Supply Vltage. Prvides pwer t the charger. ACIN can range frm 4.5V ACIN 1 t 6.5V and shuld be bypassed with at least a 1F capacitr. When ACIN drps t within 30mV abve the pin vltage, the enters shutdwn mde, drpping I t less than 1A. NC 2 Nt cnnected. Open-Drain Charge Status Output. An internal N-channel MOSFET cnnects CHG_SB pin t grund when the battery is charging. After the charge cycle is cmpleted, the internal CHG_SB 3 N-channel MOSFET is replaced by a weak pull-dwn f apprximately 25A, indicating an AC present cnditin. When the detects an under vltage lckut cnditin, CHG_SB is frced high impedance. Open-Drain Battery Pwer Gd Output. An internal N-channel MOSFET cnnects PGOODB 4 PGOODB pin t grund when ACIN is ver 4.2V. PGOODB is frced lw during nrmal peratin. GND 5 Grund. Charge Current Prgram, Charge Current Mnitr and Shutdwn Pin. The charge current is prgrammed by cnnecting a 1% resistr, RSET, t grund. When charging in cnstant-current mde, this pin servs t 1.5V. In all mdes, the vltage n this pin can be used t measure the charge current using the fllwing frmula: I = (VSET / RSET) * 500 ISETA 6 The ISETA pin can als be used t shutdwn the charger. Discnnecting the prgram resistr frm grund allws a 1A current t pull the ISETA pin high. When it reaches the 2.15V shutdwn threshld vltage, the charger enters shutdwn mde. This pin is als clamped t apprximately 2.5V. Recnnecting RSET t grund will return the charger t nrmal peratin. The ISETA pin must nt be directly shrted t grund at any cnditin. NC 7 Nt cnnected. ENB 8 Charge Enable Input (active lw). This pin is weakly pulled lw internally. TS pin is the input fr an external NTC thermistr. When the TS pin vltage is ut f the TS 9 windw, determined by the VTMIN and VTMAX, the stps charging and indicates a fault cnditin. Charge Current Output and battery vltage feedback. This pin prvides charge current 10 t the battery and regulates the final flat vltage t 4.2V. An internal precisin resistr divider frm this pin sets the flat vltage which is discnnected in shutdwn mde. Revisin: 1.2 4/19

5 Functinal Blck Diagram ACIN CHG_SB ACIN BAT Bdy Switch BS BS BS Regulatin Cntrller - + PGOODB + GND V ISETA 2.9V BAT + - Temperature Cntrller 1.5V 0.15V Disable ENB UVLO/OVP V BAT 4.05V + - Lgic Cntrller V COLD HOT V 0.5V TS FIG.1. Functinal Blck Diagram f Revisin: 1.2 5/19

6 State Diagram ERY THERMAL FAULT NO CHARGE CURRENT CHG_SB: WEAK PULL-DOWN N Fault POWER ON ISETA recnnected r UVLO/OVP cnditin stps Thermal Fault < 2.9V TRICKLE CHARGE MODE 1/10TH FULL CURRENT CHG_BS: STRONG PULL-DOWN > 2.9V SHUTDOWN MODE CHARGE MODE > 2.9V CHG_SB: Hi-Z in UVLO WEAK PULL-DOWN OTHERWISE ISETA flated, ISETA > 2.15V r UVLO/OVP cnditin FULL CURRENT CHG_SB: STRONG PULL-DOWN ISETA < 0.15V STANDBY MODE NO CHARGE CURRENT CHG_SB: WEAK PULL-DOWN < 2.9V 2.9V < < 4.05V FIG.2. flw chart Revisin: 1.2 6/19

7 Abslute Maximum Ratings (Ntes 1, 2) VACIN, V, VCHGSB, VPROODB, VEN -0.3V t 13.5V VISETA, VTS -0.3V t 3.6V Pwer Dissipatin (Nte 5) Strage Temperature Range -65 C t 150 C Junctin Temperature (TJ) 150 C Lead Temperature (Sldering, 10 sec.) 260 C Operating Ratings (Nte 1, 2) Supply Vltage 4.5V t 6.5V Operating Temperature Range -40 C t 85 C Thermal Resistance (JA, Nte 3)) Thermal Resistance (JC, Nte 4)) 110 C/W 8.5 C/W Electrical Characteristics TA = 25 C, VACIN = 5.0V; unless therwise specified. Symbl Parameter Cnditins Min Typ Max Units VACIN VOV Input Operating Vltage Range V VIN Over-vltage Lckut Threshld Frm VACIN Lw t High 7 V Charge Mde, RSET = 30K (Nte 6) 300 ua ICC Input Supply Current Standby Mde (Charge Terminated) Shutdwn Mde (RSET Nt 200 ua Cnnected, VACIN < V, VACIN < 150 ua VUV r VACIN > VOV) VFLOAT I ITRICKLE Regulated Output (Flat) Vltage Pin Current Trickle Charge Current 0 C TA 85 C V RSET = 1.5K, Current Mde 500 ma RSET = 0.75K, Current Mde 1000 ma Standby Mde, V = 4.2V ua Shutdwn Mde ua Sleep Mde, VACIN = 0V ua V < VTRICKLE, RSET = 1.5K 50 ma V < VTRICKLE, RSET = 0.75K 100 ma VTRICKLE VTRHYS VMSD VASD ITERM Trickle Charge Threshld Vltage RSET = 1.5K, V Rising 2.9 V Trickle Charge Hysteresis Vltage RSET = 1.5K 100 mv Manual Shutdwn Threshld ISETA Pin Rising 2.15 V Vltage ISETA Pin Falling 2.05 V VIN-V Lckut Threshld VACIN frm Lw t High 60 mv Vltage VACIN frm High t Lw 30 mv C/10 Terminatin Current RSET = 1.5K 0.1 ma/ma Threshld RSET = 0.75K 0.1 ma/ma VSET ISETA Pin Vltage RSET = 1.5K, Current Mde 1.5 V ICHG_SB CHG_SB Pin Weak Pull-Dwn VCHG_SB = 5.0V 25 ua Revisin: 1.2 7/19

8 Current VCHG_SB CHG_SB Pin Output Lw Vltage ICHG_SB = 5mA 0.35 V VPOOGDB PGOODB Pin Output Lw Vltage IPGOODB = 5mA 0.35 V VRECHRG TILM Recharge Battery Threshld Vltage VFLOAT V-RECHRG 150 mv Junctin Temperature in Cnstant Temperature Mde 120 (Thermal Regulatin) RON Pwer FET ON Resistance I = 500mA 375 mω TRECHARGE TTERM Recharge Cmparatr Filter Time V High t Lw 150 us Terminatin Cmparatr Filter Time I Falling Belw ICHG/10 1 ms ISET ISETA Pin Pull-up Current 1 ua VTS-COLD TS Pin Cld Threshld Vltage VTS Rising 2.5 V VCOLD-HYS TS Pin Cld Hysteresis Vltage 100 mv VTS-HOT TS Pin Ht Threshld Vltage VTS Falling 0.5 V VHOT-HYS TS Pin Ht Hysteresis Vltage 100 mv VRUN Enable Threshld 0.4 V Shutdwn Threshld 1.2 V Nte 1: Abslute Maximum ratings indicate limits beynd which damage may ccur. Electrical specificatins d nt apply when perating the device utside f its rated perating cnditins. Nte 2: All vltages are with respect t the ptential at the grund pin. Nte 3: θja is measured in the natural cnvectin at TA=25 n a high effective thermal cnductivity test bard (2 layers, 2S0P). Nte 4: θjc represents the resistance t the heat flws the chip t package tp case. Nte 5: Maximum Pwer dissipatin fr the device is calculated using the fllwing equatins: P D T - T ILM (Thermal Regulatin) A θ JA Where TILM is the thermal regulatin temperature, TA is the ambient temperature, and θ JA is the junctin-t-ambient thermal resistance. E.g. fr the TDFN-10 packageθja = 110 C/W, TILM = 120 C and using TA = 25 C, the maximum pwer dissipatin is fund t be 0.86W. The de-rating factr (-1/θJA) = -9.09mW/ C, thus belw 25 C the pwer dissipatin figure can be increased by 9.09mW per degree, and similarity decreased by this factr fr temperatures abve 25 C. Nte 6: Supply current includes PROG pin current but des nt include any current delivered t the battery thrugh the pin. Revisin: 1.2 8/19

9 Typical Perfrmance Characteristics Unless therwise specified, VACIN = 5.0V, TA = 25 C VSET vs. Temperature (V > 2.9V) VSET vs. Temperature (V < 2.9V) VSET (V) VSET v.s. Temperature Temperature ( ) VSET (V) VSET vs. Temperature Temperature ( ) I BAT (ma) V FLO A T ( V ) Charge Current vs. Battery Vltage Charge Current vs. Battery Vltage Rprg=3k Rprg=1.5k Rprg=1k Rprg=0.5k V (V) Regulated Output Vltage vs. Supply Vltage Regulated Output Vltage vs. Supply Vltage V ACIN (V) V FLO A T (V ) ITRICKLE (ma) Regulated Output Vltage vs. Temperature Regulated Output Vltage vs. Temperature Temperature ( ) Trickle Charge Current vs. Supply Vltage Trickle Charge Current vs. Supply Vltage RPROG=15KΩ RPROG=3KΩ RPROG=1.5KΩ RPROG=1KΩ VACIN (V) Revisin: 1.2 9/19

10 Operatin The is a single cell lithium-in battery charger using a cnstant-current/cnstant-vltage algrithm. It can deliver up t 1.2A f charge current (using a gd thermal PCB layut) with a final flat vltage accuracy f ±1%. The includes an internal P-channel pwer MOSFET and thermal regulatin circuitry. N blcking dide r external current sense resistr is required; thus, the basic charger circuit requires nly tw external cmpnents. Furthermre, the is capable f perating frm a USB pwer surce. Nrmal Charge Cycle A charge cycle begins when the vltage at the ACIN pin rises abve the UVLO threshld level and a 1% prgram resistr is cnnected frm the ISETA pin t grund r when a battery is cnnected t the charger utput. If the pin is less than 2.9V, the charger enters trickle charge mde. In this mde, the supplies apprximately 1/10 the prgrammed charge current t bring the battery vltage up t a safe level fr full current charging. When the pin vltage rises abve 2.9V, the charger enters cnstant-current mde, where the prgrammed charge current is supplied t the battery. When the pin appraches the final flat vltage (4.2V), the enters cnstant- vltage mde and the charge current begins t decrease. When the charge current drps t 1/10 f the prgrammed value, the charge cycle ends. Prgramming Charge Current The charge current is prgrammed using a single resistr frm the ISETA pin t grund. The battery charge current is 500 times the current ut f the ISETA pin. VSET is 1.5V when charging in cnstant-current mde. The prgram resistr and the charge current are calculated using the fllwing equatins: R SET 500V I CHG SET, I CHG 500V R SET SET The charge current ut f the pin can be determined at any time by mnitring the ISETA pin vltage using the fllwing equatin: I V R SET SET 500 Charge Terminatin A charge cycle is terminated when the charge current falls t 1/10th the prgrammed value after the final flat vltage is reached. This cnditin is detected by using an internal, filtered cmparatr t mnitr the ISETA pin. When the ISETA pin vltage falls belw 150mV fr lnger than TTERM (typically 1ms), charging is terminated. The charge current is latched ff and the enters standby mde, where the input supply current drps t 150uA. (Nte: C/10 terminatin is disabled in trickle charging and thermal limiting mdes). The draws n current frm the battery in standby mde. This feature reduces the charge and discharge cycles n the battery, further prlnging the battery life. Any external surce (VSET) that hlds the ISETA pin abve 150mV will prevent the frm terminating a charge cycle. Hwever, if the ISETA pin is cntrlled by external surce, current surcing frm the pin can be infinity (until the internal pwer MOSFET is burned ut r the pin vltage is clse t its final flat vltage), and the frmula fr charge current is nt valid anymre. When charging, transient lads n the pin can cause the ISETA pin t fall belw 150mV fr shrt perids f time befre the DC charge current has drpped t 1/10th the prgrammed value. The 1ms filter time (TTERM) n the terminatin cmparatr ensures that transient lads f this nature d nt result in premature charge cycle terminatin. Once the average charge current drps belw 1/10th the prgrammed value, the terminates the charge cycle and ceases t prvide any current thrugh the pin. This is the standby mde, and all lads n the pin must be supplied by the battery. In the standby mde, any signal belw the manual shutdwn threshld vltage (typically 2.15V) n the ISETA pin is transparent t. Revisin: /19

11 The cnstantly mnitrs the pin vltage in standby mde. If this vltage drps belw the 4.05V recharge threshld (VRECHRG), anther charge cycle begins and current is nce again supplied t the battery. T manually restart a charge cycle when in standby mde, the input vltage must be remved and reapplied, r the charger must be shut dwn and restarted using the ISETA pin. Charge Status Indicatr (CHG_SB) The charge status utput has three different states: strng pull-dwn (~10mA), weak pull-dwn (~25uA) and high impedance. The strng pull-dwn state indicates that the is in a charge cycle. Once the charge cycle has terminated, the pin state is determined by under-vltage lckut cnditins. A weak pull-dwn indicates that ACIN meets the UVLO cnditins and the is ready t charge. High impedance indicates that the is in under-vltage lckut mde: either VIN is less than 60mV abve the pin vltage r insufficient vltage is applied t the ACIN pin. A micrprcessr can be used t distinguish between these three states. This methd is discussed in the Applicatins Infrmatin sectin. Thermal Limiting An internal thermal feedback lp reduces the prgrammed charge current if the die temperature attempts t rise abve a preset value f apprximately 120 C. This feature prtects the frm excessive temperature and allws the user t push the limits f the pwer handling capability f a given circuit bard withut risk f damaging the. The charge current can be set accrding t typical (nt wrst-case) ambient temperature with the assurance that the charger will autmatically reduce the current in wrst-case cnditins. TDFN-10 pwer cnsideratins are discussed further in the Applicatins Infrmatin sectin. Under-vltage Lckut (UVLO) An internal under-vltage lckut circuit mnitrs the input vltage and keeps the charger in shutdwn mde until ACIN rises abve the under-vltage lckut threshld. The UVLO circuit has a built-in hysteresis f 150mV. Furthermre, t prtect against reverse current in the pwer MOSFET, the UVLO circuit keeps the charger in shutdwn mde if ACIN falls t within 30mV f the battery vltage. If the UVLO cmparatr is tripped, the charger will nt cme ut f shutdwn mde until ACIN rises 60mV abve the battery vltage. Manual Shutdwn At any pint in the charge cycle, the can be put int shutdwn mde by remving RSET thus flating the ISETA pin. This reduces the battery drain current t abut t 0uA and the supply current t less than 150uA. A new charge cycle can be initiated by recnnecting the prgram resistr. In manual shutdwn, the CHG_SB pin is in a weak pull- dwn state as lng as ACIN is high enugh t exceed the UVLO cnditins. The CHG_SB pin is in a high impedance state if the is in under-vltage lckut mde: either ACIN is within 60mV f the pin vltage r insufficient vltage is applied t the ACIN pin. Autmatic Recharge Once the charge cycle is terminated, the cntinuusly mnitrs the vltage n the pin using a cmparatr with a 2ms filter time (TRECHARGE). A charge cycle restarts when the battery vltage falls belw 4.05V (which crrespnds t apprximately 80% t 90% battery capacity). This ensures that the battery is kept at r near a fully charged cnditin and eliminates the need fr peridic charge cycle initiatins. CHG_SB utput enters a strng pull-dwn state during recharge cycles. Revisin: /19

12 Applicatin Infrmatin Stability Cnsideratins The cnstant-vltage mde feedback lp is stable withut an utput capacitr prvided a battery is cnnected t the charger utput. With n battery present, an utput capacitr is recmmended t reduce ripple vltage. When using high value, lw ESR ceramic capacitrs, it is recmmended t add a 1Ω resistr in series with the capacitr. N series resistr is needed if tantalum capacitrs are used. In cnstant-current mde, the ISETA pin is in the feedback lp, nt the battery. The cnstant-current mde stability is affected by the impedance at the ISETA pin. With n additinal capacitance n the ISETA pin, the charger is stable with prgram resistr values as high as 100k. Hwever, additinal capacitance n this nde reduces the maximum allwed prgram resistr. The ple frequency at the ISETA pin shuld be kept abve 100kHz. Therefre, if the ISETA pin is laded with a capacitance, CSET, the fllwing equatin can be used t calculate the maximum resistance value fr RSET: R SET 1 5 2π10 C SET Average, rather than instantaneus, charge current may be f interest t the user. Fr example, if a switching pwer supply perating in lw current mde is cnnected in parallel with the battery, the average current being pulled ut f the pin is typically f mre interest than the instantaneus current pulses. In such a case, a simple RC filter can be used n the ISETA pin t measure the average battery current as shwn in Figure 3. A 10kΩ resistr has been added between the ISETA pin and the filter capacitr t ensure stability. FIG.3. Islating capacitive lad n ISETA pin and filtering Pwer Dissipatin The cnditins that cause the t reduce charge current thrugh thermal feedback can be apprximated by cnsidering the pwer dissipated in the IC. Nearly all f this pwer dissipatin is generated by the internal MOSFET, this is calculated t be apprximately: PD = (ACIN V) I Where PD is the pwer dissipated, ACIN is the input supply vltage, V is the battery vltage and I is the charge current. The apprximate ambient temperature at which the thermal feedback begins t prtect the IC is: TA = 120 PD θja TA = 120 (ACIN V) I θja Example: An perating frm a 5V USB supply is prgrammed t supply 500mA full-scale current t a discharged Li-In battery with a vltage f 3.7V. Assuming θja is 110 /W, the ambient temperature at which the will begin t reduce the charge current is apprximately: TA = 120 (5V 3.7V) (500mA) 110 /W TA = W 100 /W = Revisin: /19

13 TA = 48.5 The can be used abve 55 ambient, but the charge current will be reduced frm 500mA. The apprximate current at a given ambient temperature can be apprximated by: I 120 C TA (ACIN V ) θ JA Using the previus example with an ambient temperature f 70, the charge current will be reduced t apprximately: I I 120 C 70 C 50 C (5 3.7) 110 C/W 143 C/A 349mA Mrever, when thermal feedback reduces the charge current, the vltage at the ISETA pin is als reduced prprtinally as discussed in the Operatin sectin. It is imprtant t remember that applicatins d nt need t be designed fr wrst-case thermal cnditins since the IC will autmatically reduce pwer dissipatin when the junctin temperature reaches apprximately 120. Thermal Cnsideratins Because f the small size f the TDFN-10 package, it is very imprtant t use a gd thermal PC bard layut t maximize the available charge current. The thermal path fr the heat generated by the IC is frm the die t the cpper lead frame, thrugh the package leads, (especially the grund lead) t the PC bard cpper. The PC bard cpper is the heat sink. The ftprint cpper pads (thermal land) shuld be as wide as pssible and expand ut t larger cpper areas t spread and dissipate the heat t the surrunding ambient. Feed-thrugh vias t inner r backside cpper layers are als useful in imprving the verall thermal perfrmance f the charger. Other heat surces n the bard, nt related t the charger, must als be cnsidered when designing a PC bard layut because they will affect verall temperature rise and the maximum charge current. Increasing Thermal Regulatin Current Reducing the vltage drp acrss the internal MOSFET can significantly decrease the pwer dissipatin in the IC. This has the effect f increasing the current delivered t the battery during thermal regulatin. One methd is by dissipating sme f the pwer thrugh an external cmpnent, such as a resistr r dide. Example: An perating frm a 5V wall adapter is prgrammed t supply 1A full-scale current t a discharged Li-In battery with a vltage f 3.7V. Assuming θja is 100 C/W, the apprximate charge current at an ambient temperature f 25 is: I 120 C 25 C 730mA (5V 3.7V) 100 C/W By drpping vltage acrss a resistr in series with a 5V wall adapter (shwn in Figure 4), the n-chip pwer dissipatin can be decreased, thus increasing the thermally regulated charge current Revisin: /19

14 FIG.4. A circuit t maximize charge current I 120 C 25 C (V I R V ) θ S CC JA Slving fr I using the quadratic frmula. I 1 2R CC [(V V S ) (V V S 2 4R ) CC (120 C TA ) ] θ JA (Nte: Large values f RCC will result in n slutin fr I. This indicates that the will nt generate enugh heat t require thermal regulatin.) Using RCC = 0.25Ω, VS = 5V, V = 3.7V, TA = 25 and θja = 100 /W we can calculate the thermally regulated charge current t be: I = 879.5mA While this applicatin delivers mre energy t the battery and reduces charge time in thermal mde, it may actually lengthen charge time in vltage mde if ACIN becmes lw enugh t put the int drput. This technique wrks best when RCC values are minimized t keep cmpnent size small and avid drput. Remember t chse a resistr with adequate pwer handling capability. ACIN Bypass Capacitr Many types f capacitrs can be used fr input bypassing, hwever, cautin must be exercised when using multilayer ceramic capacitrs. Because f the self-resnant and high Q characteristics f sme types f ceramic capacitrs, high vltage transients can be generated under sme start-up cnditins, such as cnnecting the charger input t a live pwer surce. Adding a 1.5Ω resistr in series with an X5R ceramic capacitr will minimize start-up vltage transients. Charge Current Sft-Start The includes a sft-start circuit t minimize the inrush current at the start f a charge cycle. When a charge cycle is initiated, the charge current ramps frm zer t the full-scale current ver a perid f apprximately 100us. This has the effect f minimizing the transient current lad n the pwer supply during start-up. Revisin: /19

15 CHG_SB Status Output Pin The CHG_SB pin can prvide an indicatin that the input vltage is greater than the under-vltage lckut threshld level. A weak pull-dwn current f apprximately 25uA indicates that sufficient vltage is applied t ACIN t begin charging. When a discharged battery is cnnected t the charger, the cnstant current prtin f the charge cycle begins and the CHG_SB pin pulls t grund. The CHG_SB pin can sink up t 10mA t drive an LED that indicates that a charge cycle is in prgress. When the battery is nearing full charge, the charger enters the cnstant-vltage prtin f the charge cycle and the charge current begins t drp. When the charge current drps belw 1/10 f the prgrammed current, the charge cycle ends and the strng pull-dwn is replaced by the 25uA pull-dwn, indicating that the charge cycle has ended. If the input vltage is remved r drps belw the under-vltage lckut threshld, the CHG_SB pin becmes high impedance. Figure 5 shws that by using tw different value pull-up resistrs, a micrprcessr can detect all three states frm this pin. FIG.5. Using a micrprcessr t determine CHG_SB state T detect when the is in charge mde, frce the digital utput pin (OUT) high and measure the vltage at the CHG_SB pin. The internal N-channel MOSFET will pull the pin vltage lw even with the 2k pull-up resistr. Once the charge cycle terminates, the N-channel MOSFET is turned ff and a 25uA current surce is cnnected t the CHG_SB pin. The IN pin will then be pulled high by the 2k pull-up resistr. T determine if there is a weak pull-dwn current, the OUT pin shuld be frced t a high impedance state. The weak current surce will pull the IN pin lw thrugh the 800k resistr; if CHG_SB is high impedance, the IN pin will be pulled high, indicating that the part is in a UVLO state. Reverse Plarity Input Vltage Prtectin In sme applicatins, prtectin frm reverse plarity vltage n VIN is desired. If the supply vltage is high enugh, a series blcking dide can be used. In ther cases, where the vltage drp must be kept lw a P-channel MOSFET can be used (as shwn in Figure 6). FIG.6. Lw lss input reverse plarity prtectin Revisin: /19

16 USB and Wall Adapter Pwer The allws charging frm bth a wall adapter and a USB prt. Figure 7 shws an example f hw t cmbine wall adapter and USB pwer inputs. A P-channel MOSFET, MP1, is used t prevent back cnducting int the USB prt when a wall adapter is present and a Schttky dide, D1, is used t prevent USB pwer lss thrugh the 1k pull-dwn resistr. Typically a wall adapter can supply mre current than the 500mA-limited USB prt. Therefre, an N-channel MOSFET, MN1, and an extra 10k prgram resistr are used t increase the charge current t 580mA when the wall adapter is present. FIG.7. Cmbining wall adapter and USB pwer Battery Temperature Mnitring The cntinuusly mnitrs battery temperature by measuring the vltage between the TS and GND pins. The has an internal current surce t prvide the bias fr the mst cmmn 10kΩ negative-temperature cefficient thermal resistr (NTC) (see Figure 8). The cmpares the vltage n the TS pin against the internal VTS_HIGH and VTS_LOW threshlds t determine if charging is allwed. When the temperature utside the VTS_HIGH and VTS_LOW threshlds is detected, the device will immediately stp the charge. The stps charge and keep mnitring the battery temperature when the temperature sense input vltage is back t the threshld between VTS_HIGH and VTS_LOW, the charger will be resumed. Charge is resumed when the temperature returns t the nrmal range. Hwever the user may mdify the threshlds by the negative-temperature cefficient thermal resistr. The capacitr shuld be placed clse t TS pin and cnnected t the grund plane. The capacitance value (0.1uF t 10uF) shuld be selected accrding t the quality f PCB layut. FIG.8. The battery thermal detecting circuit Revisin: /19

17 Package Outline Drawing TDFN-10L (3x3 mm) Symbl Dimensin in mm Expsed pad Min Max Dimensin in mm A Min Max A D A E b D E e L BSC 0.50 Revisin: /19

18 Revisin Histry Revisin Date Descriptin Original Skip Preliminary 2. Revise page2 Typical Applicatin Circuit 3. Revise page4 Pin Functins 4. Revise page7~8 Abslute Maximum Ratings & Electrical Characteristics 5. Revise page16 FIG Mdifying the maximum input perating frm13.5v t 6.5V. 1. Added V RUN peratin in electrical characteristics. 2. Updated the package utline drawing. Revisin: /19

19 Imprtant Ntice All rights reserved. N part f this dcument may be reprduced r duplicated in any frm r by any means withut the prir permissin f ESMT. The cntents cntained in this dcument are believed t be accurate at the time f publicatin. ESMT assumes n respnsibility fr any errr in this dcument, and reserves the right t change the prducts r specificatin in this dcument withut ntice. The infrmatin cntained herein is presented nly as a guide r examples fr the applicatin f ur prducts. N respnsibility is assumed by ESMT fr any infringement f patents, cpyrights, r ther intellectual prperty rights f third parties which may result frm its use. N license, either express, implied r therwise, is granted under any patents, cpyrights r ther intellectual prperty rights f ESMT r thers. Any semicnductr devices may have inherently a certain rate f failure. T minimize risks assciated with custmer's applicatin, adequate design and perating safeguards against injury, damage, r lss frm such failure, shuld be prvided by the custmer when making applicatin designs. ESMT's prducts are nt authrized fr use in critical applicatins such as, but nt limited t, life supprt devices r system, where failure r abnrmal peratin may directly affect human lives r cause physical injury r prperty damage. If prducts described here are t be used fr such kinds f applicatin, purchaser must d its wn quality assurance testing apprpriate t such applicatins. Revisin: /19