MOS INTEGRATED CIRCUIT

Transcription

1 DATA SHEET 128M-bit Synchronous DRAM 4-bank, LVTTL MOS INTEGRATED CIRCUIT µpd Description The µpd is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097, (word bit bank). The synchronous DRAM achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAM is compatible with Low Voltage TTL (LVTTL). This product is packaged in 54-pin TSOP (II). Features Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge Pulsed interface Possible to assert random column address in every cycle Quad internal banks controlled by (A13) and (A12) Byte control by LM and UM Programmable Wrap sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable latency (2 and 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh 16 organization Single 3.3 V ± 0.3 V power supply LVTTL compatible inputs and outputs 4,096 refresh cycles / 64 ms Burst termination by Burst stop command and Precharge command The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0344N10 (Ver.1.0) Date Published February 2003 (K) Japan URL: Elpida Memory, Inc Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

2 Ordering Information Part number Organization (word bit bank) Clock frequency MHz (MAX.) Package µpd g5-a75a-9jf 2M pin Plastic TSOP (II) µpd g5-a75-9jf 133 µpd g5-a80-9jf 125 µpd g5--9jf 100 µpd g5-a75l-9jf 133 µpd g5-a80l-9jf Data Sheet E0344N10 (Ver. 1.0)

3 Part Number [ x16 ] NEC Memory µpd g5 - A75L Synchronous DRAM Memory density 128 : 128M bits Organization Low Power 16 : x16 Minimum cycle time Number of banks 3 : 4 banks, LVTTL 75A : 7.5 ns ( : 7.5 ns ( : 8 ns (125 MHz) 10 : 10 ns (100 MHz) Low voltage A : 3.3 V ± 0.3 V Package G5 : TSOP (II) Data Sheet E0344N10 (Ver. 1.0) 3

4 Pin Configurations /xxx indicates active low signal. 54-pin Plastic TSOP (II) 2M words 16 bits 4 banks VCC 0 VCCQ 1 2 VSSQ 3 4 VCCQ 5 6 VSSQ 7 VCC LM (A13) (A12) A0 A1 A2 A3 VCC Vss 15 VssQ VccQ VssQ 10 9 VccQ 8 Vss NC UM NC A11 A9 A8 A7 A6 A5 A4 Vss A0 to A11 Note : Address inputs (A13), (A12) : Bank select 0 to 15 : Data inputs / outputs : Clock input : Clock enable : Chip select : Row address strobe : Column address strobe : enable LM : Lower mask enable UM : Upper mask enable VCC VSS VCCQ VSSQ NC : Supply voltage : Ground : Supply voltage for : Ground for : No connection Note A0 to A11 : Row address inputs A0 to A8 : Column address inputs 4 Data Sheet E0344N10 (Ver. 1.0)

5 Block Diagram Clock Generator Bank D Bank C Address Mode Register Row Address Buffer & Refresh Counter Row Decoder Bank B Bank A Decoder Control Logic Column Address Buffer & Burst Counter Sense Amplifier Column Decoder & Latch Circuit Data Control Circuit Latch Circuit Input & Output Buffer M Data Sheet E0344N10 (Ver. 1.0) 5

6 CONTENTS 1. Input / Output Pin Function s Simplified State Diagram Truth Table Truth Table M Truth Table Truth Table Operative Table Truth Table for Initialization Programming the Mode Register Mode Register Burst Length and Sequence Address Bits of Bank-Select and Precharge Precharge Auto Precharge with Auto Precharge with Auto Precharge / Interval to Interval to Interval to Interval to Interval Burst Termination Burst Stop Precharge Termination Precharge Termination in READ Cycle Precharge Termination in WRITE Cycle Data Sheet E0344N10 (Ver. 1.0)

7 13. Electrical Specifications AC Parameters for Timing AC Parameters for Timing Relationship between Frequency and Latency Mode Register Set Power on Sequence and CBR (Auto) Refresh Function Clock Suspension during Burst (using Function) Clock Suspension during Burst (using Function) Power Down Mode and Clock Mask CBR (Auto) Refresh Self Refresh (Entry and Exit) Random Column (Page with Same Bank) Random Column (Page with Same Bank) Random Row (Ping-Pong Banks) Random Row (Ping-Pong Banks) and Interleaved Column Cycle Interleaved Column Cycle Auto Precharge after Burst Auto Precharge after Burst Full Page Cycle Full Page Cycle Byte Operation Burst and Single (Option) Full Page Random Column Full Page Random Column PRE (Precharge) Termination of Burst Package Drawing Recommended Soldering Conditions Data Sheet E0344N10 (Ver. 1.0) 7

8 1. Input / Output Pin Function Pin name Input / Output Function Input is the master clock input. Other inputs signals are referenced to the rising edge. Input determine validity of the next (clock). If is high, the next rising edge is valid otherwise it is invalid. If the rising edge is invalid, the internal clock is not issued and the µpd45128xxx suspends operation. When the µpd45128xxx is not in burst mode and is negated, the device enters power down mode. During power down mode, must remain low. Input low starts the command input cycle. When is high, commands are ignored but operations continue.,, Input, and have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 - A11 Input Row Address is determined by A0 - A11 at the (clock) rising edge in the active command cycle. It does not depend on the bit organization. Column Address is determined by A0 - A9, A11 at the rising edge in the read or write command cycle. It depends on the bit organization: A0 - A8 for 16 device. defines the precharge mode. When is high in the precharge command cycle, all banks are precharged when is low, only the bank selected by (A13) and (A12) is precharged. When is high in read or write command cycle, the precharge starts automatically after the burst access., Input (A13) and (A12) are the bank select signal. In command cycle, (A13) and (A12) low select bank A, (A13) high and (A12) low select bank B, (A13) low and (A12) high select bank C and then (A13) and (A12) high select bank D. UM, LM Input M controls I/O buffers. In 16 products, UM and LM control upper byte and lower byte I/O buffers, respectively. In read mode, UM and LM controls the output buffers like a conventional /OE pin. UM and LM high and UM and LM low turn the output buffers off and on, respectively. The UM and LM latency for the read is two clocks. In write mode, UM and LM controls the word mask. Input data is written to the memory cell if UM and LM is low but not if UM and LM is high. The UM and LM latency for the write is zero Input / Output pins have the same function as I/O pins on a conventional DRAM. VCC, VSS, VCCQ, VSSQ (Power supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers. 8 Data Sheet E0344N10 (Ver. 1.0)

9 2. s Mode register set command Fig.1 Mode register set command (,,, = Low) The µpd45128xxx has a mode register that defines how the device operates. In this command, A0 through A11, (A13) and (A12) are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2 (trsc) following this command, the µpd45128xxx cannot accept any other commands. (A13), (A12) Add H command (, = Low,, = High) Fig.2 Row address strobe and bank activate command The µpd45128xxx has four banks, each with 4,096 rows. This command activates the bank selected by (A13) and (A12) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM s falling. (A13), (A12) H Add Row Row Precharge command Fig.3 Precharge command (,, = Low, = High) This command begins precharge operation of the bank selected by (A13) and (A12). When is High, all banks are precharged, regardless of (A13) and (A12). When is Low, only the bank selected by (A13) and (A12) is precharged. After this command, the µpd45128xxx can t accept the activate command to the precharging bank during trp (precharge to activate command period). This command corresponds to a conventional DRAM s rising. (A13), (A12) (Precharge select) Add H Data Sheet E0344N10 (Ver. 1.0) 9

10 command Fig.4 Column address and write command (,, = Low, = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks. (A13), (A12) H Add Col. command Fig.5 Column address and read command (, = Low,, = High) data is available after latency requirements have been met. This command sets the burst start address given by the column address. (A13), (A12) H Add Col. CBR (auto) refresh command Fig.6 CBR (auto) refresh command (,, = Low,, = High) This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During trc period (from refresh command to refresh or activate command), the µpd45128xxx cannot accept any other command. (A13), (A12) Add H 10 Data Sheet E0344N10 (Ver. 1.0)

11 Self refresh entry command Fig.7 Self refresh entry command (,,, = Low, = High) After the command execution, self refresh operation continues while remains low. When goes high, the µpd45128xxx exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. (A13), (A12) Add Burst stop command (, = Low,, = High) Fig.8 Burst stop command in Full Page Mode This command can stop the current burst operation. (A13), (A12) Add H No operation Fig.9 No operation ( = Low,,, = High) This command is not an execution command. No operations begin or terminate by this command. (A13), (A12) Add H Data Sheet E0344N10 (Ver. 1.0) 11

12 3. Simplified State Diagram 12 Data Sheet E0344N10 (Ver. 1.0)

13 4. Truth Table 4.1 Truth Table Function Symbol, A11, n 1 n A9 - A0 Device deselect DESL H H No operation NOP H L H H H Burst stop BST H L H H L READ H L H L H V L V with auto precharge READA H L H L H V H V WRIT H L H L L V L V with auto precharge WRITA H L H L L V H V Bank activate ACT H L L H H V V V Precharge select bank PRE H L L H L V L Precharge all banks PALL H L L H L H Mode register set MRS H L L L L L L V Remark H = High level, L = Low level, = High or Low level (Don't care), V = Valid data input 4.2 M Truth Table Function Symbol M n 1 n U L Upper byte write enable / output enable ENBU H L Lower byte write enable / output enable ENBL H L Upper byte write inhibit / output disable MASKU H H Lower byte write inhibit / output disable MASKL H H Remark H = High level, L = Low level, = High or Low level (Don't care) 4.3 Truth Table Current state Function Symbol Address n 1 n Activating Clock suspend mode entry H L Any Clock suspend mode L L Clock suspend Clock suspend mode exit L H Idle CBR (auto) refresh command REF H H L L L H Idle Self refresh entry SELF H L L L L H Self refresh Self refresh exit L H L H H H L H H Idle Power down entry H L Power down Power down exit L H H L H L H H H Remark H = High level, L = Low level, = High or Low level (Don't care) Data Sheet E0344N10 (Ver. 1.0) 13

14 4.4 Operative Table Note1 (1/3) Current state Address Action Notes Idle H DESL Nop or power down 2 L H H NOP or BST Nop or power down 2 L H L H BA, CA, READ/READA ILLEGAL 3 L H L L BA, CA, WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT Row activating L L H L BA, PRE/PALL Nop L L L H REF/SELF CBR (auto) refresh or self refresh 4 L L L L Op-Code MRS Mode register accessing Row active H DESL Nop L H H NOP or BST Nop L H L H BA, CA, READ/READA Begin read : Determine AP 5 L H L L BA, CA, WRIT/WRITA Begin write : Determine AP 5 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL Precharge 6 L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H DESL Continue burst to end Row active L H H H NOP Continue burst to end Row active L H H L BST Burst stop Row active L H L H BA, CA, READ/READA Terminate burst, new read : Determine AP 7 L H L L BA, CA, WRIT/WRITA Terminate burst, start write : Determine AP 7, 8 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL Terminate burst, precharging L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H DESL Continue burst to end recovering L H H H NOP Continue burst to end recovering L H H L BST Burst stop Row active L H L H BA, CA, READ/READA Terminate burst, start read : Determine AP 7, 8 L H L L BA, CA, WRIT/WRITA Terminate burst, new write : Determine AP 7 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL Terminate burst, precharging 9 L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 14 Data Sheet E0344N10 (Ver. 1.0)

15 (2/3) Current state Address Action Notes with auto H DESL Continue burst to end Precharging precharge L H H H NOP Continue burst to end Precharging L H H L BST ILLEGAL L H L H BA, CA, READ/READA ILLEGAL 3 L H L L BA, CA, WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL ILLEGAL 3 L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL with auto precharge H DESL Continue burst to end recovering with auto precharge L H H H NOP Continue burst to end recovering with auto precharge L H H L BST ILLEGAL L H L H BA, CA, READ/READA ILLEGAL 3 L H L L BA, CA, WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL ILLEGAL 3 L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Precharging H DESL Nop Enter idle after trp L H H H NOP Nop Enter idle after trp L H H L BST ILLEGAL L H L H BA, CA, READ/READA ILLEGAL 3 L H L L BA, CA, WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL Nop Enter idle after trp L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Row activating H DESL Nop Enter bank active after trcd L H H H NOP Nop Enter bank active after trcd L H H L BST ILLEGAL L H L H BA, CA, READ/READA ILLEGAL 3 L H L L BA, CA, WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3, 10 L L H L BA, PRE/PALL ILLEGAL 3 L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Data Sheet E0344N10 (Ver. 1.0) 15

16 (3/3) Current state Address Action Notes recovering H DESL Nop Enter row active after tdpl L H H H NOP Nop Enter row active after tdpl L H H L BST Nop Enter row active after tdpl L H L H BA, CA, READ/READA Start read, Determine AP 8 L H L L BA, CA, WRIT/WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL ILLEGAL 3 L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL recovering H DESL Nop Enter precharge after tdpl with auto precharge L H H H NOP Nop Enter precharge after tdpl L H H L BST Nop Enter precharge after tdpl L H L H BA, CA, READ/READA ILLEGAL 3, 8 L H L L BA, CA, WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, PRE/PALL ILLEGAL L L L H REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Refreshing H DESL Nop Enter idle after trc L H H NOP/BST Nop Enter idle after trc L H L READ/WRIT ILLEGAL L L H ACT/PRE/PALL ILLEGAL L L L REF/SELF/MRS ILLEGAL Mode register H DESL Nop Enter idle after trsc accessing L H H H NOP Nop Enter idle after trsc L H H L BST ILLEGAL L H L READ/WRIT ILLEGAL L L ACT/PRE/PALL/ REF/SELF/MRS ILLEGAL Notes 1. All entries assume that was active (High level) during the preceding clock cycle. 2. If all banks are idle, and is inactive (Low level), µpd45128xxx will enter Power down mode. All input buffers except will be disabled. 3. Illegal to bank in specified states Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and is inactive (Low level), µpd45128xxx will enter Self refresh mode. All input buffers except will be disabled. 5. Illegal if trcd is not satisfied. 6. Illegal if tras is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tdpl. 10. Illegal if trrd is not satisfied. Remark H = High level, L = Low level, = High or Low level (Don t care), V = Valid data 16 Data Sheet E0344N10 (Ver. 1.0)

17 4.5 Truth Table for Current State Address Action Notes n 1 n Self refresh H INVALID, (n 1) would exit self refresh L H H Self refresh recovery L H L H H Self refresh recovery L H L H L ILLEGAL L H L L ILLEGAL L L Maintain self refresh Self refresh recovery H H H Idle after trc H H L H H Idle after trc H H L H L ILLEGAL H H L L ILLEGAL H L H ILLEGAL H L L H H ILLEGAL H L L H L ILLEGAL H L L L ILLEGAL Power down H INVALID, (n 1) would exit power down L H H EXIT power down Idle L H L H H H EXIT power down Idle L L Maintain power down mode All banks idle H H H Refer to operations in Operative Table H H L H Refer to operations in Operative Table H H L L H Refer to operations in Operative Table H H L L L H CBR (auto) Refresh H H L L L L Op-Code Refer to operations in Operative Table H L H Refer to operations in Operative Table H L L H Refer to operations in Operative Table H L L L H Refer to operations in Operative Table H L L L L H Self refresh 1 H L L L L L Op-Code Refer to operations in Operative Table L Power down 1 Row active H Refer to operations in Operative Table L Power down 1 Any state other than H H Refer to operations in Operative Table listed above H L Begin clock suspend next cycle 2 L H Exit clock suspend next cycle L L Maintain clock suspend Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. Must be legal command as defined in Operative Table. Remark H = High level, L = Low level, = High or Low level (Don't care) Data Sheet E0344N10 (Ver. 1.0) 17

18 5. Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling. (2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum trp is satisfied, the mode register can be programmed. After the mode register set cycle, trsc (2 minimum) pause must be satisfied as well. (4) Two or more CBR (Auto) refresh must be performed. Remarks 1. The sequence of Mode register programming and Refresh above may be transposed. 2. and M must be held high until the Precharge command is issued to ensure data-bus. 18 Data Sheet E0344N10 (Ver. 1.0)

19 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits A11 through A0, (A13) and (A12) as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields Options : A11 through A7, (A13), (A12) latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued before at least 2 have elapsed. Latency latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device Relationship between Frequency and Latency shows the relationship of latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either Sequential or Interleave. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length. Data Sheet E0344N10 (Ver. 1.0) 19

20 7. Mode Register (A13) (A12) 0 0 (A13) (A12) x (A13) (A12) (A13) (A12) x (A13) (A12) 0 x x 0 A JEDEC Standard Test Set (refresh counter test) A11 x A11 A11 x A11 x x A9 A9 1 A9 A9 x A9 A8 A8 0 A8 0 LTMODE WT 1 0 Use in future A8 1 A8 A7 A7 A7 A7 A6 1 V A7 A6 A6 A6 A6 A5 A5 A5 A5 V A5 A4 A4 A4 A4 V A4 V V BL V V Burst and Single (for Through Cache) Vender Specific LTMODE WT BL Mode Register Set A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 V = Valid x = Don t care Burst length Bits WT = R R R Full page WT = R R R R Wrap type 0 1 Sequential Interleave Latency mode Bits latency R R 2 3 R R R R Remark R : Reserved Mode Register Set Timing A0 - A11, (13), (A12) Mode Register Set 20 Data Sheet E0344N10 (Ver. 1.0)

21 7.1 Burst Length and Sequence [Burst of Two] Starting address (column address A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [Burst of Four] Starting address (column address A1 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, , 2, 3, 0 1, 0, 3, , 3, 0, 1 2, 3, 0, , 0, 1, 2 3, 2, 1, 0 [Burst of Eight] Starting address (column address A2 - A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, , 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, , 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, , 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, , 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, , 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, , 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, , 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Full page burst is an extension of the above tables of sequential addressing, with the length being 512 (for 8M 16 device). Data Sheet E0344N10 (Ver. 1.0) 21

22 8. Address Bits of Bank-Select and Precharge Row A0 A1 ( command) A2 A3 A4 A5 A6 A7 A8 A9 A11 (A12) (A13) (A12) (A13) Result Select Bank A command Select Bank B command 1 0 Select Bank C command 1 1 Select Bank D command A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 (A12) (A13) (Precharge command) (A12) (A13) x x x : Don t care Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 x (A12) (A13) 0 1 disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst) ( strobes) (A12) (A13) Result 0 0 enables / commands 0 1 enables / commands for Bank B 1 0 enables / commands for Bank C 1 1 enables / commands 22 Data Sheet E0344N10 (Ver. 1.0)

23 9. Precharge The precharge command can be issued anytime after tras (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after trp is satisfied. The parameter trp is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. It is depending on the latency and clock cycle time. T0 T1 T2 T3 T4 T5 T6 T7 Burst length=4 T8 latency = 2 READ PRE Q1 Q2 Q3 Q4 latency = 3 READ PRE Q1 Q2 Q3 Q4 (tras must be satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter tdpl must be satisfied. The tdpl (MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tdpl (MIN.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference plus means time after the reference. latency 2 1 +tdpl (MIN.) 3 2 +tdpl (MIN.) Data Sheet E0344N10 (Ver. 1.0) 23

24 10. Auto Precharge During a read or write command cycle, controls whether auto precharge is selected. high in the or command ( with Auto precharge command or with Auto precharge command), auto precharge is selected and begins automatically. The tras must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after trp has been satisfied. In write cycle, the tdal must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on both the latency programmed into the mode register and whether read or write cycle with Auto Precharge During a read cycle, the auto precharge begins one clock earlier ( latency of 2) or two clocks earlier ( latency of 3) the last data word output. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 latency = 2 READA B Auto precharge starts QB1 QB2 QB3 QB4 latency = 3 READA B Auto precharge starts QB1 QB2 QB3 QB4 (tras must be satisfied) Remark READA means with Auto precharge 24 Data Sheet E0344N10 (Ver. 1.0)

25 10.2 with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of the tdpl (MIN.) after the last data word input to the device. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 latency = 2 WRITA B Auto precharge starts DB1 DB2 DB3 DB4 tdpl(min.) latency = 3 WRITA B Auto precharge starts DB1 DB2 DB3 DB4 tdpl(min.) (tras must be satisfied) Remark WRITA means with Auto Precharge In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference plus means after the reference. latency 2 1 +tdpl (MIN.) 3 2 +tdpl (MIN.) Data Sheet E0344N10 (Ver. 1.0) 25

26 11. / Interval 11.1 to Interval During a read cycle, when new command is issued, it will be effective after latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each command can be issued in every clock without any restriction. Burst length = 4, latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 READ A READ B QA1 QB1 QB2 QB3 QB4 1cycle 11.2 to Interval During a write cycle, when a new command is issued, the previous burst will terminate and the new burst will begin with a new command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1 cycle. Each command can be issued in every clock without any restriction. Burst length = 4, latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 WRITE A WRITE B DA1 DB1 DB2 DB3 DB4 1cycle 26 Data Sheet E0344N10 (Ver. 1.0)

27 11.3 to Interval command and command interval is also 1 cycle. Only the write data before command will be written. The data bus must be at least one cycle prior to the first DOUT. T0 Burst length = 4 T1 T2 T3 T4 T5 T6 T7 T8 latency = 2 WRITE A READ B DA1 QB1 QB2 QB3 QB4 latency = 3 WRITE A READ B DA1 QB1 QB2 QB3 QB4 Data Sheet E0344N10 (Ver. 1.0) 27

28 11.4 to Interval During a read cycle, READ can be interrupted by WRITE. The and command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data bus must be using M before WRITE. T0 Burst length = 4 T1 T2 T3 T4 T5 T6 T7 T8 READ WRITE M D1 D2 D3 D4 1cycle READ can be interrupted by WRITE. M must be High at least 3 clocks prior to the command. T0 T1 T2 T3 T4 T5 T6 T7 T8 Burst length = 8 T9 latency = 2 M READ WRITE Q1 Q2 Q3 is necessary D1 D2 D3 latency = 3 M READ WRITE Q1 Q2 is necessary D1 D2 D3 28 Data Sheet E0344N10 (Ver. 1.0)

29 12. Burst Termination There are two methods to terminate a burst operation other than using a or a command. One is the burst stop command and the other is the precharge command Burst Stop During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to after the latency from the burst stop command. T0 T1 T2 T3 T4 T5 T6 T7 Burst length = X READ BST latency = 2 latency = 3 Q1 Q2 Q3 Q1 Q2 Q3 Remark BST: Burst stop command During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to at the same clock with the burst stop command. T0 Burst length = X T1 T2 T3 T4 T5 T6 T7 WRITE BST latency = 2, 3 D1 D2 D3 D4 Remark BST: Burst stop command Data Sheet E0344N10 (Ver. 1.0) 29

30 12.2 Precharge Termination Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after trp from the precharge command. To issue a precharge command, tras must be satisfied. When latency is 2, the read data will remain valid until one clock after the precharge command. T0 Burst length = X, latency = 2 T1 T2 T3 T4 T5 T6 T7 READ PRE ACT Q1 Q2 Q3 Q4 trp (tras must be satisfied) When latency is 3, the read data will remain valid until two clocks after the precharge command. T0 T1 T2 T3 T4 T5 T6 T7 Burst length = X, latency = 3 T8 READ PRE ACT Q1 Q2 Q3 Q4 trp (tras must be satisfied) 30 Data Sheet E0344N10 (Ver. 1.0)

31 Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after trp from the precharge command. To issue a precharge command, tras must be satisfied. When latency is 2, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, M must be high at the same clock as the precharge command. This will mask the invalid data. T0 Burst length = X, latency = 2 T1 T2 T3 T4 T5 T6 T7 WRITE PRE ACT M D1 D2 D3 D4 D5 trp (tras must be satisfied) When latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, M must be high at the same clock as the precharge command. This will mask the invalid data. T0 T1 T2 T3 T4 T5 T6 T7 Burst length = X, latency = 3 T8 WRITE PRE ACT M D1 D2 D3 D4 D5 trp (tras must be satisfied) Data Sheet E0344N10 (Ver. 1.0) 31

32 13. Electrical Specifications All voltages are referenced to VSS (GND). After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on power supply pin relative to GND VCC, VCCQ 0.5 to +4.6 V Voltage on any pin relative to GND VT 0.5 to +4.6 V Short circuit output current IO 50 ma Power dissipation PD 1 W Operating ambient temperature TA 0 to 70 C Storage temperature Tstg 55 to C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit Supply voltage VCC, VCCQ V High level input voltage VIH 2.0 VCC+0.3 Note1 V Low level input voltage VIL 0.3 Note V Operating ambient temperature TA 0 70 C Notes 1. VIH (MAX.) = VCC V (Pulse width 5 ns) 2. VIL (MIN.) = 1.5 V (Pulse width 5 ns) Pin Capacitance (TA = 25 C, f = 1 MHz) Parameter Symbol Condition MIN. TYP. MAX. Unit Input capacitance CI pf CI2 A0 - A11, (A13), (A12),, ,,,, UM, LM Data input / output capacitance CI/O pf 32 Data Sheet E0344N10 (Ver. 1.0)

33 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition Grade Maximum Unit Notes latency 16 Operating current ICC1 Burst length = 1, CL = 2 -A75A 120 ma 1 trc trc (MIN.), Io = 0 ma, -A One bank active -A CL = 3 -A75A 120 -A A Precharge standby current ICC2P VIL (MAX.), tck = 15 ns 1 ma in power down mode ICC2PS VIL (MAX.), tck = 1 Precharge standby current in non power down mode ICC2N VIH (MIN.), tck = 15 ns, VIH (MIN.), 20 ma Input signals are changed one time during 30 ns. ICC2NS VIH (MIN.), tck =, 8 Input signals are stable. Active standby current ICC3P VIL (MAX.), tck = 15 ns 5 ma in power down mode ICC3PS VIL (MAX.), tck = 4 Active standby current in non power down mode ICC3N VIH (MIN.), tck = 15 ns, VIH (MIN.), 30 ma Input signals are changed one time during 30 ns. ICC3NS VIH (MIN.), tck =, 20 Input signals are stable. Operating current ICC4 tck tck (MIN.), Io = 0 ma, CL = 2 -A75A 185 ma 2 (Burst mode) All banks active -A A CL = 3 -A75A 185 -A A CBR (auto) refresh current ICC5 trc trc (MIN.) CL = 2 -A75A 270 ma 3 -A A CL = 3 -A75A 270 -A A Self refresh current ICC6 0.2 V -** 2 ma -**L 0.8 ma Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured condition that addresses are changed only one time during tck (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured condition that addresses are changed only one time during tck (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tck (MIN.). Data Sheet E0344N10 (Ver. 1.0) 33

34 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Note Input leakage current II (L) 0 VI VCCQ, VCCQ = VCC All other pins not under test = 0 V µa Output leakage current IO (L) 0 VO VCCQ, DOUT is disabled µa High level output voltage VOH IO = 4 ma 2.4 V Low level output voltage VOL IO = +4 ma 0.4 V AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter Value Unit AC high level input voltage / low level input voltage 2.4 / 0.4 V Input timing measurement reference level 1.4 V Transition time (Input rise and fall time) 1 ns Output timing measurement reference level 1.4 V tck 2.4 V 1.4 V 0.4 V tch tcl tsetup thold Input 2.4 V 1.4 V 0.4 V tac toh Output 34 Data Sheet E0344N10 (Ver. 1.0)

35 Synchronous Characteristics Parameter Symbol -A 75A -A 75 -A 80 -A 10 Unit Note MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Clock cycle time latency = 3 tck3 7.5 (133 MHz) 7.5 (133 MHz) 8 (125 MHz) 10 (100 MHz) ns latency = 2 tck2 7.5 (133 MHz) 10 (100 MHz) 10 (100 MHz) 13 (77 MHz) ns Access time from latency = 3 tac ns 1 latency = 2 tac ns 1 high level width tch ns low level width tcl ns Data-out hold time toh ns 1 Data-out low-impedance time tlz ns Data-out high-impedance time latency = 3 thz ns latency = 2 thz ns Data-in setup time tds ns Data-in hold time tdh ns Address setup time tas ns Address hold time tah ns setup time tcks ns hold time tckh ns setup time (Power down exit) tcksp ns (,,,, M) setup time (,,,, M) hold time tcms ns tcmh ns Note 1. Output load Ω Data Sheet E0344N10 (Ver. 1.0) 35

36 Asynchronous Characteristics Parameter Symbol -A 75A -A 75 -A 80 -A 10 Unit Note MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. ACT to REF/ACT command period (operation) trc ns REF to REF/ACT command period (refresh) trc ns ACT to PRE command period tras , , , ,000 ns PRE to ACT command period trp ns Delay time ACT to READ/WRITE command trcd ns ACT (one) to ACT (another) command period trrd ns Data-in to PRE command period tdpl ns Data-in to ACT (REF) latency = 3 tdal ns 1 command period (Auto precharge) latency = 2 tdal ns Mode register set cycle time trsc Transition time tt ns Refresh time (4,096 refresh cycles) tref ms Note 1. The A75A and A75 grade device can satisfy the tdal3 spec of 1+20 ns for up to and including 125MHz operation. 36 Data Sheet E0344N10 (Ver. 1.0)

37 13.1 AC Parameters for Timing (Manual Precharge, Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tck tch tcl tckh tcms tcmh tcks tas tah L LM L UM tac tac tac tac thz trcd tlz toh toh toh toh trp tras trc Precharge Data Sheet E0344N10 (Ver. 1.0) 37

38 AC Parameters for Timing (Auto Precharge, Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tck tch tcl tckh Auto Precharge Start for Bank C tcms tcmh tcks tas tah L LM UM L tac thz tac tac tac trcd toh toh toh toh tlz tras trrd trc for Bank C with Auto Precharge for Bank C for Bank C 38 Data Sheet E0344N10 (Ver. 1.0)

39 13.2 AC Parameters for Timing (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 tckh Auto Precharge Start for Bank C tcks tcms tcmh tas tah L LM UM L tds tdh trcd tdal trc tdpl trp trrd trcd µpd tras trc for Bank B Precharge for Bank B for Bank C for Bank B for Bank B with Auto Precharge for Bank C for Bank C Data Sheet E0344N10 (Ver. 1.0) 39

40 13.3 Relationship between Frequency and Latency Speed version - 75A Clock cycle time [ns] Frequency [MHz] latency [trcd] latency ( latency + [trcd]) [trc] [trc1] [tras] [trrd] [trp] [tdpl] [tdal] [trsc] Data Sheet E0344N10 (Ver. 1.0)

41 13.4 Mode Register Set (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H trsc 2 (MIN.) RESS KEY LM UM Precharge All Banks Mode Register Set is valid trp Data Sheet E0344N10 (Ver. 1.0) 41

42 µpd Power On Sequence and CBR (Auto) Refresh Clock cycle is necessary 2 refresh cycles are necessary trsc High level is necessary RESS KEY LM UM High level is necessary CBR (Auto) Refresh is necessary CBR (Auto) Refresh is necessary Mode Register Set is necessary Precharge All Banks is necessary trc1 trc1 trp 42 Data Sheet E0344N10 (Ver. 1.0)

43 13.6 Function (Burst Length = 4, Latency = 3) Only signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H L L RAa RAa CAa CAb LM L UM L QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb3 DAb4 Precharge Data Sheet E0344N10 (Ver. 1.0) 43

44 13.7 Clock Suspension during Burst (using Function) (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CAa RAa RAa L LM UM L QAa1 QAa2 QAa3 QAa4 µpd (turn off) at the end of burst 3-CLOCK SUSPENDED 2-CLOCK SUSPENDED 1-CLOCK SUSPENDED 44 Data Sheet E0344N10 (Ver. 1.0)

45 Clock Suspension during Burst (using Function) (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 RAa CAa RAa L LM UM L QAa1 QAa2 QAa3 QAa4 µpd (turn off) at the end of burst 3-CLOCK SUSPENDED 2-CLOCK SUSPENDED 1-CLOCK SUSPENDED Data Sheet E0344N10 (Ver. 1.0) 45

46 13.8 Clock Suspension during Burst (using Function) (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CAa RAa RAa L LM UM L DAa1 DAa2 DAa3 DAa4 µpd CLOCK SUSPENDED 2-CLOCK SUSPENDED 1-CLOCK SUSPENDED 46 Data Sheet E0344N10 (Ver. 1.0)

47 Clock Suspension during Burst (using Function) (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 RAa CAa RAa L LM UM L DAa1 DAa2 DAa3 DAa4 µpd CLOCK SUSPENDED 2-CLOCK SUSPENDED 1-CLOCK SUSPENDED Data Sheet E0344N10 (Ver. 1.0) 47

48 13.9 Power Down Mode and Clock Mask (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 tcksp tcksp VALID L RAa CAa RAa LM UM L QAa1 QAa2 QAa3 QAa4 Precharge Power Down Mode Exit Power Down Mode Entry Clock Mask End Clock Mask Start Power Down Mode Exit Power Down Mode Entry PRECHARGE STANDBY ACTIVE STANDBY 48 Data Sheet E0344N10 (Ver. 1.0)

49 13.10 CBR (Auto) Refresh T0 T1 T2 T3 T4 T5 T6 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 H L LM UM L Q1 µpd CBR (Auto) Refresh CBR (Auto) Refresh Precharge (if necessary) trc1 trc1 trp Data Sheet E0344N10 (Ver. 1.0) 49

50 13.11 Self Refresh (Entry and Exit) T0 T1 T2 T3 T4 Tn Tn + 1 Tn + 2 Tm Tm + 1 Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4 L LM UM L µpd Self Refresh Exit Self Refresh Entry (or ) Self Refresh Exit Self Refresh Entry Precharge (if necessary) Next Clock Enable Next Clock Enable trc1 trc1 trp 50 Data Sheet E0344N10 (Ver. 1.0)

51 13.12 Random Column (Page with Same Bank) (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RAd RAa RAa CAa CAb CAc RAd CAd L LM UM L QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 QAd1 QAd2 QAd3 µpd Precharge Data Sheet E0344N10 (Ver. 1.0) 51

52 Random Column (Page with Same Bank) (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RAa RAa RAa CAa CAb CAc RAa CAa L LM UM L QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 µpd Precharge 52 Data Sheet E0344N10 (Ver. 1.0)

53 13.13 Random Column (Page with Same Bank) (1/2) (Burst Length = 4, Latency = 2) L T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RDd RDa RDa CDa CDb CDc RDd CDd LM UM L DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 DDd1 DDd2 DDd3 DDd4 µpd Precharge Data Sheet E0344N10 (Ver. 1.0) 53

54 Random Column (Page with Same Bank) (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RDd RDa RDa CDa CDb CDc RDd CDd L LM UM L DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 DDd1 DDd2 Precharge 54 Data Sheet E0344N10 (Ver. 1.0)

55 13.14 Random Row (Ping-Pong Banks) (1/2) (Burst Length = 8, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RDb RBa RDa RDa CDa RBa CBa RDb CDb L LM UM L QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 for Bank B for Bank B Precharge Data Sheet E0344N10 (Ver. 1.0) 55

56 Random Row (Ping-Pong Banks) (2/2) (Burst Length = 8, Latency = 3) L T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RBb RAa RBa RBa CBa RAa CAa RBb CBb LM UM L QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 Precharge for Bank B for Bank B Precharge for Bank B for Bank B for Bank B 56 Data Sheet E0344N10 (Ver. 1.0)

57 13.15 Random Row (Ping-Pong Banks) (1/2) (Burst Length = 8, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RAb RDa RAa RAa CAa RDa CDa RAb CAb L LM UM L DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 DAb3 µpd Precharge Precharge Data Sheet E0344N10 (Ver. 1.0) 57

58 Random Row (Ping-Pong Banks) (2/2) (Burst Length = 8, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RAb RDa RAa RAa CAa RDa CDa CAb RAb L LM UM L DDa8 DAb1 DAb2 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DAa3 DAa4 DAa1 DAa2 Precharge Precharge 58 Data Sheet E0344N10 (Ver. 1.0)

59 13.16 and (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RAa RAa CAa CAb CAc Latency = 0 L LM Word Masking L UM Word Masking QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2 QAc4 (lower) QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2 QAc4 QAa1 QAa2 (Upper) µpd Clock Latency 2-Clock Latency at the end of wrap function Data Sheet E0344N10 (Ver. 1.0) 59

60 and (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H CAa RAa RAa CAb CAc Latency = 0 L LM Word Masking UM L QAc2 QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 (lower) QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2 QAa1 QAa2 (upper) µpd at the end of wrap function 0-Clock Latency 2-Clock Latency 60 Data Sheet E0344N10 (Ver. 1.0)

61 13.17 Interleaved Column Cycle (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RAa RDa CDd CDa CDb CDc CAb RAa CAa RDa L LM UM L Aa3 Aa4 Da1 Da2 Db1 Db2 Dc1 Dc2 Ab1 Ab2 Dd1 Dd2 Dd3 Dd4 Aa1 Aa2 Precharge Precharge for bank D Data Sheet E0344N10 (Ver. 1.0) 61

62 Interleaved Column Cycle (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RDa RAa RAa CAa RDa CDa CDb CDc CAb L LM UM L Aa3 Aa4 Da1 Da2 Db1 Db2 Dc1 Dc2 Ab1 Ab2 Ab3 Ab4 Aa1 Aa2 Precharge Precharge 62 Data Sheet E0344N10 (Ver. 1.0)

63 13.18 Interleaved Column Cycle (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RBa RAa CBd CBa CBb CBc CAb RAa CAa RBa L LM UM L Aa3 Aa4 Ba1 Ba2 Bb1 Bb2 Bc1 Bc2 Ab1 Ab2 Bd1 Bd2 Bd3 Bd4 Aa1 Aa2 µpd Precharge for Bank B for Bank B for Bank B for Bank B for Bank B Precharge for Bank B Data Sheet E0344N10 (Ver. 1.0) 63

64 Interleaved Column Cycle (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RBa RAa CBd RAa CAa RBa CBa CBb CBc CAb L LM UM L Aa3 Aa4 Ba1 Ba2 Bb1 Bb2 Bc1 Bc2 Ab1 Ab2 Bd1 Bd2 Bd3 Bd4 Aa1 Aa2 µpd for Bank B for Bank B for Bank B for Bank B Precharge for Bank B Precharge for Bank B 64 Data Sheet E0344N10 (Ver. 1.0)

65 13.19 Auto Precharge after Burst (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 L H RAc RDb RDa RAa CAa RDa CDa CAb RDb CDb RAc CAc RAa LM UM L µpd with Auto Precharge with Auto Precharge Auto Precharge Start with Auto Precharge Auto Precharge Start with Auto Precharge Auto Precharge Start Data Sheet E0344N10 (Ver. 1.0) 65

66 Auto Precharge after Burst (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 H RDb RDa RAa RAa CAa RDa CDa CAb RDb CDb LM L UM L µpd with Auto Precharge with Auto Precharge with Auto Precharge Auto Precharge Start Auto Precharge Start 66 Data Sheet E0344N10 (Ver. 1.0)

67 RDb Auto Precharge after Burst (1/2) (Burst Length = 4, Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 L H RAc RDa RAa CAa RDa CDa CAb RDb CDb RAc CAc RAa LM UM L µpd with Auto Precharge with Auto Precharge with Auto Precharge with Auto Precharge Auto Precharge Start Auto Precharge Start Auto Precharge Start Data Sheet E0344N10 (Ver. 1.0) 67

68 Auto Precharge after Burst (2/2) (Burst Length = 4, Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 L H RAa RDb RDa RAa CAa RDa CDa CAb RDb CDb LM UM L µpd for bank D with Auto Precharge with Auto Precharge with Auto Precharge Auto Precharge Start Auto Precharge Start 68 Data Sheet E0344N10 (Ver. 1.0)

69 13.21 Full Page Cycle (1/2) ( Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 H RDb RAa RDa RAa CAa RDa CDa RDb L LM UM L Aa Aa+1 Aa+2 Aa+m-2 Aa+m-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6 µpd Precharge Burst Stop Note: m is Full page burst length. Data Sheet E0344N10 (Ver. 1.0) 69

70 70 Full Page Cycle (2/2) ( latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Data Sheet E0344N10 (Ver. 1.0) H RAa RDa RAa CAa RDa CDa RDb RDb LM UM L L Aa Aa+1 Aa+m-3 Aa+m-2 Aa+m-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Note: m is Full page burst length. Burst Stop Precharge µpd

71 13.22 Full Page Cycle (1/2) ( latency = 2) T0 T1 T2 T3 T4 T5 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 Tn + 14 Tn + 15 H RDb RAa RDa RAa CAa RDa CDa RDb L LM UM L Aa Aa+1 Aa+2 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Aa+m-2 Aa+m-1 Precharge Burst Stop Note: m is Full page burst length. Data Sheet E0344N10 (Ver. 1.0) 71