M390S3320AT1 SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The

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1 Revision History Revision 0.0 (Sep. 1999) PC133 first published

2 M390S3320AT1 SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M390S3320AT1 is a 32M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M390S3320AT1 consists of eighteen CMOS 32Mx4 bit Synchronous DRAMs in TSOPII 400mil packages, three 18bits Drive ICs for input control signal, one PLL in 24pin TSSOP package for clock and one 2K EEPROM in 8pin TSSOP package for Serial Presence Detect on a 168pin glassepoxy substrate. One 0.22uF and two uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M390S3320AT1 is a Dual Inline Memory Module and is intented for mounting into 168pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE Performance range Part No. M390S3320AT1C75 Max Freq. (Speed) 133MHz CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,700mil), double sided component PIN CONFIGURATIONS (Front side/back side) Front DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ CB0 CB1 WE Front 1 0 DU A0 A2 A4 A6 A8 A10/AP BA1 0 DU DU CB2 CB3 DQ16 DQ Front DQ18 DQ19 DQ20 *VREF *1 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 *2 WP **SDA **SCL Back DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CB4 CB5 CAS Back 5 *1 RAS A1 A3 A5 A7 A9 BA0 A11 *1 *A12 0 *3 6 7 *A13 CB6 CB7 DQ48 DQ49 PIN NAMES Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 Function Address input (Multiplexed) Select bank Data input/output Check bit (Datain/dataout) * These pins are not used in this module. ** These pins should be in the system which does not support SPD. SAMSUNG ELECTRONI CO., Ltd. reserves the right to change products and specifications without notice Back DQ50 DQ51 DQ52 *VREF REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 *3 **SA0 **SA1 **SA , 2 RAS CAS WE 0 ~ 7 *VREF REGE SDA SCL SA0 ~ 2 DU WP Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Don t use No connection Write protection

3 PIN CONFIGURATION DESCRIPTION Name Input Function System clock Active on the positive going edge to sample all inputs. A0 ~ A11 BA0 ~ BA1 RAS CAS WE 0 ~ 7 REGE Chip select Clock enable Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Register enable Disables or enables device operation by masking or enabling all inputs except, and Masks system clock to freeze operation from the next clock cycle. should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. should be enabled 1+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output HiZ, tshz after the clock and masks the output. Blocks data input when active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if is held at a high or low logic level. the inputs are stored in the latch/flipflop on the rising edge of. REGE is tied to through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. WP Write Protection WP pin is connected to through 47KΩ Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be writeprotected. / Power supply/ground Power and ground for the input buffers and the core logic.

4 FUTIONAL BLOCK DIAGRAM P0 B0 B00 B0A0~B0A10,BBA0,BBA1,BRAS,BCAS,BWE B0 A3,~A10,BA0 P6 REGE A11,BA ,3,6,7 A0,A1,A2 RAS,CAS,WE,0 0,1,4,5 DQ4~7 P1 B1 DQ8~11 DQ12~ CB0~3 DQ16~19 P4 B2 DQ20~23 DQ24~27 P5 B3 DQ28~31 10kΩ P2 P3 B2 74ALVCF LE 74ALVC LE 74ALVC LE OE OE OE D0 D1 D2 D3 D4 D5 D6 D7 D8 B0A3~B0A10,B0BA0 B0A11.B0BA1 B2 B00 B10 B2,3,6,7 B0A0,B0A1,B0A2 DQ32~35 DQ36~39 B5 DQ40~43 DQ44~47 CB4~7 DQ48~51 BRAS, BCAS, BWE,B0 B0,1,4,5 B6 DQ52~55 DQ56~59 B10 B4 B7 DQ60~63 1,2, SCL WP 47KΩ 2G AGND 1G AVCL FIBIN CDCF2510 Cb *1 A0 SA0 D9 D10 D11 D12 D13 D14 D D16 D17 IY0 IY1 IY2 IY3 IY4 2Y0 2Y1 FBOUT Serial PD A1 A2 SA1 SA2 P0 P1 P2 P3 P4 P5 P6 Note 1. The actual values of Cb will depend upon the PLL chosen. SDA

5 STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4) *2 *1 REG *1. Register Input Control Signal(RAS,CAS,WE) *3 DOUT RAS CAS WE *2. Register Output RAS CAS td tr td tr WE *3. SDRAM trac(refer to *1) CAS latency(refer to *1) =2+1 tsac 1 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 trac(refer to *2) CAS latency(refer to *2) =2 trdl Row Active Read Command Precharge Command Row Active Write Command Precharge Command td, tr = Delay of register (74ALVCF162835) Notes : 1. In case of module timing, command cycles delayed 1 with respect to external input timing at the address and input signal because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be issued 1 earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module. : Don t care

6 ABSOLUTE MAIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT 1.0 ~ 4.6 V Voltage on supply relative to Vss, Q 1.0 ~ 4.6 V Storage temperature TSTG 55 ~ +0 C Power dissipation PD 18 W Short circuit current IOS 50 ma Note : Permanent device damage may occur if "ABSOLUTE MAIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTI Recommended operating conditions (Voltage referenced to = 0V, TA = 0 to 70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage V Input high voltage VIH Q+0.3 V 1 Input low voltage VIL V 2 Output high voltage VOH 2.4 V IOH = 2mA Output low voltage VOL 0.4 V IOL = 2mA Input leakage current ILI ua 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = 2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN Q. Input leakage currents include HiZ output leakage for all bidirectional buffers with TriState outputs. CAPACITAE ( = 3.3V, TA = 23 C, f = 1MHz, VREF =1.4V ± 200 mv) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A11) Input capacitance (RAS, CAS, WE) Input capacitance (0) Input capacitance (0) Input capacitance (0, 2) Input capacitance (0 ~ 7) Input capacitance (BA0 ~ BA1) Data input/output capacitance (DQ0 ~ DQ63) Data input/output capacitance (CB0 ~ CB7) CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT

7 DC CHARACTERISTI (Recommended operating condition unless otherwise noted, TA = 0 to 70 C) Parameter Symbol Test Condition Version 75 Unit Note Operating current (One bank active) ICC1 Burst length = 1 trc trc(min) IO = 0 ma 2,660 ma 1,3 Precharge standby current in powerdown mode ICC2P VIL(max), tcc = 10ns 368 ICC2PS & VIL(max), tcc = 20 ma 3 Precharge standby current in non powerdown mode ICC2N ICC2NS VIH(min), VIH(min), tcc = 10ns Input signals are changed one time during 20ns VIH(min), VIL(max), tcc = Input signals are stable ma 3 Active standby current in powerdown mode ICC3P VIL(max), tcc = 10ns 440 ICC3PS & VIL(max), tcc = 92 ma 3 Active Standby current in non powerdown mode ICC3N ICC3NS VIH(min), VIH(min), tcc = 10ns Input signals are changed one time during 20ns VIH(min), VIL(max), tcc = Input signals are stable 990 ma ma 3 Operating current (Burst mode) ICC4 IOL = 0mA Page burst 4 Banks activated tccd=2 3,020 ma 1,3 Refresh current ICC5 trc trc(min) 4,460 ma 2,3 Self refresh current ICC6 0.2V 377 ma 3 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 3 Drive ICs. 4. Unless otherwise noticed, Input swing level is CMOS(VIH/VIL=Q/Q)

8 AC OPERATING TEST CONDITIONS ( = 3.3V ± 0.3V, TA = 0 to 70 C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig V Vtt = 1.4V 1200Ω 50Ω Output VOH (DC) = 2.4V, IOH = 2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50Ω 870Ω (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) (Fig. 2) AC output load circuit Parameter Symbol Version Row active to row active delay trrd(min) ns 1 RAS to CAS delay trcd(min) 20 ns 1 Row precharge time trp(min) 20 ns 1 Row active time Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time 75 Unit tras(min) 45 ns 1 tras(max) 100 us Row cycle time trc(min) 65 ns 1 Last data in to row precharge trdl(min) 2 2 Last data in to Active delay tdal(min) ns Last data in to new col. address delay tcdl(min) 1 2 Last data in to burst stop tbdl(min) 1 2 Col. address to col. address delay tccd(min) 1 3 Number of valid output data and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. CAS latency= All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Note ea 4

9 AC CHARACTERISTI (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter Symbol cycle time CAS latency=3 tcc ns 1 to valid output delay Output data hold time Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/20.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/21]ns should be added to the parameter. Min CAS latency=3 tsac 5.4 ns 1,2 CAS latency=3 toh 2.7 ns 1,2 high pulse width tch 2.5 ns 3 low pulse width tcl 2.5 ns 3 Input setup time tss 1.5 ns 3 Input hold time tsh 0.8 ns 3 to output in LowZ tslz 1 ns 2 to output in HiZ CAS latency=3 tshz 5.4 ns 1 75 Max Unit Note

10 SIMPLIFIED TRUTH TABLE Command n1 n RAS CAS WE BA0,1 A10/AP Notes : 1. OP Code : Operand code (V=Valid, =Don t care, H=Logic high, L=Logic low) A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 6. Burst stop command is valid at every burst length. 7. sampled at positive going edge of a and masks the datain at the very (Write latency is 0), but makes HiZ state the dataout of 2 cycles after. (Read latency is 2) A11, A9 ~ A0 Register Mode register set H L L L L OP code 1,2 Refresh Auto refresh Self refresh H 3 H L L L H Entry L 3 Exit L H Note L H H H 3 H 3 Bank active & row addr. H L L H H V Row address Read & column address Write & column address Auto precharge disable L Column 4 H L H L H V address Auto precharge enable H (A0 ~ A9, A11) 4,5 Auto precharge disable L Column 4 H L H L L V address Auto precharge enable H (A0 ~ A9, A11) 4,5 Burst stop H L H H L 6 Precharge Clock suspend or active power down Precharge power down mode Bank selection H L L H L V L All banks H Entry H L H L V V V Exit L H Entry H L Exit L H H L H H H H L V V V H V 7 No operation command H H L H H H

11 PACKAGE DIMENSIONS Units : Inches (Millimeters) (3.000) ( ) ( ) (1.372) R (R 2.000) (43.18) (3.000) REG REG PLL 0.7 ± (4.000 ± 0.100) (17.780).118DIA ± (3.000DIA ± 0.100) (8.890) A.450 (11.430) (6.350) (36.830) B (1.57) (6.350) C 2.0 (54.61) Min (2.540 Min) 0.0 Max (3.81 Max) REG Min (4.19 Min) ± (1.270 ± 0.10) (6.350) (6.350) Min (2.540 Min) ± (1.000 ± 0.050) ± (3.125 ± 0.125) ± (3.125 ± 0.125) ± (0.200 ± 0.0) Detail A ± (2.000 ± 0.100) Detail B ± (2.000 ± 0.100) Detail C (1.270) Tolerances : ± 0.005(.13) unless otherwise specified The used device is 32Mx4 SDRAM, TSOP SDRAM Part No. : K4S280432ATC75 This module is based on JEDEC PC133 Specification