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- Peregrine Charles
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19 T0 T1 T T T T T CLK ADDRESS Row Addr. Col. Addr Row Addr. Row Addr. t RCD t RRD COMMAND Write A NOP NOP with Auto Precharge NOP : H or L t RC
20 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Minimum delay between the Read and Write s = 4+1 = 5 cycles DQM t DQZ t DQW COMMAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP I/O s : H or L DOUT A 0 DIN B0 DIN B1 DIN B2 Must be Hi-Z before the Write
21 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK t DQW DQM t DQZ 1 Clk Interval COMMAND NOP NOP BANK A ACTIVATE NOP READ A WRITE A NOP NOP NOP CAS latency = 2 t CK2, I/O s Must be Hi-Z before the Write DIN A 0 DIN A 1 DIN A 2 DIN A 3 : H or L T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM t DQW t DQZ COMMAND NOP READ A NOP NOP READ A NOP WRITE B NOP NOP CAS latency = 2 t CK1, I/O s CAS latency = 3 t CK2, I/O s DOUT A0 DOUT A1 DOUT A0 Must be Hi-Z before the Write DIN B0 DIN B1 DIN B2 DIN B 0 DIN B 1 DIN B 2 : H or L
22 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP I/O s DIN A 0 DIN A 1 DIN A 2 DIN A 3 don t care The first data element and the Write are registered on the same clock edge. Extra data is ignored after termination of a Burst.
23 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP CAS latency = 2 t CK2, I/O s DIN A0 don t care DOUT B 0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 3 t CK3, I/O s DIN A0 don t care don t care DOUT B0 DOUT B 1 DOUT B 2 DOUT B 3 Input data must be removed from the I/O s at least one clock cycle before the Read dataappears on the outputs to avoid data contention. T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 C L K B A N K A W R IT E A C O M M A NAD C T IV E N O P N O P N O P N O P N O P N O P A u to -P re c h a rg e N O P I/O s D IN A 0 D IN A 1 t * B e g in A u to p re c h a rg e * t
24 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 t CK2, I/O s CAS latency = 3 t CK3, I/O s * DOUT A0 DOUT A1 DOUT A2 * t RP DOUT A3 t RP DOUT A0 DOUT A1 DOUT A2 DOUT A3 * Begin Autoprecharge Bank can be reactivated after t RP
25 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP CAS latency = 2,3 I/O s DIN A0 DIN A1 DIN A2 don t care Input data for the Write is masked.
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29 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O Hi-Z High level is required trp Precharge All Banks 1st Auto Refresh Minimum of 2 Refresh Cycles are required 2nd Auto Refresh trc 2 Clock min. Address Key Mode Register Set Any
30 Hi-Z RAx RAx t t
31 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O Hi-Z All Banks must be idle Self Refresh Entry t CKS t SREX trc Begin Self Refresh Exit Self Refresh Exit issued Self Refresh Exit
32 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O Hi-Z tck2 Precharge All Banks trp trc trc Auto Refresh Auto Refresh RAx RAx CAx Read Ax0 Ax1 Ax2 Ax3
33 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O Hi-Z t CK2 RAw RAw CAw Read RAz CAx CAy RAz CAz Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Read Read Precharge Read
34 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O Hi-Z tck3 RAw RAw CAw Read CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Read Precharge RAz RAz CAz Read
35 CLK t CK2 CKE CS RAS CAS WE BS AP RBz RAw RBz Addr RBz CBz CBx CBy RAw RBz CAx CBz DQM I/O Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Write Write Write Precharge Write
36 CLK t CK3 CKE CS RAS CAS WE BS AP RBz RBz Addr RBz CBz CBx CBy RBz CBz DQM I/O Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 Write Write Write Precharge Write
37 CLK tck2 CKE High CS RAS CAS WE BS AP RBx RAx RBy Addr RBx CBx RAx CAx RBy CBy DQM t RCD t AC2 t RP Hi-Z I/O Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Read Read Precharge Read
38 CLK t CK3 CKE High CS RAS CAS WE BS AP RBx RAx RBy Addr RBx CBx RAx CAx RBy CBy DQM trcd tac3 trp Hi-Z I/O Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Read Read Precharge Read Precharge By0
39 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z t CK2 RBx RAy CAy CAX RBx CBx RAy CAy t RCD t DPL t RP tdpl DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Write Precharge Write Precharge DAy4
40 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z tck3 trcd RBx RAy CAX RBx CBx RAy CAy tdpl trp tdpl DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 Write Write Precharge Write Precharge DAy3
41 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z tck2 RAy CAx RAy CAy trp DAx0 DAx1 DAx2 DAx3 Write Precharge Termination of a Write Burst. Write data is masked. Precharge Read trp Ay0 Ay1 Ay2 Precharge RAz RAz CAz t RP Az0 Az1 Az2 Read Precharge Precharge Termination of a Read Burst.
42 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z t CK3 RAy CAx RAy CAy trp DAx0 Write Precharge Read Write Data is masked Precharge Termination of a Write Burst. t RP Ay0 Ay1 Ay2 Precharge RAz RAz Precharge Termination of a Read Burst.
43 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z tck2 CAx Read RBx RBx CBx Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Read The burst counter wraps from the highest order page address back to zero during this time interval. Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Burst Stop Precharge t RP RBy RBy
44 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z t CK3 CAx Read RBx RBx CBx t RRD Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Read The burst counter wraps from the highest order page address back to zero during this time interval. Full Page burst operation does not terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Burst Stop Precharge RBy RBy
45 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z tck2 RBx CAx RBx CBx DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 Write The burst counter wraps from the highest order page address back to zero Write Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Data is ignored. during this time interval. bursting beginning with the starting address. Burst Stop Precharge RBy RBy
46 CLK CKE CS RAS CAS WE BS AP Addr DQM I/O High RAx RAx Hi-Z t CK3 RBx CAx RBx CBx Data is ignored. DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 Write The burst counter wraps from the highest order page address back to zero during this time interval. Write Full Page burst operation does not terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Burst Stop Precharge RBy RBy
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128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM)
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Features High Performance: f Clock Frequency -7K 3 CL=2-75B, CL=3-8B, CL=2 Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Units 133
IS42S32800B. Integrated Silicon Solution, Inc Rev. E 1/22/07
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Features Clock frequency: 166, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Four banks operation Single 3.3V power supply LVTTL interface Programmable burst length -- (1,
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Feature. 512Mb DDR SDRAM. REV 1.1 Jul CAS Latency Frequency NT5DS64M8DS NT5DS32M16DS CONSUMER DRAM. 2KB page size for all configurations.
Feature CAS Latency Frequency DDR-333 DDR400 DDR500 Speed Sorts Units -6K/-6KI -5T/-5TI -4T CL-tRCD-tRP 2.5-3-3 3-3-3 3-4-4 tck CL=2 266 266-2KB page size for all configurations. DQS is edge-aligned with
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Mobile SDRAM 2M x 16 Bit x 4 Banks Mobile Synchronous DRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2
- - DQ0 NC DQ1 DQ0 DQ2 - NC DQ1 DQ3 NC - NC
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128Mb DDR SDRAM. Features. Description. REV 1.1 Oct, 2006
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IS42S8800/IS42S8800L IS42S16400/IS42S16400L 2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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V58C2512804/164SH HIGH PERFORMAE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 804 4 BANKS X 8Mbit X 16 164 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time t CK2 7.5ns 7.5ns 7.5ns Clock Cycle Time t CK2.5 6ns 6ns
8. OPERATION Read Operation Write Operation Precharge... 18
128Mb Mobile LPSDR Table of Contents- 1. GENERAL DESCRIPTION... 4 2. FEATURES... 4 3. ORDER INFORMATION... 4 4. BALL CONFIGURATION... 5 4.1 Ball Assignment: LPSDR x16... 5 4.2 Ball Assignment: LPSDR x32...
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1. Features. Description
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Data Sheet Jan. 2003, V1.1 Features CAS Latency and Frequency Maximum Operating Frequency (MHz) CAS Latency DDR200-8 DDR266A -7 DDR266-7F DDR333-6 2 100 133 133 133 2.5 125 143 143 166 Double data rate
PT483208FHG PT481616FHG
Table of Content- 8M x 4Banks x 8bits SDRAM 4M x 4Banks x 16bits SDRAM 1. GENERAL DESCRIPTION...3 2. FEATURES...3 3. PART NUMBER INFORMATION...3 4. PIN CONFIGURATION...4 5. PIN DESCRIPTION...5 6. BLOCK
IS42S Meg x MBIT SYNCHRONOUS DRAM SEPTEMBER 2009
16Meg x16 256-MBIT SYNCHRONOUS DRAM SEPTEMBER 2009 FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge
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256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256M (16Mx16bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description
Advantage Memory Corporation reserves the right to change products and specifications without notice
SDRAM SODIMM 4MX64 SDRAM SO DIMM based on 4MX16, 4Banks, 4K Refresh, 3.3V DRAMs with SPD GENERAL DESCRIPTION The Advantage is a 4MX64 Synchronous Dynamic RAM high density memory module. The Advantage consists
256M (16Mx16bit) Hynix SDRAM Memory
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This document is a general product description and is subject
- DQ0 - NC DQ1 - NC - NC DQ0 - NC DQ2 DQ1 DQ CONFIGURATION. None SPEED GRADE
SYNCHRONOUS DRAM 52Mb: x4, x8, x6 MT48LC28M4A2 32 MEG x 4 x 4 S MT48LC64M8A2 6 MEG x 8 x 4 S MT48LC32M6A2 8 MEG x 6 x 4 S For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds
IS42S32160B IS45S32160B
IS42S32160B IS45S32160B 16M x 32 512Mb SYNCHRONOUS DRAM DECEMBER 2009 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding
IS42S16800A. 8Meg x MBIT SYNCHRONOUS DRAM JUNE 2007
8Meg x16 128-MBIT SYNCHRONOUS DRAM JUNE 2007 FEATURES Clock frequency: 143, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power
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512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16i/o Specification of 512Mb (32Mx16bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 8,388,608 x16 This document is a general product description
SDRAM Device Operations
DEVICE OPERATIONS SDRAM Device Operations * Samsung Electronics reserves the right to change products or specification without notice. EECTRONICS DEVICE OPERATIONS A. MODE REGISTER FIED TABE TO PROGRAM
ESMT M52S128168A. Revision History. Elite Semiconductor Memory Technology Inc. Publication Date: Oct Revision: 1.1 1/47
Revision History Revision 1.0 (May. 29, 2007) -Original Revision 1.1 (Oct. 08, 2007) -Add Speed -7 spec. -Modify Icc spec Revision: 1.1 1/47 Mobile SDRAM FEATURES ORDERING INFORMATION 2M x 16 Bit x 4 Banks
Advantage Memory Corporation reserves the right to change products and specifications without notice
SD872-8X8-72VS4 SDRAM DIMM 8MX72 SDRAM DIMM with ECC based on 8MX8, 4B, 4K Refresh, 3.3V DRAMs with SPD GENERAL DESCRIPTION The Advantage SD872-8X8-72VS4 is a 8MX72 Synchronous Dynamic RAM high-density
HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L)
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Data Sheet, Rev. 1.21, Jul. 2004 HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) 256 Mbit Double Data Rate SDRAM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g. Edition 2004-07
SYNCHRONOUS DRAM. 256Mb: x4, x8, x16 SDRAM 3.3V
SYNCHRONOUS DRAM 256Mb: x4, x8, x16 Features: Intel PC133 (3-3-3) compatible Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can
IS42S16400J IS45S16400J
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JULY 2014 FEATURES Clock frequency: 200, 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank
M52D A (2F) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
Mobile SDRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (3) - Burst Length (1, 2, 4, 8 & full page) - Burst
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128MBit MOBILE SDR SDRAMs based on 1M x 4Bank x32 I/O Specification of 128M (4Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 1,048,576 x32 This document is a general product description
SDR SDRAM. MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks. Features. 128Mb: x4, x8, x16 SDRAM
SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all
Revision History Revision 1.0 (August, 2003) - First release. Revision 1.1 (February, 2004) -Corrected typo.
stacked 1Gb B-die SDRAM Specification Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice. Revision History Revision 1.0 (August, 2003)
IS42S81600D IS42S16800D
IS42S81600D IS42S16800D 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM JULY 2008 FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank
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1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JANUARY 2008 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for
Advantage Memory Corporation reserves the right to change products and specifications without notice
SDRAM DIMM 32MX72 SDRAM DIMM with PLL & Register based on 32MX4, 4 Internal Banks, 4K Refresh, 3.3V DRAMs with SPD GENERAL DESCRIPTION The Advantage is a 32MX72 Synchronous Dynamic RAM high density memory
EM828164PAY-xxUx. Document Title. Revision History. 1 Rev M: 8M x 16 Mobile SDRAM. 128M: 8M x 16 Mobile SDRAM. Revision No.
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IS42S32400B. 4Meg x MBIT SYNCHRONOUS DRAM
4Meg x 32 128-MBIT SYNCHRONOUS DRAM PRELIMINARY INFORMATION MARCH 2009 FEATURES Clock frequency: 166, 143, 125, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank
DQ0 NC DQ1 DQ0 DQ2 DQ3 DQ Speed Grade
Features SDRAM MT48LC32M4A2 8 Meg x 4 x 4 banks MT48LC16M8A2 4 Meg x 8 x 4 banks MT48LC8M16A2 2 Meg x 16 x 4 banks For the latest data sheet, refer to Micron s Web site: www.micron.com Features PC100 and
256Mbit SDRAM. 8M x 8bit x 4 Banks Synchronous DRAM LVTTL. Revision 0.1 Sept. 2001
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MOS INTEGRATED CIRCUIT
DATA SHEET 128M-bit Synchronous DRAM 4-bank, LVTTL MOS INTEGRATED CIRCUIT µpd45128163 Description The µpd45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152
Mobile SDRAM AVM121632S- 32M X 16 bit AVM123216S- 16M X 32 bit
Mobile SDRAM AVM2632S- 32M X 6 bit AVM2326S- 6M X 32 bit Features V DD /V D =.7.95V Fully synchronous; all signals registered on positive edge of system clock Internal, pipelined operation; column address
IS42S86400B IS42S16320B, IS45S16320B
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M464S1724CT1 SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD. Pin. Pin. Back. Front DQ53 DQ54 DQ55
M464S1724CT1 SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M464S1724CT1 is a 16M bit x 64 Synchronous Dynamic RAM high
512 Mbit DDR SDRAM. This preliminary data sheet contains product specifications which are subject to change without notice.
V 512 Mbit DDR SDRAM M X 8 M X 4 M X 16 16 Features High speed data transfer rates with system frequency up to 200MHz Data Mask for Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency:
- DQ0 - NC DQ1 - NC - NC DQ0 - NC DQ2 DQ1 DQ
SYHRONOUS DRAM Features PC66, PC100, and PC133compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock
V58C SJ HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 4Mbit X 16. Description
HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 4Mbit X 16 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time t CK2 5ns 7.5ns 7.5ns Clock Cycle Time t CK2.5 5ns 6ns 6ns Clock Cycle Time t CK3 4ns 5ns 6ns System
512K x 32 Bit x 4 Banks Synchronous DRAM
SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full
Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A E
SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks Features Features PC100- and PC133-compliant Fully synchronous; all signals registered on positive
OKI Semiconductor MD56V82160
4-Bank 4,194,304-Word 16-Bit SYNCHRONOUS DYNAMIC RAM FEDD56V82160-01 Issue Date:Feb.14, 2008 DESCRIPTION The is a 4-Bank 4,194,304-word 16-bit Synchronous dynamic RAM. The device operates at 3.3 V. The
Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A
SDR SDRAM MT48LC4M32B2 1 Meg x 32 x 4 s 128Mb: x32 SDRAM Features Features PC100-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column
SDRAM Unbuffered SODIMM. 144pin Unbuffered SODIMM based on 256Mb H-die. 54 TSOP-II/sTSOP II with Pb-Free. (RoHS compliant)
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Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A E
SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all
DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD
PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 DQ8 DQ9 0 1 2 3 4 5 CB0 CB1 WE 0
Revision History. REV. 0.1 June Revision 0.0 (May, 1999) PC133 first published.
Revision History Revision 0.0 (May, 1999) PC133 first published. Revision 0.1 (June, 1999) - Changed PCB Dimensions in PACKAGE DIMENSIONS This datasheet has been downloaded from http://www.digchip.com
t WR = 2 CLK A2 Notes:
SDR SDRAM MT48LC16M4A2 4 Meg x 4 x 4 Banks MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks 64Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all
Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) A
SDR SDRAM MT48LC4M32B2 1 Meg x 32 x 4 s 128Mb: x32 SDRAM Features Features PC100-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column
W948D6KBHX. 256Mb Mobile LPDDR. Table of Contents- Publication Release Date: May 25, 2017 Revision: A
256Mb Mobile LPDDR Table of Contents-. GENERAL DESCRIPTION... 4 2. FEATURES... 4 3. ORDER INFORMATION... 4 4. BALL CONFIGURATION... 5 5. BALL DESCRIPTION... 6 5. Signal Descriptions... 6 5.2 ing Table...
256K x 32 / 512K x 32 / 1M x 32 Synchronous Graphic RAM
256K x 32 / 512K x 32 / 1M x 32 Synchronous Graphic RAM ADDRESS TRANSLATION TABLE DEVICE OPERATIONS TIMING DIAGRAM PACKAGE DIAGRAM Samsung Electronics reserves the right to change products or specification