Si trim applications: benefits and challenges

Transcription

1 Si trim applications: benefits and challenges SPCC, April 2, 2019 S. Kal 1, Y. Oniki 2, C. Alix 1, E. Liu 1, K. Pillai 1, D. Chanemougame 1, F. Holsteyns 2, A. Mosden 1, K. Kumar 1, P. Biolsi 1, T Hurd 1. 1 TEL Technology Center, America, LLC, USA 2 Imec, Belgium Subhadeep.Kal@us.tel.com

2 DIMENSIONAL SCALING CHALLENGES DEVICE ARCHITECTURE & MATERIAL INNOVATION log 2 (#transistors/$) Standard cell track height reduction (7,5T-3T): FinFET depopulation 20nm Double Patterning (Cost!) 14-10nm FinFET saves the day Multi-patterning cost escalates 5nm 3nm 2nm 14A 28nm Planar HKMG 28nm 20nm 14nm 10nm 7nm 7nm EUV reduces cost and complexity 22nm pitch 22nm pitch 120nm STI 170nm STI Scaled FinFET GAA CFET Scaling boosters - Materials and integration choices - Device and reliability impact VFET This presentation Year of 1 st introduction LOGIC SCALING 2

3 Trim technique 1 multi cycle Trim technique 1 Single cycle Trim technique 1 Multi cycle incoming Vapor Si trim techniques: benchmarking (gas phase etches) CDU Center Edge CD/CDU Center Edge ~52% CD = 11.4 nm CDU = 2.9 %CD LWR = 8.7 %CD LER = 11.6 %CD CD = 15nm CDU = 5.67 %CD LWR = 6.87 %CD LER = 8.67 %CD Bulk Si mandrel CD trim asi MND Inc = 19.1 ~32% CD = 11.8 nm CDU = 1.8 %CD LWR = 8.7 %CD LER = 11.0 %CD CD/CDU Center Edge ~66% CD = 12.3nm CDU = 4.88 %CD LWR = 12.2 %CD LER = 13.6 %CD Technique Details 1 Single chamber; gas X + B etch 2 Single chamber; gas Y etch 3 Two chamber gas; A + B etch S. Kal / TEL / April 2-3, 2019/ SPCC

4 Trim technique 2 Multi cycle Trim technique 2 Single cycle (T1) Trim technique 2 Single cycle (T2, T2>>T1) Vapor Si trim techniques: benchmarking (gas phase etches) incoming CD/CDU Center Edge CD/CDU Center Edge ~34% CD = 11 nm CDU = 3.0 %CD LWR = 10.8 %CD LER = 13.5 %CD CD = 15nm CDU = 5.67 %CD LWR = 6.87 %CD LER = 8.67 %CD Bulk Si mandrel CD trim ~78% CD = 12.6 nm CDU = 3.9 %CD LWR = 9.2 %CD LER = 10.5 %CD Technique Details 1 Single chamber; gas X + B etch 2 Single chamber; gas Y etch ~11% CD = 11.9 nm CDU = 5.12 %CD LWR = 11.7 %CD LER = 12.4 %CD 3 Two chamber gas; A + B etch S. Kal / TEL / April 2-3, 2019/ SPCC

5 Trim technique 3 T1 Trim technique 3 T2 (T2>>T1) Vapor Si trim techniques: benchmarking (gas phase etches) incoming CD/CDU Center Edge CD/CDU Center Edge CD = 15nm CDU = 5.67 %CD LWR = 6.87 %CD LER = 8.67 %CD ~26% CD = 13 nm CDU = 1.47 %CD LWR = 7.56 %CD LER = 9.57 %CD Bulk Si mandrel CD trim Technique Details ~44% CD = 12.3 nm CDU = 2.52 %CD LWR = 7.8 %CD LER = 10.5 %CD 1 Single chamber; gas X + B etch 2 Single chamber; gas Y etch 3 Two chamber gas; A + B etch S. Kal / TEL / April 2-3, 2019/ SPCC

6 Vapor Si trim techniques: benchmarking (gas phase etches) CDU (normalized as %CD) CD trim Bulk Si or asi CDU Improvement Wets Trim Technique Technique Details 1 Single chamber; gas X + B etch 2 Single chamber; gas Y etch 3 Two chamber gas; A + B etch Technique 1 & 3 has the best Si trim CDU improvement Technique 2 however has better post trim surface roughness Wet etch also trim feasibility; maintaining incoming CDU S. Kal / TEL / April 2-3, 2019/ SPCC

7 Vapor Si etch : Roughness Analysis Trim Technique NA (incoming) 1 3 details Control Si etch (process A) Si etch (process B) Technique 1 AFM Img. Rq RMS) nm nm nm nm Img. Ra (Avg) nm nm nm nm Summary: Certas post Si etch roughness on bare-si shows slight increases in roughness (AFM/SEM) Roughness can be minimized by recipe tuning Major knobs for improving roughness: Temperature Pressure Gas ratio S. Kal / TEL / April 2-3, 2019/ SPCC 2019

8 FinFET Extension: Need for fin trim NONSELECTIVE SI/SIGE FIN CD Fin CD for better electrostatic control w/o sacrificing R ext Target FW: ~4-5nm (etch 0.5-1nm/side) Controlled etch Si/SiGe fins at the same time with a similar etch rate Selectivity to: STI, ILD0, dummy OX, spacer, CESL,... Fin (EPI) STI Spacer CESL ILD0 Fin (EPI) STI ~4-5nm Spacer CESL ILD0 Y. Oniki et al. (imec) SPCC 2018 S. Kal / TEL / April 2-3, 2019/ SPCC

9 Post Trim Incoming FinFET Extension: Si and SiGe Fin Trim (simultaneous) Si Silicon fins SiGe fins Avg = 9.1nm Avg = 7.5nm Si SiGe SiGe Technique 1 Avg CD@55nm = 6.07nm Etch = 1.5nm/side Si Si Avg CD@55nm = 5nm Etch = 1.25nm/side SiGe SiGe SiGe Technique 1 can trim Si and SiGe fins simultaneously Ability to tune trim rates for preferential trimming S. Kal / TEL / April 2-3, 2019/ SPCC

10 FinFET Extension: Si Fin Trim Feasibility Technique 1 Incoming Low gas ratio Baseline BKM Temp effect (T2) Temp effect (T3) Target Fin width (nm) 5 10/ 10/ / 5.8/ / 6.2/ / 5.4/ / 5.6/ 9.1 Fin height (nm) (low temp BT) EA/ DELTA* (nm) 5/<1 0/ 1 5.8/4.2/3.9/ 2 3.8/3.8/2.4/ /4.6/3.8/ /4.4/1.9/ 4 *Delta: measure the widest narrowest fin CD ~ fin width non-uniformity/roughness Summary: Isotropic Si fin trim looks promising Gas ratio tuning in ME step improves fin width variation and fin fin trim uniformity (~ roughness) Post trim FW variation (roughness) is higher than incoming BT step does not introduce field oxide iso-dense loading: fin height maintained Incoming fins have slightly wider CD at bottom and oxide footing Technique 1 has ability to improve post trim roughness Trim is very selective to STI oxide (also SiN) Baseline Temp > T2 > T3 S. Kal / TEL / April 2-3, 2019/ SPCC

11 IL/HK/MG VFET: Gate Length Definition VERTICAL SI NANOWIRE CHANNEL CD TRIM SiGe Si channel trim for self-aligned Lg definition W Si Lg Need for a controlled Si etch with selectivity to SiGe S/D SiGe SiGe Si channel trim HKMG S. Kal / TEL / April 2-3, 2019/ SPCC

12 VFET: Si Channel Trim Feasibility Technique 1 Incoming POST CERTAS No process T1 T2 T3 Summary for Si channel trim: Selective Si trim (wrt SiGe) looks promising Ability control the trim amount By tuning etch time Etch gas ratio Post Certas etch roughness for the Si channel needs improvement Si width (avg) 20.9nm 21.8nm 18.5nm 9.6nm Technique 1 shows good Si channel trim selectivity w.r.t SiGe for VFET Facilitate VFET Si gate length definition (self aligned) S. Kal / TEL / April 2-3, 2019/ SPCC

13 CFET: Mushroom Gate DUMMY POLY CD TRIM PRIOR TO SPACER FORMATION Conventional spacer etch needs thicker gate HM >FinH poly collapse for taller fin devices Mushroom gate to enable HM thickness scaling Lg (& spacer width) defined by poly trim amount need for a controlled a-si selective etch >FinH HM HM <FinH Trimmed dummy poly HM HM Spacer Poly (a-si) Poly (a-si) Spacer Poly (a-si) Poly (a-si) FinH (Fin) (Fin) FinH (Fin) (Fin) STI STI STI STI S. Kal / TEL / April 2-3, 2019/ SPCC

14 4nm/side CFET: Mushroom Gate (Feasibility) Incoming (ict-inc) T1 T2 T3 10nm/EA Target 18/0 16.4/0.8 13/2.5 8/5 100nm/EA 20/0 17.5/ / / nm/EA 32/0 24.8/ / /8.4 Summary: Technique 1 Isotropic Si fin trim looks promising Roughness looks same as incoming Further improvement needed for: Uniformity tuning Incoming gates have slightly wider CD at bottom 4nm trim/side gate bending (may be due to TEM decoration?) Technique 1 shows feasibility for CFET gate trim S. Kal / TEL / April 2-3, 2019/ SPCC

15 Conclusion Technique Details Improvement 1 Single chamber; gas X + B etch 2 Single chamber; gas Y etch CDU 3 Two chamber gas; A + B etch Wet Single chamber Throughput Established 3 dry Si trim techniques for patterning purposes All dry techniques improve CDU post trim Demonstrated Si trim feasibility with wet etch Dry plasma free etches are advantageous & crucial for FiFET/VFET/CFET integrations applications, due to: High etch selectivity, inherent from the etch mechanism No plasma damage Aspect ratio dependency S. Kal / TEL / April 2-3, 2019/ SPCC

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