The Low Warpage Coreless Substrate for High Speed Large Size Die Packages. Device Packaging Technology Dept. Fujitsu Advanced Technology Ltd.

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1 62 nd ECTC San Diego, CA: May 29 June 1, 2012 The Low Warpage Coreless Substrate for High Speed Large Size Die Packages Device Packaging Technology Dept. Fujitsu Advanced Technology Ltd. -1-

2 AGENDA 1. Introduction 2. Targets of Development 3. Warpage Control Method Development 1. Coreless Substrate 2. Package Assembly 3. Board Mounting 4. Conclusion -2-

1. Introduction Fujitsu s Technologies -102 processors are installed in a rack -32

3 1. Introduction Fujitsu s Technologies -102 processors are installed in a rack = 864 racks are installed Installed Area: 36m 38.4m -88,128 CPUs (705,024cores) -3-

4 1. Introduction Rank Site Computer/Year Vendor Cores Super Computer Ranking RIKEN Advanced Institute for Computational Science(AICS) Japan National Supercomputing Center In Tianjin China DOE/SC/Oak Ridge National Laboratory United States National Supercomputing Centre in Shenzhen (NSCS) China GSIC Center, Tokyo Institute of Technology Japan DOE/NNSA/LANL/SNL United States NASA/Ames Research Center/NAS United States DOE/SC/LBNL/NERSC United States Commissariat a l'energie Atomique (CEA) France DOE/NNSA/LANL United States K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnect / 2011 Fujitsu Efficiency ratio93.2% / 88,128CPU Tianhe-1A - NUDT TH MPP, X Ghz 6C, NVIDIA GPU, FT C / 2010 NUDT Jaguar - Cray XT5-HE Opteron 6-core 2.6 GHz / 2009 Cray Inc. Nebulae - Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU / 2010 Dawning TSUBAME HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows / 2010 NEC/HP Cielo- Cray XE6 8-core 2.4GHz / 2011 Cray Inc. Pleiades - SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/ Ghz, Infiniband / 2011 SGI Hopper - Cray XE6 12-core 2.1 GHz / 2010 Cray Inc. Tera Bull bullx super-node S6010/S6030 / 2010 Bull SA Roadrunner - BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband / 2009 IBM R max [Pflops] Power [MW] 705, , , , , , , , , , Source : 37 th TOP500LIST ( -4-

5 1. Introduction Fujitsu Server Development trend High Performance Technology High Reliability technology Store Ahead Branch History Prefetch Hardware Barrier Multi-core / Multi-thread L2$ on Die Non-Blocking $ O-O-O Execution Super-Scalar Single-chip CPU ~1995 SPARC64 II SPARC64 GS ~1997 GS ~1999 SPARC64 GP GS8900 SPARC64 TM Processor SPARC64 V GS ~2003 SPARC64 V+ GS Main Frame 2004 ~2006 SPARC64 VI SPARC64 VII GS21 Technology Generation 2007~ SPARC64 VⅢfx HPC UNIX -5-

1. Introduction CPU Package Outline PKG Size 55.5 55.

6 1. Introduction CPU Package Outline PKG Size mm Cu-LID Size mm BGA 2408pin Heat resistance 0.06 /w -6-

7 1. Introduction Why High Via Density Substrate? Equivalent circuit LSI Bump Via Power Consumption Higher Power Voltage Lower Decrease Power noise in High frequency Range Use Low Inductance Capacitor Mounting under LSI is efficient Core via Need low Power-GND roop inductance via Solder High efficient Low inductance capacitor Thinner Substrate Finer Core Via pitch or Core-Less Full Stacked Thin-Film layer via -7-

8 2. Targets of Development Coreless Issue Coreless Conventional Cost Miniaturization Inductance Assembly Why is not Coreless popular? Warpage Control Issue The factors of Warpage 1) CTE mismatch and Low Young s modulus of package substrate material 2) Package assembly technique 3) Board mount reflow temperature -8-

9 2. Targets of Development Development Target Warpage control technique 1. Coreless Substrate Structure Material composition and Structure control 2. Package Assembly Warpage Correction control 3. Board mounting Reflow Temperature control -9-

10 2. Targets of Development Development Target Warpage control technique 1. Coreless Substrate Material composition and Structure control 2. Package Assembly Warpage Correction control 3. Board mounting Reflow Temperature control -10-

11 3. Experimental Methods Warpage Improvement Method Using an insulating material with a small CTE mismatch We use prepregs General Material Combination Resin = 35ppm/ C Cu = 17ppm/ C Prepreg = 15ppm/ C Our Material Combination Cu = 17ppm/ C CTE mismatch decreased to 1/9 by prepreg application. Coreless substrate with all prepreg layers exhibits smaller warpage -11-

12 3. Experimental Methods Problem of Prepreg in Transmission Properties Prepreg Resin 15ppm/ C 35ppm/ C CTE mismatch with Cu Small Large Warpage Exellent Poor Transmission Property Poor Exellent Coreless substrate with all prepreg layers is inferior to transmission property. Necessary to reduce the prepreg consumption as much as possible, and to control a warpage. -12-

13 3. Experimental Methods Low warpage and High Trans. Quality 1. Arrangement of prepregs in external layers. To control the warpage by moment power Prepreg Prepreg Moment power > Central Axis Prepreg Prepreg 2. Arrangement of resins in internal layers. Skew less transmission property We propose the coreless structure with external prepregs and internal resins. -13-

14 3. Experimental Methods Layer Structures of Prepared Corelss 1. All-PP 2. Outer-PP 3. Inner-PP 4. None-PP PP PP PP PP Cross-sectional view confirms the PP arrangement difference Layer V2 V3 V4 V5 V6 V7 All-PP Layer Structure Outer-PP Inner-PP None-PP PP layer Small CTE mismatch Resin layer Large CTE mismatch -14-

15 4. Results Warpage Measurement Results All-PP Outer-PP Inner-PP None-PP We succeeded in reducing the warpage with Outer-PP structure. Minimum Warpage Warpage (mm)

16 2. Targets of Development Development Target Warpage control technique 1. Coreless Substrate Material composition and Structure control 2. Package Assembly Warpage Correction control 3. Board mounting Reflow Temperature control -16-

17 LSI Area 実装エリア反り Warpage [μm/ 20mm] [um/20sq.mm] 3.2 Package Assembly Package Substrate Warpage Average Too Large! Same as conventional 20 0 Conventional Thincore Coreless Fig.1 Comparison of LSI area warpage in Each substrate type -17-

Cure Cure 3.2 Package Assembly Stiffener Assembly Process <Controlling parameters on Stiffener assembly> Curing temperature Pressure Thermal curing Adhesive Curing reaction Temp.

18 Cure Cure 3.2 Package Assembly Stiffener Assembly Process <Controlling parameters on Stiffener assembly> Curing temperature Pressure Thermal curing Adhesive Curing reaction Temp. : 100<->130C Stiffner(Cu) CTE : 17ppm/K Coreless CTE : 25ppm/K CTE Gap Stiffner < Coreless Tensile force dominate during below curing temperature Tensile force Large pressure prevent expansion. Deformation Need for process optimization -18-

3.2 Package Assembly Process Optimization LSI Area warpage[um/20mm] 140 120 Average 100 80 60 Improving!

19 3.2 Package Assembly Process Optimization LSI Area warpage[um/20mm] Average Improving! Thincore Coreless Coreless Optimized Fig.4 Substrate type and warpage Optimization of the warpage controlling -19-

3.2 Package Assembly Reliability Test Result Test conditions Thermal Cycle

of the initial resistance Sample 1000cycle Effective factors for reliability

20 3.2 Package Assembly Reliability Test Result Test conditions Thermal Cycle -25/+125(cel) 1,000cycles LSI Size 20mm square, 0.15mm thick Substrate Size 42.5mm square, 0.3mm thick 20 test pieces were prepared Pass conditions Test results Less than twice of the initial resistance Sample 1000cycle Effective factors for reliability Reliability Test 1. The warpage value at maximum All-PP Passed temperature Outer-PP Passed 2. The temperature dependent Inner-PP Failed warpage in cooling process. None-PP Failed -20-

21 Reliability Test Result -21-

22 2. Targets of Development Development Target Warpage control technique 1. Coreless Substrate Material composition and Structure control 2. Package Assembly Warpage Correction control 3. Board mounting Reflow Temperature control -22-

23 Warpage Warpage(micron) 3.2 Board Mounting Adopting Low-Temperature Soldering Warpage reduction 1/ SnBi 200 SnAgCu Temperuture(cel) Reflow Temperature -23-

24 Melting temperature (ºC) 3.2 Board Mounting Candidates of Low-Temperature Solder 300 Sn-80Au Sn-3.5Ag Sn-0.7Cu Sn-3Ag-0.5Cu Sn-9Zn 150 Sn-58Bi Low melting temperature Sn-57Bi-1Ag In-3Ag Sn-52In 100 Eutectic Composition(mass%) Melting point ( ) Price In-3Ag Good Expensive Sn-58Bi(-1Ag) Good Reasonable In-48Sn Good Expensive In-34Bi 72.7 Too Low Expensive -24-

Shortening Temporal Change Stability Concern under High Temperature Operation Coarsening of

25 3.2 Board Mounting Issues of Sn-Bi eutectic Solder Mechanical Characteristic Bi : Hard / Brittle Less Ductility High Strain Rate Deformation Brittleness Destruction Shock Resistant Lifetime Shortening Temporal Change Stability Concern under High Temperature Operation Coarsening of metallographic structure Growth of reaction layer in the bonded interface Improvement by Third element addition -25-

improvement by Sb Conventional Sn-Bi Solder Test Temp. : Room Temp.

26 Breaking elongation (%) 3.2 Board Mounting Charactristic Sn-Bi-Sb-Zn Texture Miniaturization and Ductility improvement by Sb Conventional Sn-Bi Solder Test Temp. : Room Temp. Strain Speed: /sec Developed Solder Developed Solder (Sb Added) Conventional (Ag Added) rd element content(wt%) 10μm -26-

reinforcement by Zn Conventional SnBi Solder Bi 30 25 125 /1000h Developed Solder Cu 6 Sn 5 20 (Sn-57Bi-0.

27 Bump Pull Strength(N) 3.2 Board Mounting Charactristic Sn-Bi-Sb-Zn Inhibition of Bi-rich layer constitution, interfacial reinforcement by Zn Conventional SnBi Solder Bi /1000h Developed Solder Cu 6 Sn 5 20 (Sn-57Bi-0.5Sb-0.5Zn) Cu Pad Developed Solder 15 (Sn-57Bi-1.0Ag) 10 (Sn-58Bi) Conventional Cu 5 Zn 8 Cu Pad 5 0 スタートチャックプル Start Chucking Pull Time(h) Joint Reliability was Successfully improved -27-

28 Conclusion The most effective structure to reduce warpage in our study was the application of prepreg materials only in both external layers. For Coreless Substrate structure, Stiffener assembly materials and appropriate processes enabled the same assembling level as conventional organic substrates. New Composition of Sn-Bi-Pb-Zn Solder enabling Low temperature reflow that realize low-reflow warpage. -28-

29 Daisuke Mizutani (Material Analysis) Mamoru Kurashina (Material Analysis) Seiki Sakuyama(Material Development) Kenji Fukuzono (Package Structure Analysis) Manabu Watanabe(Board Level Reliability) -29-

30 -30-

Coreless Packaging Technology for High-performance Application

62 nd ECTC San Diego, CA: May 29 June 1, 2012 Coreless Packaging Technology for High-performance Application Corp Advanced LSI Assembly Product Department Analog LSI Bussiness Division Semiconductor Business