64M(4Mx16) Low Power SDRAM

Transcription

1 64M(4Mx16) ow Power SDRAM Revisio 1.4 September, 2012

2 Documet Title 64M(4Mx16) ow Power SDRAM Revisio istory Revisio No. istory Draft date Remark 0.0 Iitial Draft Ju.25 th, 2004 Prelimiary 0.1 Correct typo. Add Write Burst Mode descriptio Aug.13 th, 2004 Prelimiary 0.2 Add commercial & exteded temperature optios Add package dimesio Oct.6 th, 2004 Prelimiary 0.3 Exted Vddmax limit for 2.5V product Oct.20 th, 2004 Prelimiary 0.4 Chage IDD specificatios Dec.6 th, 2004 Prelimiary 1.0 Add Pb & aloge free package item Chage from maual TCSR to auto TCSR Chage IDD2N specificatios Ja.5 th, 2005 Prelimiary 1.1 Chage Setup/old time Ja.10 th, Chage IDD3p specificatio Feb, Add (Pb-Free & aloge Free) descriptios Nov. 1 st, 2005 Fial 1.3 Add 60ball FBGA descriptios Sep. 24 st, 2012 Fial

3 Features - Fuctioality - Stadard SDRAM Fuctioality - Programmable burst legths : 1, 2, 4, 8, or full page - JEDEC Compatibility - ow Power Features - ow voltage power supply : 2.5V/3.0V - Auto TCSR(Temperature Compesated Self Refresh) - Partial Array Self Refresh power-savig mode - Deep Power Dow Mode - Driver Stregth Cotrol - Operatig Temperature Rages: - Special (-10 to +60 ) - Commercial (0 to +70 ) - Exteded (-25 to +85 ) - Idustrial (-40 to +85 ) - VCMOS Compatible IO Iterface - 54ball FBGA with 0.8mm ball pitch - CMS6416AF : Normal - CMS6416AG : Pb-Free - CMS6416A : Pb-Free & aloge Free - CMS6416AS : 60ball, Pb-Free & aloge Free Fuctioal Descriptio The CMS6416Ax-xxxx family is high-performace CMOS Dyamic RAMs (DRAM) orgaized as 4M x 16. These devices feature advaced circuit desig to provide ultra-low active curret ad extremely low stadby curret.this is ideal for providig More Battery ife i portable applicatios such as wireless hadsets. The device is compatible with the JEDEC stadard P-SDRAM specificatios. ogic Block Diagram CKE /CS /WE /CAS /RAS Cotrol ogic Mode Reg Ehaced Mode Reg Refresh Couter Row Add Mux 0 Row 0 Row Addr Addr atch/ atch/ Decoder Decoder Memory Array 4Kx4K Sese Amp Data Output Reg M - UM A0-A11 BA0-BA1 Addr Reg Cotrol ogic Colum atch Colum Colum Colum Decoder Decoder Colum Decoder Decoder Write Drivers M Mask READ DATA ATC Data Output Reg 0-15 Selectio Guide Device Voltage Access Time(t AC ) Frequecy V DD V D C=2 C=3 t RCD t RP 133Mz 6s 18s 18s CMS6416Ax-75xx V 1.65-V DD 100Mz 7.5s 20s 20s

4 Pi Cofiguratio for ball FBGA(8mm x 8mm) 60 ball FBGA(6.4mm x 10.1mm) A V SS 15 V SSQ V D 0 V DD A VSS 15 0 VDD B V D V SSQ 2 1 B 14 VSSQ VD 1 C V SSQ V D 4 3 C 13 VD VSSQ 2 D 10 9 V D V SSQ 6 5 D E 8 NC V SS V DD M 7 E 10 VSSQ VD 5 F UM CKE /CAS /RAS /WE F 9 VD VSSQ 6 G NC A 11 A 9 BA 0 BA 1 /CS G 8 NC NC 7 A8 A 7 A 6 A 0 A 1 A 10 NC NC NC NC J V SS A 5 A 4 A 3 A 2 V DD J NC UM M /WE K NC /RAS /CAS CKE NC NC /CS M A11 A9 BA1 BA0 N A8 A7 A0 A10 P A6 A5 A2 A1 R VSS A4 A3 VDD

5 Pi Descriptio Symbol Type Descriptio CKE Iput Iput Clock : is drive by the system clock. All SDRAM iput sigals are sampled o the positive edge of. also icremets the iteral burst couter ad cotrols the output registers. Clock Eable: CKE activates(ig) ad deactivates(ow) the sigal. Deactivatig the clock provides PRECARGE POWER-DOWN ad SEF REFRES operatio(all baks idle), ACTIVE POWER-DOWN(row active i ay bak) or COCK SUSPEND operatio(burst/access i progress). CKE is sychroous except after the device eters power-dow ad self refresh modes, where CKE becomes asychroous util after exitig the same mode. The iput buffers, icludig, are disabled durig power-dow ad self refresh modes, providig low stadby power. CKE may be tied IG. /CS Iput Chip Select: CS# eables (registered OW) ad disables (registered IG) the commad decoder. All commads are masked whe /CS is registered IG. /CS provides for exteral bak selectio o systems with multiple baks. /CS is cosidered part of the commad code. /CAS, /RAS, /WE Iput Iputs : /CAS, /RAS, ad /WE (alog with /CS) defie the commad beig etered. M, UM Iput Iput/Output Mask: (U)M is sampled IG ad is a iput mask sigal for write accesses ad a output eable sigal for read accesses. Iput data is masked durig a WRITE cycle. The output buffers are placed i a igh-z state (two-clock latecy) whe durig a READ cycle. M correspods to 0 7 ad UM correspods to BA0, BA1 A0-A11 Iput Iput Iput(s): BA0 ad BA1 defie to which bak the ACTIVE, READ, WRITE or PRECARGE commad is beig applied. These pis also provide the op-code durig a OAD MODE REGISTER commad. Iputs: A0 A11 are sampled durig the ACTIVE commad (row-address A0 A11) ad READ/WRITE commad (colum-address A0 A7; with A10 defiig auto precharge) to select oe locatio out of the memory array i the respective bak. A10 is sampled durig a PRECARGE commad to determie if all baks are to be precharged (A10 IG) or bak selected by BA0, BA1 (A10 OW). The address iputs also provide the op-code durig a OAD MODE REGISTER commad. I/O Data Iput/Output : Data bus NC - No Coect V D Supply Power: Provide isolated power to s for improved oise immuity. V SSQ Supply Groud: Provide isolated groud to s for improved oise immuity. V DD Supply Power Supply: Voltage depedet o optio. V SS Supply Groud.

6 FUNCTIONA DESCRIPTION The Fidelix 64Mb SDRAM is a quad-bak DRAM that operates at 2.5V ad icludes a sychroous iterface (all sigals are registered o the positive edge of the clock sigal, ). Each of the x16 s 16,777,216-bit baks is orgaized as 4,096 rows by 256 colums by 16 bits. Read ad write accesses to the SDRAM are burst orieted; accesses start at a selected locatio ad cotiue for a programmed umber of locatios i a programmed sequece. Accesses begi with the registratio of a ACTIVE commad, which is the followed by a READ or WRITE commad. The address bits registered coicidet with the ACTIVE commad are used to select the bak ad row to be accessed (BA0 ad BA1 select the bak, A0- A11 select the row). The address bits (A0-A7) registered coicidet with the READ or WRITE commad are used to select the startig colum locatio for the burst access.the SDRAM must be iitialized prior to ormal operatio. The followig sectios provide detailed iformatio regardig device iitializatio, register defiitio, commad descriptios ad device operatio. Iitializatio SDRAMs must be powered up ad iitialized i a predefied maer. Operatioal procedures other tha those specified may result i udefied operatio. Oce power is applied to V DD ad V D (simultaeously) ad the clock is stable (meets the clock specificatios i the AC characteristics), the SDRAM requires a 100µs delay prior to issuig ay commad other tha a COMMAND INIBIT or. The COMMAND INIBIT or should be applied at least oce durig the 100µs delay. After the 100µs delay, a PRECARGE commad should be applied. All baks must the be precharged, thereby placig the device i the all baks idle state. Oce i the idle state, two AUTO REFRES cycles must be performed. After the AUTO REFRES cycles are complete, the SDRAM is ready for mode register programmig. Because the mode register will power up i a ukow state, it should be loaded prior to applyig ay operatioal commad. Refer to Figure 1.

7 Figure 1. Iitialize ad oad Mode Register [1.2.3.] CKE /CS /RAS /CAS /WE ADDR Key Key Key BA0 BA0 BA1 BA1 A10/AP RAa iz iz M igh level is ecessary t RP t RC t RC Precharge (All ) Auto Refresh Auto Refresh Normal MRS Exteded MRS Row Active a Note : 1. The two AUTO REFRES commads at T4 ad T9 may be applied before either OAD MODE REGISTER (MR) commad. 2. PRE = PRECARGE commad, MR = OAD MODE REGISTER commad, AR = AUTO REFRES commad, ACT = ACTIVE commad, RA = Row, BA = 3. The oad Mode Register for both MR/EMR ad 2 Auto Refresh commads ca be i ay order; owever, all must occur prior to a Active commad. Register Defiitio There are two mode registers which cotai settigs to achieve low power cosumptio. The two registers : Mode Register ad Exteded Mode Register are discussed below. Mode Register The mode register is used to defie the specific mode of operatio of the SDRAM. This defiitio icludes the selectio of a burst legth, a burst type, a CAS latecy, a operatig mode ad a write burst mode, as show i Table 1. The mode register is programmed via the OAD MODE REGIS- TER commad ad will retai the stored iformatio util it is programmed agai or the device loses power. Mode Register bits M0-M2 specify the burst legth, M3 specifies the type of burst (sequetial or iterleaved), M4-M6 specify the CAS latecy, M7 ad M8 specify the operatig mode, M9 specifies the write burst mode, M10, M11, M12 ad M13 should be set to zero.the mode register must be loaded whe all baks are idle, ad the cotroller must wait the specified time before iitiatig the subsequet operatio. Violatig either of these requiremets will result i uspecified operatio. Burst egth Read ad write accesses to the SDRAM are burst orieted. The burst legth is programmable, as show i Table 2. The burst legth determies the maximum umber of colum locatios that ca be accessed for a give READ or WRITE commad. Burst legths of 1,2, 4, or 8 locatios are available for both the

8 sequetial ad the iterleaved burst types, ad a full-page burst is available for the sequetial type. The full-page burst is used i cojuctio with the BURST TERMINATE commad to geerate arbitrary burst legths. Reserved states should ot be used, as ukow operatio or icompatibility with future versios may result. Whe a READ or WRITE commad is issued, a block of colums equal to the burst legth is effectively selected. All accesses for that burst take place withi this block, meaig that the burst will wrap withi the block if a boudary is reached. The block is uiquely selected by A1-A7 whe the burst legth is set to two; by A2-A7 whe the burst legth is set to four; ad by A3-A7 whe the burst legth is set to eight. The remaiig(least sigificat) address bit(s) is (are) used to select the startig locatio withi the block. Full-page bursts wrap withi the page if the boudary is reached. Burst Type The burst type ca be set to either Sequetial or Iterleaved by usig the M3 bit i the Mode register. The orderig of accesses withi a burst is determied by the burst legth, the burst type ad the startig colum address, as show i Table 2. [ ] M13- BA1 M12- BA0 M11- A11 M10- A10 M9-A9 M8-A8 M7-A7 M6-A6 M5-A5 M4-A4 M3-A3 M2-A2 M1-A1 M0-A0 Reserved(Set to 0 ) WB Op Mode CAS atecy BT Burst egth Burst egth M2 M1 M0 M3=0 M3= Reserved Reserved Reserved Reserved M3 Burst Type 0 Sequetial 1 Iterleaved M9 Write Burst Mode 0 Prog. Burst egth 1 Sigle Mode Access Reserved Reserved Full Page Reserved M6 M5 M4 CAS atecy M8 M7 M6-M0 Operatig Mode Reserved Defied Stadard Operatio All other states reserved Reserved Reserved Reserved Reserved Note : 4. For full-page accesses: y = For a burst legth of two, A1-A7 select the block-of-two burst; A0 selects the startig colum withi the block. 6. For a burst legth of four, A2-A7 select the block-of-four burst; A0-A1 select the startig colum withi the block. 7. For a burst legth of eight, A3-A7 select the block-of-eight burst; A0-A2 select the startig colum withi the block. 8. For a full-page burst, the full row is selected ad A0-A7 select the startig colum. 9. Wheever a boudary of the block is reached withi a give sequece above, the followig access wraps withi the block. 10. For a burst legth of oe, A0-A7 select the uique colum to be accessed,ad mode register bit M3 is igored. Table 1. Mode Register Defiitio.

9 Order of Accesses withi a Burst Burst egth Startig Colum Type=Sequetial Type=Iterleaved 2 A A1 A A2 A1 A Full Page(y) =A0-A8(locatio 0-y) B, B+1, B+2..B, Not supported Table 2. Burst egth Defiitio. Operatig Mode The ormal operatig mode is selected by settig M7 ad M8 to zero; the other combiatios of values for M7 ad M8 are reserved for future use ad/or test modes. The programmed burst legth applies to both READ ad WRITE bursts.test modes ad reserved states should ot be used because ukow operatio or icompatibility with future versios may result. Reserved states should ot be used as ukow operatio or icompatibility with future versios may result. Write Burst Mode Whe M9=0, the burst legth programmed via M0-M2 applies to both READ ad WRITE bursts; whe M9=1, the programmed burst legth applies to READ bursts, but write accesses are sigle-locatio (o-burst) accesses. CAS atecy The CAS latecy is the delay, i clock cycles, betwee the registratio of a READ commad ad the availability of the first piece of output data. The latecy ca be set to oe, two, or three clocks. If a READ commad is registered at clock edge r, ad the latecy is q clocks, the data will be available by clock edge r+q. The s will start drivig as a result of the clock edge oe cycle earlier (r + q- 1), ad provided that the relevat access times are met, the data will be valid by clock edge r+q.for example, assumig that the clock cycle time is such that all relevat access times are met, if a READ commad is registered at T0 ad the latecy is programmed to two clocks, the s will start drivig after T1 ad the data will be valid by T2, as show i Figure 2.

10 Read t Z t O t AC CAS atecy=1 T3 Read t Z t O t AC CAS atecy=2 T3 T4 Read t Z t O t AC CAS atecy=3 Figure 2. CAS atecy

11 ETENDED MODE REGISTER The Exteded Mode Register cotrols additioal fuctios such as the Temperature Compesated Self Refresh (TCSR) Cotrol, Partial Array Self Refresh (PASR), ad Output Drive Stregth.The Exteded Mode Register is programmed via the Mode Register Set commad (BA1=1, BA0=0) ad retais the stored iformatio util it is programmed agai or the device loses power. The Exteded Mode Register must be programmed with M8 through M11 set to 0. The Exteded Mode Register must be loaded whe all baks are idle ad o bursts are i progress, ad the cotroller must wait the specified time iitiatig ay subsequet operatio. Violatig either of these requiremets results i uspecified operatio. PARTIA ARRAY SEF REFRES The Partial Array Self Refresh (PASR) feature allows the cotroller to select the amout of memory that will be refreshed durig SEF REFRES. The refresh optios are all baks (baks 0, 1, 2, ad 3); two baks(baks 0 ad 1 or 2 ad 3 by M7); ad oe bak (bak 0 or 2 by M7). WRITE ad READ commads occur to ay bak selected durig stadard operatio, but oly the selected baks i PASR will be refreshed durig SEF REFRES. The data i baks 2 ad 3 will be lost whe the two bak optio with M7=0 is used. Similarly the data will be lost i baks 1, 2, ad 3 whe the oe bak optio with M7=0 is used dow. AUTO TEMPERATURE COMPENSATED SEF REFRES Every cell i the DRAM requires refreshig due to the capacitor losig its charge over time. The refresh rate is depedet o temperature. At higher temperatures a capacitor loses charge quicker tha at lower temperatures, requirig the cells to be refreshed more ofte. I order to save power cosumptio, accordig to the temperature, Mobile-SDRAM icludes the iteral temperature sesor ad cotrol uits to cotrol the self refresh cycle automatically. Driver Stregth Cotrol The driver stregth feature allows oe to reduce the drive stregth of the I/O s o the device durig low frequecy operatio. This allows systems to reduce the oise associated with the I/O s switchig. Table 4. Exteded Mode Register Defiitio EM13- BA1 EM12- BA0 EM11- A11 EM10- A10 EM9- A9 EM8- A8 EM7- A7 EM6- A6 EM5- A5 EM4- A4 EM3- A3 EM2- A2 EM1- A1 EM0- A0 1 0 All must be set to 0 Up/Dow Driver Stregth 0 0 PASR

12 Table 5. Exteded Mode Register Table [11.12.]. A7 A2 A1 A0 Self Refresh Coverage A6 A5 Driver Stregth Four s Two s (0 & 1) Oe ( 0) RFU 1 RFU Four s Two s (2 & 3) Oe (2) RFU 1 RFU Note : 11. EM13 ad EM12 (BA1 ad BA0) must be 1, 0 to select the Exteded Mode Register(vs. the base Mode Register). 12. RFU: Reserved for Future Use % % % % Table 6. s [ ]. Name(Fuctio) CKE /CS /RAS /CAS /WE M ADDR COMMAND INIBIT() NO OPERATION() ACTIVE(Select bak ad activate row) [15.] / Row READ(Select bak ad colum, ad start READ burst) [16.] / / Col WRITE(Select bak ad colum, ad start WRITE burst) [16.] / / Col Valid BURST TERMINATE Active PRECARGE(Deactivate row i bak or baks) [17.] Code AUTO REFRES or SEF REFRES(Eter Self Refresh Mode) )[ ] OAD MODE REGISTER) [14.] Opcode Write Eable/Output Eable) [20.] Active Write Ihibit/Output igh-z) [20.] igh Z Deep Power Dow(Eter DPD Mode)

13 Table 6. s [ ]. Note : 13. CKE is IG for all commads show except SEF REFRES. 14. A0-A10 defie the op-code writte to the mode register. 15. A0-A11 provide row address, ad BA0, BA1 determie which bak is made active. 16. A0-A7 provide colum address; A10 IG eables the auto precharge feature (opersistet), while A10 OW disables the auto precharge feature; BA0, BA1 determie which bak is beig read from or writte to. 17. A10 OW: BA0, BA1 determie the bak beig precharged. A10 IG: All baks precharged ad BA0, BA1 are Do t Care. 18. This commad is AUTO REFRES if CKE is IG, SEF REFRES if CKE is OW. 19. Iteral refresh couter cotrols row addressig; all iputs ad I/Os are Do t Care except for CKE. 20. Activates or deactivates the s durig WRITEs (zero-clock delay) ad READs (two-clock delay). M cotrols 0-7 ad UM cotrols s Table 6. provides a referece of all the commads available with the state of the cotrol sigals for executig a specific commad. COMMAND INIBIT The COMMAND INIBIT fuctio effectively deselects the SDRAM by prevetig ew commads from beig executed by the SDRAM, regardless of whether the sigal is eabled. Operatios already i progress are ot affected. OAD MODE REGISTER The mode register is loaded via iputs A0-A11, BA0, BA1. The OAD MODE REGISTER ad OAD ETENDED MODE REGISTER commads ca oly be issued whe all baks are idle, ad a subsequet executable commad caot be issued util t MRD is met. Table 1. ad Table 4. provide the defiitio for the Mode Register ad Exteded Mode Register. NO OPERATION () The NO OPERATION () commad is used to perform a to a SDRAM which is selected (/CS is OW). This prevets uwated commads from beig registered durig idle or wait states. Operatios already i progress are ot affected. ACTIVE The ACTIVE commad is used to activate a row i a particular bak for a subsequet access. The value o the BA0, BA1 iputs selects the bak, ad the address provided o iputs A0-A11 selects the row. This row remais active for accesses util a PRECARGE commad is issued to that bak. A PRECARGE commad must be issued before opeig a differet row i the same bak. READ READ commad is used to iitiate a burst read access to a active row. The value o the BA0, BA1 iputs selects the bak, ad the address provided o iputs A0-A7 selects the startig colum locatio. The value o iput A10 determies whether or ot auto precharge is used. If auto precharge is selected, the row beig accessed will be precharged at the ed of the READ burst. If auto precharge is ot selected, the row will remai ope for subsequet accesses. Read data appears o the s subject to the logic level o the M iputs two clocks earlier. If a give M sigal was registered IG, the correspodig s will be igh-z two clocks later; if the M sigal was registered OW, the s will provide valid data. WRITE The WRITE commad is used to iitiate a burst write access to a active row. The value o the BA0, BA1 iputs selects the bak, ad the address provided o iputs A0-A7 selects the startig colum locatio. The value o iput A10 determies whether or ot auto precharge is used. If auto precharge is selected, the row beig accessed will be precharged at the ed of the WRITE burst. If auto precharge is ot selected, the row will remai ope for subsequet accesses. Iput data appearig othesiswrittetothememoryarraysubjecttothem iput logic level appearig coicidet with the data. If a give M sigal is registered OW, the correspodig data will be writte to memory; if the M sigal is registered IG, the correspodig data iputs will be igored, ad a WRITE will ot be executed to that byte/colum locatio. PRECARGE The PRECARGE commad is used to deactivate the active row i a particular bak or the active row i all baks. The bak(s) will be available for a subsequet row access a specified time (t RP ) after the PRECARGE commad is issued. Iput A10 determies whether oe or all baks are to be precharged, ad i the case where oly oe bak is to be precharged, iputs BA0, BA1 select the bak. Otherwise BA0, BA1 are treated as Do t Care. Oce a bak has bee precharged, it is i the idle state ad must be activated prior to ay READ or WRITE commads beig issued to that bak. AUTO PRECARGE AUTO PRECARGE is accomplished by usig A10 to eable auto precharge i cojuctio with a specific READ or WRITE commad. AUTO PRECARGE thus performs the same PRECARGE commad described above, without requirig a explicit commad. A PRECARGE of the bak/row that is addressed with the READ or WRITE commad is automatically performed upo completio of the READ or WRITE burst. AUTO PRECARGE does ot apply i the full page mode burst. Auto precharge is opersistet i that it is either eabled or disabled for each idividual READ or WRITE commad. Auto precharge esures that the precharge is iitiated at the earliest valid stage withi a burst. The user must ot issue aother commad to the same bak util the precharge time (t RP ) is completed. BURST TERMINATE The BURST TERMINATE commad is used to trucate either fixed-legth or full-page bursts. The most recetly registered READ or WRITE commad prior to the BURST TERMINATE commad will be trucated.

14 AUTO REFRES AUTO REFRES is used durig ormal operatio of the SDRAM. This commad is opersistet, so it must be issued each time a refresh is required. All active baks must be PRECARGED prior to issuig a AUTO REFRES commad. The AUTO REFRES commad should ot be issued util the miimum t RP has bee met after the PRECARGE commad. The addressig is geerated by the iteral refresh cotroller. The address bits thus are a Do t Care durig a AUTO REFRES commad. The Fidelix 64Mb SDRAM requires 4,096 AUTO REFRES cycles every 64ms (t REF ), regardless of width optio. Providig a distributed AUTO REFRES commad every µs will meet the refresh requiremet ad esure that each row is refreshed. Alteratively, 4,096 AUTO REFRES commads ca be issued i a burst at the miimum cycle rate (t RFC ), oce every 64ms. DEEP POWER DOWN Deep Power Dow Mode is a operatig mode to achieve maximum power reductio by cuttig the power of the whole memory array of the device. Data will ot be retaied oce the device eters DPD Mode. Full iitializatio is required whe the device exits from DPD Mode. The DC value of DPD Mode ca t be zero due to trasistor s leakage curret; a reverse PN diode leakage curret which is called Juctio leakage curret ad a puch-through leakage curret. [Figure29.30] SEF REFRES TheSEFREFREScommadcabeusedtoretaidatai the SDRAM(without exteral clockig), eve if the rest of the system is powered dow. The SEF REFRES commad is iitiated like a AUTO REFRES commad except CKE is disabled (OW). Oce the SEF REFRES commad is registered, all the iputs to the SDRAM become Do t Care with the exceptio of CKE, which must remai OW. Oce self refresh mode is egaged, the SDRAM provides its ow iteral clockig, causig it to perform its ow AUTO REFRES cycles. The SDRAM must remai i self refresh mode for a miimum period equal to t RAS ad may remai i self refresh mode for a idefiite period beyod that. The procedure for exitig self refresh requires a sequece of commads. First, must be stable (meet the clock specificatios i the AC characteristics) prior to CKE goig back IG. Oce CKE is IG, the SDRAM must have commads issued (a miimum of two clocks) for t SR because time is required for the completio of ay iteral refresh i progress. Upo exitig the self refresh mode, AUTO REFRES commads must be issued every µs or less as both SEF REFRES ad AUTO REFRES utilize he row refresh couter.

15 Absolute Maximum Ratigs Voltage o V DD /V D Supply Relative to V SS... 1V to + 3.6V Voltage o Iputs, NC or I/O Pis Relative to V SS. -1V to + 3.6V Storage Temperature(plastic) to Power Dissipatio.. 1W *Stresses greater tha those listed uder Maximum Ratigs may cause permaet damage to the device.this is a stress ratig oly, ad fuctioal operatio of the device at these or ay other coditios above those idicated i the operatioal sectios of this specificatio is ot implied. Exposure to absolute maximum ratig coditios for exteded periods may affect reliability. Operatig Rage Device Rage Ambiet Temperature V DD V D CMS6416Ax-75xS Special -10 to +60 CMS6416Ax-75xC Commercial 0 to +70 CMS6416Ax-75xE Exteded -25 to V to 3.3V 1.65V to V DD CMS6416Ax-75xI Idustrial -40 to +85 DC EECTRICA CARACTERISTICS AND OPERATING CONDITIONS [21,22] Parameter / Coditio Symbol Mi Max Uits Supply Voltage V DD V I/O Supply Voltage V D V Iput igh Voltage : ogic 1 All Iputs [23.] V I 0.8* V D V D +0.3 V Iput ow Voltage : ogic 0 All Iputs [23.] V I V Data Output igh Voltage : ogic 1 : All Iputs(-0.1mA) V O 0.9* V D V Data Output ow Voltage : ogic 0 : All Iputs(0.1mA) V O 0.2 V Iput eakage Curret : Ay Iput 0V=V IN =V DD (All other pis ot uder test=0v) II -5 5 μa Output eakage Curret : s are disabled ; 0V= V OUT =V D l OZ -5 5 μa Table 7. AC OPERATING CONDITIONS [ ] Parameter / Coditio Symbol Value Uits Iput igh Voltage : ogic 1 All Iputs V I 0.9* V D V Iput ow Voltage : ogic 0 All Iputs V I 0.2 V Iput ad Output Measuremet Referece evel 0.5*V D V

16 Table 8. I DD Specificatios ad Coditios [ ]. Parameter Descriptio -75 Uits I DD 1 Operatig Curret : Active Mode ; Burst =1 ; Read or Write ; t RC = t RC (mi); CAS atecy =3 [ ] 35 ma I DD 2p Precharge Stadby Curret i Power Dow Mode ; CKE=OW ; All baks Idle 300 μa I DD 2 Precharge Stadby Curret i o ower dow Mode; CKE=IG ; All baks Idle 12 ma I DD 3p I DD 3 I DD 4 Active Stadby Curret i Power Dow Mode ; CS#=IG ; CKE=OW ; All baks active after t RCD met ; No access i progress [ ] 3 ma Active Stadby Curret i o Power Dow Mode ; CS#=IG ; CKE=IG ; All baks active after t RCD met ; No access i progress [ ] 16 ma Operatig Curret : Burst Mode ; Cotiuous Burst ; Read or Write ; All baks Active ; CAS atecy =3 [ ] 40 ma I DD 5 Auto Refresh Curret : t RC =t RC (mi) CAS atecy=3 ; CKE,CS#=IG [ ] 62 ma I DD 6 Self Refresh Curret : CKE <=0.2V, 4 s 350 μa Self Refresh Curret : CKE <=0.2V, 2 s 250 μa Self Refresh Curret : CKE <=0.2V, 1 s 200 μa I DD 7 Deep power dow 10 μa Note : 21. The miimum specificatios are used oly to idicate cycle time at which proper operatio over the full temperature rage (-40 C = TA = +85 C for IT parts) is esured. 22. A iitial pause of 100µs is required after power-up, followed by two AUTO REFRES commads, before proper device operatio is esured. (V DD ad V D must be powered up simultaeously. V SS ad V SSQ must be at same potetial.) The two AUTO REFRES commad wake-ups should be repeated ay time the t REF refresh requiremet is exceeded. 23. All states ad sequeces ot show are illegal or reserved. 24. I additio to meetig the trasitio rate specificatio, the clock ad CKE must trasit betwee V I ad V I (or betwee V I ad V I) i a mootoic maer. 25. t Z defies the time at which the output achieves the ope circuit coditio; it is ot a referece to V O or V O. The last valid data elemet will meet t O before goig igh-z. 26. AC timig ad I DD tests have V I ad V I, with timig refereced to V I/2 = crossover poit. If the iput trasitio time is loger tha t T (MA), the the timig is refereced at V I (MA) ad V I (MIN) ad o loger at the V I/2 crossover poit. 27. I DD specificatios are tested after the device is properly iitialized. 28. I DD is depedet o output loadig ad cycle rates. Specified values are obtaied with miimum cycle time ad the outputs ope. 29. The I DD curret will icrease or decrease proportioally accordig to the amout of frequecy alteratio for the test coditio. 30. trasitios average oe trasitio every two clocks. 31. Other iput sigals are allowed to trasitio o more tha oce every two clocks ad are otherwise at valid V I or V I levels. 32. CKE is IG durig refresh commad period t RFC (MIN) else CKE is OW. The I DD 6 limit is actually a omial value ad does ot result i a fail value Capacitace Parameter Descriptio Test Coditios Max Uits C IN Iput Capacitace 4 pf T A =25, f=1mhz, V DD(typ) C OUT Output Capacitace 6 pf AC Test oads VD/2 OUTPUT Z0=50Ω 50Ω 30pF

17 AC Characteristics AC Characteristics -75 Symbol Uits Parameter Mi Max Clock Period [33.] ts3 7.5 s ts2 10 Clock igh Time tc 2.5 s Clock ow Time tc 2.5 s Setup Time to Clock tcas 2.0 s old Time to Clock tca 1.0 s CKE Setup Time to Clock tcks 2.0 s CKE old Time to Clock tck 1.0 s C=3 tac(3) 6 s Clock Access Time C=2 tac(2) 7.5 s C=1 tac(1) - s Output old Time from Clock to 2.5 s Data I Setup Time to Clock tcds 2.0 s Data I old Time to Clock tcd 1.0 s /CS, /RAS, /CAS, /WE, /M Setup Time to Clock tcms 2.0 s /CS, /RAS, /CAS, /WE, /M old Time to Clock tcm 1.0 s Data igh Impedace Time [25.] C=2 tz(2) 7.5 s C=3 tz(3) 6 s C=1 tz(1) - s Active to Precharge tras s Active to Active Period trc 70 s Active to Read/Write Delay trcd 18 s Refresh Period(4096 rows) tref 64 ms Auto Refresh Period trfc 70 s Precharge Period trp 18 s Active a to Active b trrd 15 s Trasitio Time [34.] tt s Write Recovery Time [35.] twr 2 tck Write Recovery Time [36.] twr 15 s Exit Self Refresh to Active [37.] tsr 80 s READ/WRITE commad to READ/WRITE commad [38.] tccd 1 tck CKE to clock disable or power-dow etry mode [39.] tcked 1 tck CKE to clock eable or power-dow exit setup mode [39.] tped 1 tck M to iput data delay [38.] td 0 tck M to data mask durig WRITEs [38.] tm 0 tck M to data high-impedace durig READs [38.] tz 2 tck WRITE commad to iput data delay [38.] tdwd 0 tck Data-i to ACTIVE commad [40.] tda t WR +t RP s Data-i to PRECARGE commad [41.] tdp 2 tck ast data-i to burst STOP commad [38.] tbd 1 tck

18 AC Characteristics AC Characteristics -75 Symbol Parameter Mi Max Uits ast data-i to ew READ/WRITE commad [38.] tcd 1 tck ast data-i to PRECARGE commad [41.] trd 2 tck OAD MODE REGISTER commad to ACTIVE or REFRES commad [42.] tmrd 2 tck Data-out to high-impedace from PRECARGE commad [40.] C=2 tro(2) 2 tck C=3 tro(3) 3 tck C=1 tro(1) 1 tck Note : 33. The clock frequecy must remai costat (stable clock is defied as a sigal cyclig withi timig costraits specified for the clock pi) durig access or precharge states (READ, WRITE, icludig t WR, ad PRECARGE commads). CKE may be used to reduce the data rate. 34. AC characteristics assume t T = 1s. 35. Auto precharge mode oly. 36. Precharge mode oly. 37. must be toggled a miimum of two times durig this period. 38. Required clocks are specified by JEDEC fuctioality ad are ot depedet o ay timig parameter. 39. Timig actually specified by t CKS; clock(s) specified as a referece oly at miimum cycle rate. 40. Timig actually specified by t WR plus t RP; clock(s) specified as a referece oly at miimum cycle rate. 41. Timig actually specified by t WR. 42. JEDEC ad PC100 specify three clocks.

19 Operatio BANK / ROW ACTIVATION Before ay READ or WRITE commads ca be issued to a bak withi the SDRAM, a row i that bak must be opeed (activated). This is accomplished via the ACTIVE commad, which selects both the bak ad the row to be activated. A READ or WRITE commad may the be issued to that row, subject to the t RCD specificatio. t RCD (MIN) should be divided by the clock period ad rouded up to the ext whole umber to determie the earliest clock edge after the ACTIVE commad o which a READ or WRITE commad ca be etered. For example, a t RCD specificatio of 20s with a 125 Mhz clock (8s period) results i 2.5 clocks, rouded to 3. (The same procedure is used to covert other specificatio limits from time uits to clock cycles.) A subsequet ACTIVE commad to a differet row i the same bak ca oly be issued after the previous active row has bee closed (precharged). The miimum time iterval betwee successive ACTIVE commads to the same bak is defied by t RC. A subsequet ACTIVE commad to aother bak ca be issued while the first bak is beig accessed, which results i a reductio of total row-access overhead. The miimum time iterval betwee successive ACTIVE commads to differet baks is defied by t t RRD. READs READ bursts are iitiated with a READ commad, as show i Figure 3. The startig colum ad bak addresses are provided with the READ commad, ad auto precharge is either eabled or disabled for that burst access. For the geeric READ commads used i the followig illustratios, auto precharge is disabled. Durig READ bursts, the valid data-out elemet from the startig colum address will be available followig the CAS latecy after the READ commad. Each subsequet data-out elemet will be valid by the ext positive clock edge. Figure 2. shows geeral timig for each possible CAS latecy settig. Upo completio of a burst, assumig o other commads have bee iitiated, the s will go igh-z. A fullpage burst will cotiue util termiated. (The burst will wrap aroud at the ed of the page). A cotiuous flow of data ca be maitaied by havig addtioal Read Burst or sigle Read. The first data elemet from the ew burst follows either the last elemet of a completed burst or the last desired data elemet of a loger burst that is beig trucated. The ew READ commad should be issued x cycles before the clock edge at which the last desired data elemet is valid, where x equals the CAS latecy mius oe. This is show i Figure 4. for CAS latecies of oe, two ad three; data elemet + 3 is either the last of a burst of four or the last desired of a loger burst. Full-speed radom read accesses ca be performed to the same bak, as show i Figure 5., or each subsequet READ may be performed to a differet bak. Read CKE igh /CS /RAS /CAS /WE A0-A7 Colum A9, A11 Eable Auto Precharge A10 BA0, 1 Disable Auto Precharge Do t Care Figure 3. Read

20 T3 T4 T5 Read Read Col =0cycles Col b b CAS atecy=1 T3 T4 T5 T6 =1cycles Read Read Col Col b b CAS atecy=2 Figure 4. Cosecutive Burst Reads -Trasitio from Burst of 4 Read to a Sigle read for CAS atecy 1,2,3

21 T3 T4 T5 T6 T7 Read Read =2cycles Col Col b b CAS atecy=3 Figure 4. Cosecutive Burst Reads -Trasitio from Burst of 4 Read to a Sigle read for CAS atecy 1,2,3 T3 T4 Read Read Read Read Col Col a Col x Col m a x m CAS atecy=1 Figure 5. Radom Read Accesses for CAS atecy =1,2,3

22 T3 T4 T5 Read Read Read Read Col Col a Col x Col m a x m CAS atecy=2 T3 T4 T5 T6 Read Read Read Read Col Col a Col x Col m a x m CAS atecy=3 Figure 5. Radom Read Accesses for CAS atecy =1,2,3 A Read Burst ca be termiated by a subsequet Write commad, ad data from a fixed legth READ burst may be immediately followed by data from a WRITE commad (subject to bus turaroud limitatios). The WRITE burst may be iitiated o the clock edge immediately followig the last (or last desired) data elemet from the READ burst, provided that I/O cotetio ca be avoided. I a give system desig, there may be a possibility that the device drivig the iput data will go ow-z before the SDRAM s go igh-z. I this case, at least a sigle-cycle delay should occur betwee the last read data ad the WRITE commad. The M iput is used to avoid I/O cotetio, as show i Figure 6. ad Figure 7.. The M sigal must be asserted (IG) at least two clocks prior to the WRITE commad (M latecy is two clocks for output buffers) to suppress data-out from the READ. Oce the WRITE commad is registered, the s will go igh-z (or remai igh-z), regardless of the state of the M sigal, provided the M

23 was active o the clock just prior to the WRITE commad that trucated the READ commad. The M sigal must be asserted prior to the WRITE commad (M latecy is zero clocks for iput buffers) to esure that the writte data is ot masked. Figure 6. shows the case where the clock frequecy allows for bus cotetio to be avoided without addig a cycle, ad Figure 7. shows the case where the additioal is eeded. T3 T4 M t CK Read Write Col Col b t Z b CAS atecy=3 t DS Figure 6. Read to Write

24 T3 T4 T5 M t CK Read Write Col Col b t Z CAS atecy=3 b t DS Figure 7. Read to Write with extra clock cycle T3 T4 T5 T6 T7 T8 CMD Read Write Read masked by write M CMD Read Write Read masked by M M CMD M Read Write Read CAS= Figure 8. Read Iterrupted by Write ad M ; CAS atecy =2

25 A fixed-legth READ burst or a full-page burst may be followed by, or trucated with, a PRECARGE commad to the same bak. The PRECARGE commad should be issued x cycles before the clock edge at which the last desired data elemet is valid, where x equals the CAS latecy mius oe. This is show i Figure 9. for each possible CAS latecy; data elemet + 3 is either the last of a burst of four or the last desired of a loger burst. Followig the PRECARGE commad, a subsequet commad to the same bak caot be issued util t RP is met. Note that part of the row precharge time is hidde durig the access of the last data elemet(s). The BURST TERMINATE commad should be issued x cycles before the clock edge at which the last desired data elemet is valid, where x equals the CAS latecy mius oe. This is show i Figure 10. for each possible CAS latecy; data elemet + 3 is the last desired data elemet of a loger burst. T3 T4 T5 T6 T7 t RP Read Precharge Active =0cycles a Col (a or all) a Row CAS atecy=1 T3 T4 T5 T6 T7 t RP Read Precharge Active =1cycles a Col (a or all) a Row CAS atecy=2 Figure 9. Read to Precharge

26 T3 T4 T5 T6 T7 t RP Read Precharge Active =2cycles a Col (a or all) a Row CAS atecy=3 Figure 9. Read to Precharge T3 T4 T5 T6 T7 Read Burst Termiate =0cycles a Col CAS atecy=1 Figure 10. Termiatig a Read Burst

27 T3 T4 T5 T6 T7 Read Burst Termiate =1cycles a Col CAS atecy=2 T3 T4 T5 T6 T7 Read Burst Termiate =2cycles a Col CAS atecy=3 Figure 10. Termiatig a Read Burst

28 COCK CKE /CS t RC *ote 45. IG /RAS /CAS t RCD *ote 46. t RP ADDR RAa CAa RAb CAb BA0 BA1 A10/AP RAa RAb t O C=2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 t RAC *ote 47. t SAC t SZ *ote 48. t DP t O C=3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 t RAC *ote 47. t SAC t SZ *ote 48. t DP /WE M Row Active (A-) Read (A-) Precharge (A-) Row Active (A-) Write (A-) Precharge (A-) Do t Care Note : 45. Miimum row cycle times is required to complete iteral DRAM operatio. 46. Row precharge ca iterrupt burst o ay cycle.[cas atecy -1] umber of valid output data is available after Row precharge. ast valid output will be i-z(t SZ) after the clock. 47. Access time from Row active commad. t CC *(t RCD + CAS latecy - 1) + t SAC 48. Out put will be i-z after the ed of burst. (1,2,3,8 & Full page bit burst) Figure 11. Read & Write Cycle at egth=4, t DP =2 (100Mhz)

29 COCK CKE /CS t RC *ote 45. IG t RCD t RP /RAS *ote 46. /CAS ADDR RAa CAa RAb CAb BA0 BA1 A10/AP RAa RAb t O C=2 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 t RAC *ote 47. t SAC t SZ *ote 48. t DP t O C=3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 t RAC *ote 47. t SAC t SZ *ote 48. t DP /WE M Row Active (A-) Read (A-) Precharge (A-) Row Active (A-) Write (A-) Do t Care Figure 12. Read & Write Cycle at egth=4, t DP =2 (133Mhz)

30 COCK CKE IG /CS /RAS *ote 49. /CAS ADDR RAa RBb CAa RCc CBb RDd CCc CDd BA0 BA1 A10/AP RAa RBb RCc RDd C=2 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 C=3 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 /WE M Row Active (A-) Read (A-) Read (B-) Read (C-) Read (D-) Precharge (D-) Row Active (B-) Row Active (C-) Precharge (A-) Precharge (B-) Precharge (C-) Do t Care Note : 49. Row precharge will iterrupt writig. ast data iput, t DP before Row precharge, will be writte. Figure 13. Page Read Cycle at Burst egth=4 WRITE WRITE bursts are iitiated with a WRITE commad,as show i Figure 14. The startig colum ad bak addresses are provided with the WRITE commad, ad auto precharge is

31 either eabled or disabled for that access. If auto precharge is eabled, the row beig accessed is precharged at the completio of the burst. Durig WRITE bursts, the first valid data-i elemet will be registered coicidet with the WRITE commad. Subsequet data elemets will be registered o each successive positive clock edge. Upo completio of a fixedlegth burst, assumig o other commads have bee iitiated, the s will remai igh-z ad ay additioal iput data will be igored (see Figure 15.). A fullpage burst will cotiue util termiated. (wrap aroud at the ed of the page) A example is show i Figure 16.. Data + 1 is either the last of a burst of two or the last desired of a loger burst. A WRITE commad ca be iitiated o ay clock cycle followig a previous WRITE commad. Full-speed radom write accesses withi a page ca be performed to the same bak, as show i Figure 17., or each subsequet WRITE may be performed to a differet bak. Write CKE igh /CS /RAS /CAS /WE A0-A7 Colum A9, A11 Eable Auto Precharge A10 Disable Auto Precharge BA0, 1 Do t Care Figure 14. Write

32 T3 Write Col +1 Figure 15. Write Burst - Burst legth of 2 Write Write Col Col b +1 b Figure 16. Write to Write - Trasitio from a burst of 2 to a sigle write Data for a fixed-legth WRITE burst a full-page WRITE burst may be followed by, or trucated with, a PRECARGE commad to the same bak.the PRECARGE commad should be issued t WR after the clock edge at which the last desired iput data elemet is registered. The auto precharge mode requires a t WR of at least oe clock plus time, regardless of frequecy. I additio, whe trucatig a WRITE burst, the M sigal must be used to mask iput data for the clock edge prior to, ad the clock edge coicidet with, the PRECARGE commad. A example is show i Figure 19. Data + 1 is either the last of a burst of two or the last desired of a loger burst. Followig the PRECARGE commad, a subsequet commad to the same bak caot be issued util t RP is met.

33 T3 Write Write Write Write Col Col a Col x Col m a x m Figure 17. Radom Write Cycles T3 T4 T5 Write Read Col Col b +1 b b+1 Figure 18. Write to Read Burst of 2 Write ad Read(CAS atecy =2)

34 T3 T4 T5 T6 M t CK >=15s t RP Write Precharge Active Col (a or all) a Row t WR +1 M t CK <=15s t RP Write Precharge Active Col (a or all) a Row t WR +1 Figure 19. Write to Precharge Write Burst Termiate Next Col () (Data) Figure 20. Termiatig a Write Burst Fixed-legth or full-page WRITE bursts ca be trucated with the BURST TERMINATE commad. Whe trucatig a WRITE burst, the iput data applied coicidet with the BURST TERMINATE commad will be igored. The last data writte (provided that M is OW at that time) will be the iput data applied oe clock previous to the BURST TERMINATE

35 commad. This is show i Figure 20., where data is the last desired data elemet of a loger burst. PRECARGE The PRECARGE commad (see Figure 21. ) is used to deactivate the ope row i a particular bak or the ope row i all baks. The bak(s) will be available for a subsequet row access some specified time (t RP )aftertheprecarge commad is issued. Iput A10 determies whether oe or all baks are to be precharged, ad i the case where oly oe bak is to be precharged, iputs BA0, BA1 select the bak. Whe all baks are to be precharged, iputs BA0, BA1 are treated as Do t Care. Oce a bak has bee precharged, it is i the idle state ad must be activated prior to ay READ or WRITE commads beig issued to that bak. POWER-DOWN Power-dow occurs if CKE is registered OW coicidet with a or COMMAND INIBIT whe o accesses are i progress. If power-dow occurs whe all baks are idle, this mode is referred to as precharge power-dow; if power-dow occurs whe there is a row active i ay bak, this mode is referred to as active power-dow. Eterig power-dow deactivates the iput ad output buffers, excludig CKE, for maximum power savigs while i stadby. The device may ot remai i the power-dow state loger tha the refresh period (64ms) sice o refresh operatios are performed i this mode. The power-dow state is exited by registerig a or COMMAND INIBIT ad CKE IG at the desired clock edge(meetig t CKS ). See Figure 22..

36 Precharge CKE igh /CS /RAS /CAS /WE A0-A9 All baks A10 BA0, 1 Selected Do t Care Figure 21. Precharge

37 t CKS >=t CKS CKE Active All baks Idle Iput buffers gated off t RCD t RAS t RC Eter Power Dow Mode Exit Power Dow Mode Figure 22. Power Dow COCK SUSPEND The clock susped mode occurs whe a colum access/ burst is i progress ad CKE is registered OW. I the clock susped mode, the iteral clock is deactivated, freezig the sychroous logic. For each positive clock edge o which CKE is sampled OW, the ext iteral positive clock edge is suspeded. Ay commad or data preset o the iput pis at the time of a suspeded iteral clock edge is igored; ay data preset o the pis remais drive; ad burstcouters are ot icremeted, as log as the clock is suspeded. (See examples i Figure 23. ad Figure 24..) Clock susped mode is exited by registerig CKE IG; the iteral clock ad related operatio will resume o the subsequet positive clock edge. BURST READ/SINGE WRITE I this mode, all WRITE commads result i the access of a sigle colum locatio (burst of oe), regardless of the programmed burst legth. The burst read/sigle write mode is etered by programmig the write burst mode bit (M9) i the mode register to a logic 1. READ commads access colums accordig to the programmed burst legth ad sequece.

38 T3 T4 T5 CKE Iteral Write Col Figure 23. Clock Susped Durig Write Burst

39 T3 T4 T5 T6 CKE Iteral Read Col Figure 24. Clock Susped Durig Read Burst - Burst of 4 (CAS latecy =2) Cocurret Auto Precharge If a access commad with Auto Precharge is beig execeuted a access commad (either a Read or Write ) is ot allowed by SDRAM s. If this feature is allowed the the SDRAM supports Cocurret Auto Precharge. Fidelix SDRAMs support Cocurret Auto Precharge. Four casees where Cocurret Auto Precharge occurs are defied below. Read With Auto Precharge 1.Iterrupted by a Read(with or without auto precharge): A read to bak m will iterrupt a Read o bak, CAS latecy later. The precharge to bak will begi whe the Read to bak m is registered. (Figure 25. ) 2. Iterrupted by a Write(with or without auto precharge): A Write to bak m will iterrupt a Read o bak whe registered. M should be used two clocks prior to the Write commad to prevet bus cotetio. The Precharge to bak will begi whe the write to bak m is registered. (Figure 26. ) Write with Auto Precharge 3. Iterrupted by a Read(with or without auto precharge): A Read to bak m will iterrupt a Write o bak whe registered, with the data-out appearig CAS latecy later. The Precharge to bak will begi after t WR is met, where t WR begis whe the Read to bak m is registered. The last valid Write to bak will be data-i registered oe clock prior to the Read to bak m.(figure 27. ) 4. Iterrupted by a Write ( with or without auto Precharge): A Write to bak m will iterrupt a Write o bak whe registered. The Precharge to bak will begi after t WR is met,where t WR begis whe the Write to bak m is registered. The latest valid data Write to bak will be data registered oe clock prior to a Write to bak m.( Figure 28. )

40 T3 T4 T5 T6 T7 Read-AP Read-AP m Iteral States t RP - t RP - m Page Active Read with a Burst of 4 Iterrupt Burst, Precharge Idle m Page Active Read with Burst of 4 Precharge Col a m Col d a a+1 d d+1 CAS atecy=3( ) CAS atecy=3( m) Figure 25. Read with Auto Precharge Iterrupted by a Read(CAS atecy =3) T3 T4 T5 T6 T7 Read-AP Write-AP m Iteral States t RP - t WR - m Page Active Read with a Burst of 4 Iterrupt Burst, Precharge Idle m Page Active Write with Burst of 4 Write- Col a m Col d M a d d+1 d+2 d+3 CAS atecy=3( ) Figure 26. Read With Auto Precharge Iterrupted by a Write(Read CAS atecy =3)

41 T3 T4 T5 T6 T7 Write-AP Read-AP m Iteral States t WR - t RP - m Page Active Write with a Burst of 4 Iterrupt Burst, Write- Precharge t RP - m Page Active Read with Burst of 4 Precharge Col a m Col d a a+1 d d+1 CAS atecy=3( m) Figure 27. Write with Auto Precharge Iterrupted by a Read(CAS atecy =3) T3 T4 T5 T6 T7 Write-AP Write-AP m Iteral States t WR - t RP - Page Active Write with a Burst of 4 Iterrupt Burst, Write- Precharge t WR - m m Page Active Write with Burst of 4 Write- Col a m Col d a a+1 a+2 d d+1 d+2 d+2 Figure 28. Write with Auto Precharge Iterrupted by a Write

42 DEEP POWER DOWN MODE ENTRY The Deep Power Dow Mode is etered by havig burst termiatio commad, while CKE is low. The Deep Power Dow Mode has to be maitaied for a miimum of 100us. The followig diagram illustrates Deep Power Dow mode etry. CKE t RP Precharge All Burst Termiate Precharge If eeded Deep Power Dow Etry Figure 29. Deep Power Dow Mode Etry DEEP POWER DOWN MODE EIT SEQUENCE The Deep Power Dow Mode is exited by assertig CKE high. After the exit, the followig sequece is eeded to eter a ew commad 1. Maitai iput coditios for a miimum of 200us 2. Issue precharge commads for all baks of the device 3. Issue 8 or more auto refresh commads 4. Issue a mode register set commad to iitialize the mode register 5. Issue a exteded mode register set commad to iitialize the exteded mode register The followig timig diagram illustrates deep power dow exit sequece CKE Precharge All AREF MRS EMRS Active A10 Key Key a Row 200 us t RP Deep Power Dow Exit Precharge All Normal MRS Exteded MRS Row Active A Figure 30. Deep Power Dow Mode Exit

43 Table 9. CKE [ ]. CKE -1 CKE Curret State Actio Power Dow Maitai Power Dow Self Refresh Maitai Self Refresh Clock Susped Maitai Clock Susped Power Dow [54.] Self Refresh [55.] Ihibit or Ihibit or Exit Power Dow Exit Self Refresh Clock Susped [56.] Exit Clock Susped All s Idle Ihibit or Power Dow Etry All s Idle Readig or Writig Auto Refresh Valid Self Refresh Etry Clock Susped Etry See Table 10. Note : 50. CKE is the logic state of CKE at clock edge ; CKE -1 was the state of CKE at the previous clock edge. 51. Curret State is the state of the SDRAM immediatly prior to the clock edge. 52. is the commad registered at clock edge, ad Actio is a result of. 53. All states ad sequeces ot show are illegal or reserved. 54. Exitig power dow at clock edge will put the device i all the baks idle state i time for clock edge +1(provided the t CKS is met) 55. Exitig self refresh at clock edge will put the device i all the baks idle state oce t SR is met. Ihibit or commads should be issued o ay clock edges occurig durig the t SR period. A miimum of two commads must be provided durig the t SR period. 56. After exitig clock susped at clock edge, the device will resume operatio ad recogize the ext commad at clock edge +1. Table 10. Curet State, to [ ]. Curret State CS# RAS# CAS# WE# (Actio) Ay Idle COMMAND INIBIT (/Cotiue previous operatio) NO OPERATION (/Cotiue previous operatio) ACTIVE (Select ad activate row) AUTO REFRES [63.] OAD MODE REGISTER [63.] PRECARGE [67.] Note : 57. This table applies whe CKE -1 was IG ad CKE is IG (see Table 9. ) ad after t SR has bee met (if the previous state was self refresh). 58. This table is bak-specific, except where oted; i.e., the curret state is for a specific bak ad the commads show are those allowed to be issued to that bak whe i that state. Exceptios are covered i the otes below. 59. Curret state defiitios: Idle: The bak has bee precharged, ad t RP has bee met. Row Active: A row i the bak has bee activated, ad t RCD has bee met. No data bursts/accesses ad o register accesses are i progress. Read: A READ burst has bee iitiated, with auto precharge disabled, ad has ot yet termiated or bee termiated. Write: A WRITE burst has bee iitiated, with auto precharge disabled, ad has ot yet termiated or bee termiated. 60. The followig states must ot be iterrupted by a commad issued to the same bak. COMMAND INIBIT or commads, or allowable commads to the other bak should be issued o ay clock edge occurrig durig these states. Allowable commads to the other bak are determied by its curret state ad Table 10. ad accordig to Table 11.. Prechargig: Starts with registratio of a PRECARGE commad ad eds whe t RP is met. Oce t RP is met, the bak will be i the idle state. Row Activatig: Starts with registratio of a ACTIVE commad ad eds whe t RCD is met. Oce t RCD is met, the bak will be i the row active state. Read w/auto Precharge Eabled: Starts with registratio of a READ commad with auto precharge eabled ad eds whe t RP has bee met. Oce t RP is met, the bak will be i the idle state. Write w/auto Precharge Eabled: Starts with registratio of a WRITE commad with auto precharge eabled ad eds whe t RP has bee met. Oce t RP is met, the bak will be i the idle state. 61. The followig states must ot be iterrupted by ay executable commad; COMMAND INIBIT or commads must be applied o each positive clock edge durig these states. Refreshig: Starts with registratio of a AUTO REFRES commad ad eds whe t RC is met. Oce t RC is met, the SDRAM will be i the all baks idle state. Accessig Mode Register: Starts with registratio of a OAD MODE REGISTER commad ad eds whe t MRD has bee met. Oce t MRD is met, the SDRAM will be i the all baks idle state. Prechargig All: Starts with registratio of a PRECARGE A commad ad eds whe t RP is met. Oce t RP is met, all baks will be i the idle state. 62. All states ad sequeces ot show are illegal or reserved. 63. Not bak-specific; requires that all baks are idle. 64. May or may ot be bak-specific; if all baks are to be precharged, all must be i a valid state for prechargig. 65. Not bak-specific; BURST TERMINATE affects the most recet READ or WRITE burst, regardless of bak. 66. READs or WRITEs listed i the (Actio) colum iclude READs or WRITEs with auto precharge eabled ad READs or WRITEs with auto precharge disabled. 67. Does ot affect the state of the bak ad acts as a to that bak.

44 Table 10. Curet State, to [ ]. Curret State CS# RAS# CAS# WE# (Actio) Row Active Read(Auto Precharge Disabled) Write (Auto Precharge Disabled) READ (Select colum ad start READ burst) [66.] WRITE (Select colum ad start WRITE burst) [66.] PRECARGE (Deactivate row i bak or baks) [64.] READ (Select colum ad start ew READ burst) [66.] WRITE (Select colum ad start WRITE burst) [66.] PRECARGE (Trucate READ burst, start RECARGE) [64.] BURST TERMINATE [65.] READ (Select colum ad start READ burst) [66.] WRITE (Select colum ad start ew WRITE burst) [66.] PRECARGE (Trucate WRITE burst, start PRECARGE) [64.] BURST TERMINATE [65.] Table 11. Curret State, to m [ ]. Curret State CS# RAS# CAS# WE# (Actio) Ay COMMAND INIBIT (/Cotiue previous operatio) NO OPERATION (/Cotiue previous operatio) Idle Ay Otherwise Allowed to m Row Activatig, Active, or Prechargig Read(Auto Precharge Disabled) Write(Auto Precharge Disabled) ACTIVE (Select ad activate row) READ (Select colum ad start READ burst) [74.] WRITE (Select colum ad start WRITE burst) [74.] PRECARGE ACTIVE (Select ad activate row) READ (Select colum ad start ew READ burst) [74.78.] WRITE (Select colum ad start WRITE burst) [74.79.] PRECARGE [76.] ACTIVE (Select ad activate row) READ (Select colum ad start READ burst) [74.79.] WRITE (Select colum ad start ew WRITE burst) [76.80.] PRECARGE [76.]

45 Table 11. Curret State, to m [ ]. Curret State CS# RAS# CAS# WE# (Actio) Read (With Auto Precharge) Write (With Auto Precharge) ACTIVE (Select ad activate row) READ (Select colum ad start ew READ burst) [ ] WRITE (Select colum ad start WRITE burst) [ ] PRECARGE [76.] ACTIVE (Select ad activate row) READ (Select colum ad start READ burst) [ ] WRITE (Select colum ad start ew WRITE burst) [ ] PRECARGE [76.] Note : 68. This table applies whe CKE -1 was IG ad CKE is IG ad after t SR has bee met (if the previous state was self refresh). 69. This table describes alterate bak operatio, except where oted; i.e., the curret state is for bak ad the commads show are those allowed to be issued to bak m (assumig that bak m is i such a state that the give commad is allowable). Exceptios are covered i the otes below. 70. Curret state defiitios: Idle: The bak has bee precharged, ad t RP has bee met. Row Active: A row i the bak has bee activated, ad t RCD has bee met. No data bursts/accesses ad o register accesses are i progress. Read: A READ burst has bee iitiated, with auto precharge disabled, ad has ot yet termiated or bee termiated. Write: A WRITE burst has bee iitiated, with auto precharge disabled, ad has ot yet termiated or bee termiated. Read w/auto Precharge Eabled: Starts with registratio of a READ commad with auto precharge eabled, ad eds whe t RP has bee met. Oce t RP is met, the bak will be i the idle state. Write w/auto Precharge Eabled: Starts with registratio of a WRITE commad with auto precharge eabled, ad eds whe t RP has bee met. Oce t RP is met, the bak will be i the idle state. 71. AUTO REFRES, SEF REFRES ad OAD MODE REGISTER commads may oly be issued whe all baks are idle. 72. A BURST TERMINATE commad caot be issued to aother bak; it applies to the bak represeted by the curret state oly. 73. All states ad sequeces ot show are illegal or reserved. 74. READs or WRITEs to bak m listed i the (Actio) colum iclude READs or WRITEs with auto precharge eabled ad READs or WRITEs with auto precharge disabled. 75. CONCURRENT AUTO PRECARGE: will iitiate the auto precharge commad whe its burst has bee iterrupted by bak m s burst. 76. Burst i bak cotiues as iitiated. 77. For a READ without auto precharge iterrupted by a READ (with or without auto precharge), the READ to bak m will iterrupt the READ o bak, CAS latecy later. 78. For a READ without auto precharge iterrupted by a WRITE (with or without auto precharge), the WRITE to bak m will iterrupt the READ o bak whe registered. M should be used twwo clock prior to the WRITE commad to prevet bus cotetio. 79. For a WRITE without auto precharge iterrupted by a READ (with or without auto precharge), the READ to bak m will iterrupt the WRITE o bak whe registered, with the data-out appearig CAS latecy later. The last valid WRITE to bak will be data-i registered oe clock prior to the READ to bak m. 80. For a WRITE without auto precharge iterrupted by a WRITE (with or without auto precharge), the WRITE to bak m will iterrupt the WRITE o bak whe registered. The last valid WRITE to bak will be data-i registered oe clock prior to the READ to bak m. 81. For a READ with auto precharge iterrupted by a READ (with or without auto precharge), the READ to bak m will iterrupt the READ o bak, CAS latecy later. The PRECARGE to bak will begi whe the READ to bak m is registered (Figure 25.). 82. For a READ with auto precharge iterrupted by a WRITE (with or without auto precharge), the WRITE to bak m will iterrupt the READ o bak whe registered. M should be used two clocks prior to the WRITE commad to prevet bus cotetio. The PRECARGE to bak will begi whe the WRITE to bak m is registered (Figure 26. ). 83. For a WRITE with auto precharge iterrupted by a READ (with or without auto precharge), the READ to bak m will iterrupt the WRITE o bak whe registered, with the data-out appearig CAS latecy later. The PRECARGE to bak will begi after t WR is met, where t WR begis whe the READ to bak m is registered. The last valid WRITE to bak will be data-i registered oe clock prior to the READ to bak m(figure 27. ). 84. For a WRITE with auto precharge iterrupted by a WRITE (with or without auto precharge), the WRITE to bak m will iterrupt the WRITE o bak whe registered. The PRECARGE to bak will begi after t WR is met, where t WR begis whe the WRITE to bak m is registered. The last valid WRITE to bak will be data registered oe clock prior to the WRITE to bak m (Figure 28. ).

46 PACKAGE DIMENSION 54 BA FINE PITC BGA (8 x 8 x 1.0 mm) Uit : millimeters Top View E Bottom View E1 A1 INDE MARK A B A B e #A1 C D C D E D D1 E F F G J G J D/2 e E/2 Side View b z A E - Mi Typ Max A E E D D e b z

47 PACKAGE DIMENSION 60 BA FINE PITC BGA (6.4 x 10.1 x 1.0 mm) Uit : millimeters