256M(8Mx32) Low Power SDRAM 2 pcs of 128Mb components

Transcription

1 CMS4S32Ax 75xx 256M(8Mx32) ow Power SDRAM 2 pcs of 28Mb compoets Revisio.3 Dec. 26

2 CMS4S32Ax 75xx Documet Title 256M(8Mx32) ow Power SDRAM Revisio istory Revisio No. istory Draft date Remark. Iitial Draft Apr.23 rd, 25 Prelimiary. I/O voltage modified, mior chages Sep.9 th, 25.2 Added (FbFree & aloge Free) descriptios Nov.st, 25.3 Revised IDD6 from 8uA to 9uA Dec.7th, 25 2

3 Features Fuctioality Stadard SDRAM Fuctioality Programmable burst legths :, 2, 4, 8, or full page JEDEC Compatibility ow Power Features ow voltage power supply : 2.5V Auto TCSR(Temperature Compesated Self Refresh) Partial Array Self Refresh powersavig mode Deep Power Dow Mode Driver Stregth Cotrol Operatig Temperature Rages: Special ( to +6 ) Commercial ( to +7 ) Exteded (25 to +85 ) Idustrial (4 to +85 ) CMS4S32Ax 75xx 256M(8Mx32) ow Power SDRAM VCMOS Compatible IO Iterface 9ball FBGA with.8mm ball pitch CMS4S32AF : ead CMS4S32AG : ead Free 2 pcs of 28Mb compoets Fuctioal Descriptio The CMS4S32AFFamily is highperformace CMOS Dyamic RAMs (DRAM) orgaized as 8M x 32. These devices feature advaced circuit desig to provide low active curret ad extremely low stadby curret. The device is compatible with the JEDEC stadard PSDRAM specificatios. ogic Block Diagram CKE CK /CS /WE /CAS /RAS Cotrol ogic Mode Register Exteded Mode Register Refresh Couter Row Mux Row Row Addr atch/ atch/ Decoder Decoder Memory Array 8Kx8K 3 2 Sese Amp Data Output Register M M3 AA BABA Register Cotrol ogic Colum atch Colum Colum Colum Decoder Colum Decoder Decoder Decoder Write Drivers M Mask Data Iput Register 3 Selectio Guide Device Voltage Frequecy Access Time Trcd Trp Core I/O C=2 C=3 CMS4S32AF75xx V.65V DD 33Mz Mz 7s 6s 8s 8s 8s 8s 3

4 CMS4S32Ax 75xx Pi Cofiguratio 9 ball.8mm pitch FBGA(8mm x 3mm) Top View A VSS VDD 23 2 B 28 V D VSSQ VD VSSQ 9 C VSSQ VD D VSSQ VD E V D 3 NC NC 6 VSSQ F VSS M3 A3 A 2 M2 V DD G A4 A 5 A 6 A A A A7 A 8 NC NC BA A J CK CKE A9 BA /CS /RAS K M NC NC /CAS /WE M V D 8 VSS V DD 7 VSSQ M VSSQ VD N V SSQ VD P V D V SSQ V D VSSQ 4 R 3 5 VSS V DD 2 4

5 CMS4S32Ax 75xx Pi Descriptio Symbol CK CKE Type Iput Iput Descriptio Clock : CK is drive by the system clock. All SDRAM iput sigals are sampled o the positive edge of CK. CK also icremets the iteral burst couter ad cotrols the output registers. Clock Eable: CKE activates(ig) ad deactivates(ow) the CK sigal. Deactivatig the clock provides PRECARGE POWERDOWN ad SEF Refresh operatio(all baks idle), ACTIVE POWERDOWN(row active i ay bak) or COCK SUSPEND operatio(burst/access i progress). CKE is sychroous except after the device eters powerdow ad self refresh modes, where CKE becomes asychroous util after exitig the same mode. The iput buffers, icludig CK, are disabled durig powerdow ad self refresh modes, providig low stadby power. CKE may be tied IG. /CS /CAS, /RAS, /WE M3 BA, BA AA NC V D V SSQ V DD V SS Iput Iput Iput Iput Iput I/O Supply Supply Supply Supply Chip Select: /CS eables (registered OW) ad disables (registered IG) the commad decoder. All commads are masked whe /CS is registered IG. /CS provides for exteral bak selectio o systems with multiple baks. /CS is cosidered part of the commad code. Iputs : /CAS, /RAS, ad /WE (alog with /CS) defie the commad beig etered. Iput/Output Mask: M is sampled IG ad is a iput mask sigal for write accesses ad a output disable sigal for read accesses. Iput data is masked durig a WRITE cycle. The output buffers are placed i a ighz state (twoclock latecy) whe durig a READ cycle. M correspods to 7, M correspods to 8 5, M2 correspods to 623, ad M3 correspods to 243. Iput(s): BA ad BA defie to which bak the ACTIVE, READ, WRITE or PRECARGE commad is beig applied. These pis also provide the opcode durig a OAD MODE REGISTER commad. Iputs: A A are sampled durig the ACTIVE commad (row address A A) ad READ/WRITE commad (columaddress A A8; with A defiig auto precharge) to select oe locatio out of the memory array i the respective bak. A is sampled durig a PRECARGE commad to determie if all baks are to be precharged (A IG) or bak selected by BA, BA (A OW). The address iputs also provide the opcode durig a OAD MODE REGISTER commad. Data Iput/Output : Data bus No Coect Power: Provide isolated power to s for improved oise immuity. Groud: Provide isolated groud to s for improved oise immuity. Power Supply: Voltage depedat o optio. Groud. 5

6 CMS4S32Ax 75xx FUNCTIONA DESCRIPTION The Fidelix 256Mb SDRAM is a quadbak DRAM that operates at.8v or 2.5V ad icludes a sychroous iterface (all sigals are registered o the positive edge of the clock sigal, CK ). Read ad write accesses to the SDRAM are burst orieted; accesses start at a selected locatio ad cotiue for a programmed umber of locatios i a programmed sequece. Accesses begi with the registratio of a ACTIVE commad, which is the followed by a READ or WRITE commad. The address bits registered coicidet with the ACTIVE commad are used to select the bak ad row to be accessed (BA ad BA select the bak, A A select the row). The address bits (AA8) registered coicidet with the READ or WRITE commad are used to select the startig colum locatio for the burst access.the SDRAM must be iitialized prior to ormal operatio. The followig sectios provide detailed iformatio regardig device iitializatio, register defiitio, commad descriptios ad device operatio. Iitializatio SDRAMs must be powered up ad iitialized i a predefied maer. Operatioal procedures other tha those specified may result i udefied operatio. Oce power is applied to V DD ad V D(simultaeously) ad the clock is stable (meets the clock specificatios i the AC characteristics), the SDRAM requires a µs delay prior to issuig ay commad other tha a COMMAND INIBIT or. The COMMAND INIBIT or should be applied at least oce durig the µs delay. After the µs delay, a PRECARGE commad should be applied. All baks must the be precharged, thereby placig the device i the all baks idle state. Oce i the idle state, two AUTO REFRES cycles must be performed. After the AUTO REFRES cycles are complete, the SDRAM is ready for mode register programmig. Because the mode register will power up i a ukow state, it should be loaded prior to applyig ay operatioal commad. Refer Figure. 6

7 CMS4S32Ax 75xx Figure. Iitialize ad oad Mode Register [.2.3.] CK CKE /CS /RAS /CAS ADDR Key Key Key BA RAa BA RAa A/AP Key iz iz /WE M igh level is ecessary t RP t RC t RC Precharge (All ) Auto Refresh Auto Refresh Normal MRS Exteded MRS Row Active a Note :. The two AUTO REFRES commads at T4 ad T9 may be applied before either OAD MODE REGISTER (MR) commad. 2. PRE = PRECARGE commad, MR = OAD MODE REGISTER commad, AR = AUTO REFRES commad, ACT = ACTIVE commad, RA = Row, BA = 3. The oad Mode Register for both MR/EMR ad 2 Auto Refresh commads ca be i ay order; owever, all must occur prior to a Active commad. Register Defiitio There are two mode registers which cotai settigs to achieve low power cosumptio. The two registers : Mode Register ad Exteded Mode Register are discussed below. Mode Register The mode register is used to defie the specific mode of operatio of the SDRAM. This defiitio icludes the selectio of a burst legth, a burst type, a CAS latecy, a operatig mode ad a write burst mode, as show i Table. The mode register is programmed via the OAD MODE REGIS TER commad ad will retai the stored iformatio util it is programmed agai or the device loses power. Mode Register bits MM2 specify the burst legth, M3 specifies the type of burst (sequetial or iterleaved), M4M6 specify the CAS latecy, M7 ad M8 specify the operatig mode, M9 specifies the width burst mode, M, M, M2 ad M3 should be set to zero. The mode register must be loaded whe all baks are idle, ad the cotroller must wait the specified time before iitiatig the subsequet operatio. Violatig either of these requiremets will result i uspecified operatio. Burst egth Read ad write accesses to the SDRAM are burst orieted. The burst legth is programmable, as show i Table 2. The burst legth determies the maximum umber of colum locatios that ca be accessed for a give READ or WRITE commad. Burst legths of,2, 4, or 8 locatios are available for both the 7

8 CMS4S32Ax 75xx sequetial ad the iterleaved burst types, ad a fullpage burst is available for the sequetial type. The fullpage burst is used i cojuctio with the BURST TERMINATE commad to geerate arbitrary burst legths. Reserved states should ot be used, as ukow operatio or icompatibility with future versios may result. Whe a READ or WRITE commad is issued, a block of colums equal to the burst legth is effectively selected. All accesses for that burst take place withi this block, meaig that the burst will wrap withi the block if a boudary is reached. The block is uiquely selected by AA8 whe the burst legth is set to two; by A2A8 whe the burst legth is set to four; ad by A3A8 whe the burst legth is set to eight. The remaiig(least sigificat) address bit(s) is (are) used to select the startig locatio withi the block. Fullpage bursts wrap withi the page if the boudary is reached. Burst Type The burst type ca be set to either Sequetial or Iterleaved by usig the M3 bit i the Mode register. The orderig of accesses withi a burst is determied by the burst legth, the burst type ad the startig colum address, as show i Table 2. [ ] Table. Mode Register Defiitio. M3 BA M2 BA M A M A M9A9 M8A8 M7A7 M6A6 M5A5 M4A4 M3A3 M2A2 MA MA Reserved(Set to ) WB Op Mode CAS atecy BT Burst egth M2 M M M3= 2 Burst egth M3= 2 M3 Burst Type Sequetial Iterleaved 4 8 Reserved Reserved 4 8 Reserved Reserved M9 Write Burst Mode Prog. Burst egth Sigle Mode Access Reserved Reserved Full Page Reserved M6 M5 M4 CAS atecy M8 M7 M6M Operatig Mode Reserved Defied Stadard Operatio All other states reserved 2 3 Reserved Reserved Reserved Reserved Note : 4. For fullpage accesses: y = For a burst legth of two, AA8 select the blockoftwo burst; A selects the startig colum withi the block. 6. For a burst legth of four, A2A8 select the blockoffour burst; AA select the startig colum withi the block. 7. For a burst legth of eight, A3A8 select the blockofeight burst; AA2 select the startig colum withi the block. 8. For a fullpage burst, the full row is selected ad AA8 select the startig colum. 9. Wheever a boudary of the block is reached withi a give sequece above, the followig access wraps withi the block.. For a burst legth of oe, AA8 select the uique colum to be accessed,ad mode register bit M3 is igored. 8

9 CMS4S32Ax 75xx Table 2. Burst egth Defiitio. Burst egth Full Page(y) Startig Colum A A A A2 A A =AA8(locatio y) Order of Accesses withi a Burst Type=Sequetial Type=Iterleaved B, B+, B+2..B, Not supported Operatig Mode The ormal operatig mode is selected by settig M7 ad M8 to zero; the other combiatios of values for M7 ad M8 are reserved for future use ad/or test modes.test modes ad reserved states should ot be used because ukow operatio or icompatibility with future versios may result. CAS atecy The CAS latecy is the delay, i clock cycles, betwee the registratio of a READ commad ad the availability of the first piece of output data. The latecy ca be set to oe, two, or three clocks. If a READ commad is registered at clock edge r, ad the latecy is q clocks, the data will be available by clock edge r + q. The s will start drivig as a result of the clock edge oe cycle earlier (r + q ), ad provided that the relevat access times are met, the data will be valid by clock edge r + q. For example, assumig that the clock cycle time is such that all relevat access times are met, if a READ commad is registered at T ad the latecy is programmed to two clocks, the s will start drivig after T ad the data will be valid by T2, as show i Figure 2. Table 3 idicates the operatig frequecies at which each CAS latecy settig ca be used. Reserved states should ot be used as ukow operatio or icompatibility with future versios may result. Write Burst Mode Whe M9=, the burst legth programmed via MM2 applies to both READ ad WRITE bursts; whe M9=, the programmed burst legth applies to READ bursts, but write accesses are siglelocatio (oburst) accesses. 9

10 CMS4S32Ax 75xx T T T2 CK Read t Z t O t AC CAS atecy= T T T2 T3 CK Read t Z t O t AC CAS atecy=2 T T T2 T3 T4 CK Read t Z t O t AC CAS atecy=3 Figure 2. CAS atecy

11 CMS4S32Ax 75xx Table 3. CAS atecy. Speed CAS atecy = Allowable Operatig Frequecy (Mz) CAS atecy = 2 CAS atecy = 3 33Mz 5 33 Mz 4 83 ETENDED MODE REGISTER The Exteded Mode Register cotrols additioal fuctios such as Partial Array Self Refresh (PASR) ad Driver Stregth (DS). The Exteded Mode Register is programmed via the Mode Register Set commad (BA=, BA=) ad retais the stored iformatio util it is programmed agai or the device loses power. The Exteded Mode Register must be programmed with M8 through M set to. The Exteded Mode Register must be loaded whe all baks are idle ad o bursts are i progress, ad the cotroller must wait the specified time iitiatig ay subsequet operatio. Violatig either of these requiremets results i uspecified operatio. AUTO TEMPERATURE COMPENSATED SEF REFRES Every cell i the DRAM requires refreshig due to the capacitor losig its charge over time. The refresh rate is depedet o temperature. At higher temperatures a capacitor loses charge quicker tha at lower temperatures, requirig the cells to be refreshed more ofte. I order to save power cosumptio, accordig to the temperature, MobileSDRAM icludes the iteral temperature sesor ad cotrol uits to cotrol the self refresh cycle automatically. PARTIA ARRAY SEF REFRES The Partial Array Self Refresh (PASR) feature allows the cotroller to select the amout of memory that will be refreshed durig SEF REFRES. The refresh optios are all baks (baks,, 2, ad 3); two baks(baks ad or 2 ad 3 by M7); ad oe bak (bak or 2 by M7). WRITE ad READ commads occur to ay bak selected durig stadard operatio, but oly the selected baks i PASR will be refreshed durig SEF REFRES. The data i the deselected bak will be lost. Driver Stregth Cotrol The driver stregth feature allows oe to reduce the drive stregth of the I/O s o the device durig low frequecy operatio. This allows systems to reduce the oise associated with the I/O s switchig. EM3 BA EM2 BA EM A EM A EM9 A9 EM8 A8 EM7 A7 EM6 A6 EM5 A5 EM4 A4 EM3 A3 EM2 A2 EM A EM A All must be set to Driver Stregth Up/Dow PASR

12 CMS4S32Ax 75xx Table 5. Exteded Mode Register Table [.2.]. A7 A2 A A Self Refresh Coverage A6 A5 Driver Stregth Four s Two s ( & ) Oe ( ) RFU RFU Four s Two s (2 & 3) Oe (2) RFU RFU Note :. EM3 ad EM2 (BA ad BA) must be, to select the Exteded Mode Register(vs. the base Mode Register). 2. RFU: Reserved for Future Use % 75% 5% 25% Table 6. s [ ]. Name(Fuctio) CKE /CS /RAS /CAS /WE M ADDR COMMAND INIBIT() NO OPERATION() ACTIVE(Select bak ad activate row) [5.] / Row READ(Select bak ad colum, ad start READ burst) [6.] / / Col WRITE(Select bak ad colum, ad start WRITE burst) [6.] / / Col Valid BURST TERMINATE Active PRECARGE(Deactivate row i bak or baks) [7.] Code AUTO REFRES or SEF REFRES(Eter Self Refresh Mode) )[8. 9.] OAD MODE REGISTER) [4.] Opcode Write Eable/Output Eable) [2.] Active Write Ihibit/Output ighz) [2.] igh Z Deep Power Dow(Eter DPD Mode) 2

13 CMS4S32Ax 75xx Note : 3. CKE is IG for all commads show except SEF REFRES ad Deep Power Dow. 4. AA provide row address, ad BA, BA determie which bak is made active. 5. AA8 provide colum address; A IG eables the auto precharge feature (opersistet), while A OW disables the auto precharge feature; BA, BA determie which bak is beig read from or writte to. 6. A OW: BA, BA determie the bak beig precharged. A IG: All baks precharged ad BA, BA are Do t Care. 7. Iteral refresh couter cotrols row addressig; all iputs ad I/Os are Do t Care except for CKE. 8. This commad is AUTO REFRES if CKE is IG, SEF REFRES if CKE is OW. 9. AA9 defie the opcode writte to the mode register ad BA, BA determie Normal MRS ad Exteded MRS. 2. Activates or deactivates the s durig WRITEs (zeroclock delay) ad READs (twoclock delay). M cotrols 7, M cotrols 85, M2 cotrols 623 ad M3 cotrols 243. s Table 6. provides a referece of all the commads available with the state of the cotrol sigals for executig a specific commad. COMMAND INIBIT The COMMAND INIBIT fuctio effectively deselects the SDRAM by prevetig ew commads from beig executed by the SDRAM, regardless of whether the CK sigal is eabled. Operatios already i progress are ot affected. NO OPERATION () The NO OPERATION () commad is used to perform a to a SDRAM which is selected (/CS is OW). This prevets uwated commads from beig registered durig idle or wait states. Operatios already i progress are ot affected. OAD MODE REGISTER The mode register is loaded via iputs AA, BA, BA. The OAD MODE REGISTER ad OAD ETENDED MODE REGISTER commads ca oly be issued whe all baks are idle, ad a subsequet executable commad caot be issued util t MRD is met. Table, Table 4 Ad Table 5 provide the defiitio for the Mode Register ad Exteded Mode Register. ACTIVE The ACTIVE commad is used to activate a row i a particular bak for a subsequet access. The value o the BA, BA iputs selects the bak, ad the address provided o iputs AA selects the row. This row remais active for accesses util a PRECARGE commad is issued to that bak. A PRECARGE commad must be issued before opeig a differet row i the same bak. READ READ commad is used to iitiate a burst read access to a active row. The value o the BA, BA iputs selects the bak, ad the address provided o iputs AA8 selects the startig colum locatio. The value o iput A determies whether or ot auto precharge is used. If auto precharge is selected, the row beig accessed will be precharged at the ed of the READ burst. If auto precharge is ot selected, the row will remai ope for subsequet accesses. Read data appears o the s subject to the logic level o the M iputs two clocks earlier. If a give M sigal was registered IG, the correspodig s will be ighz two clocks later; if the M sigal was registered OW, the s will provide valid data. WRITE The WRITE commad is used to iitiate a burst write access to a active row. The value o the BA, BA iputs selects the bak, ad the address provided o iputs AA8 selects the startig colum locatio. The value o iput A determies whether or ot auto precharge is used. If auto precharge is selected, the row beig accessed will be precharged at the ed of the WRITE burst. If auto precharge is ot selected, the row will remai ope for subsequet accesses. Iput data appearig o the s is writte to the memory array subject to the M iput logic level appearig coicidet with the data. If a give M sigal is registered OW, the correspodig data will be writte to memory; if the M sigal is registered IG, the correspodig data iputs will be igored, ad a WRITE will ot be executed to that byte/colum locatio. PRECARGE The PRECARGE commad is used to deactivate the active row i a particular bak or the active row i all baks. The bak(s) will be available for a subsequet row access after a specified time (t RP) from the issued PRECARGE commad. Iput A determies whether oe or all baks are to be precharged, ad i the case where oly oe bak is to be precharged, iputs BA, BA select the bak. Otherwise BA, BA are treated as Do t Care. Oce a bak has bee precharged, it is i the idle state ad must be activated prior to ay READ or WRITE commads beig issued to that bak. AUTO PRECARGE AUTO PRECARGE is accomplished by usig A to eable auto precharge i cojuctio with a specific READ or WRITE commad. AUTO PRECARGE thus performs the same PRECARGE commad described above, without requirig a explicit commad. A PRECARGE of the bak/row that is addressed with the READ or WRITE commad is automatically performed upo completio of the READ or WRITE burst. AUTO PRECARGE does ot apply i the full page mode burst. Auto precharge is opersistet i that it is either eabled or disabled for each idividual READ or WRITE commad. Auto precharge esures that the precharge is iitiated at the earliest valid stage withi a burst. The user must ot issue aother commad to the same bak util the precharge time (t RP) is completed. BURST TERMINATE The BURST TERMINATE commad is used to trucate either fixedlegth or fullpage bursts. The most recetly registered READ or WRITE commad prior to the BURST TERMINATE commad will be trucated. 3

14 CMS4S32Ax 75xx AUTO REFRES AUTO REFRES is used durig ormal operatio of the SDRAM. This commad is opersistet, so it must be issued each time a refresh is required. All active baks must be PRECARGED prior to issuig a AUTO REFRES commad. The AUTO REFRES commad should ot be issued util the miimum t RP has bee met after the PRECARGE commad. The addressig is geerated by the iteral refresh cotroller. The address bits thus are a Do t Care durig a AUTO REFRES commad. The Fidelix 256Mb SDRAM requires 4,96 AUTO REFRES cycles every 64ms (t REF), regardless of width optio. Providig a distributed AUTO REFRES commad every 5.625µs will meet the refresh requiremet ad esure that each row is refreshed. Alteratively, 4,96 AUTO REFRES commads ca be issued i a burst at the miimum cycle rate (t RFC), oce every 64ms. DEEP POWER DOWN Deep Power Dow Mode is a operatig mode to achieve extreme power reductio by cuttig the power of the whole memory array of the device. Data will ot be retaied oce the device eters DPD Mode. Full iitializatio is required whe the device exits from DPD Mode. [Figure 29.3] SEF REFRES The SEF REFRES commad ca be used to retai data i the SDRAM( without exteral clockig), eve if the rest of the system is powered dow. The SEF REFRES commad is iitiated like a AUTO REFRES commad except CKE is disabled (OW). Oce the SEF REFRES commad is registered, all the iputs to the SDRAM become Do t Care with the exceptio of CKE, which must remai OW. Oce self refresh mode is egaged, the SDRAM provides its ow iteral clockig, causig it to perform its ow AUTO REFRES cycles. The SDRAM must remai i self refresh mode for a miimum period equal to t RAS ad may remai i self refresh mode for a idefiite period beyod that.the procedure for exitig self refresh requires a sequece of commads. First, CK must be stable (meet the clock specificatios i the AC characteristics) prior to CKE goig back IG. Oce CKE is IG, the SDRAM must have commads issued (a miimum of two clocks) for t SR because time is required for the completio of ay iteral refresh i progress. Upo exitig the self refresh mode, AUTO REFRES commads must be issued every 5.625µs or less as both SEF REFRES ad AUTO REFRES utilize he row refresh couter. 4

15 CMS4S32Ax 75xx Maximum Ratigs Voltage o V DD/V D Supply Relative to V SS..... V to + 4.6V Voltage o Iputs, NC or I/O Pis Relative to V SS.... V to + 4.6V Storage Temperature(plastic).. 55 to + 5 Power Dissipatio.. W *Stresses greater tha those listed uder Maximum Ratigs may cause permaet damage to the device.this is a stress ratig oly, ad fuctioal operatio of the device at these or ay other coditios above those idicated i the operatioal sectios of this specificatio is ot implied. Exposure to absolute maximum ratig coditios for exteded periods may affect reliability. Operatig Rage Device Rage Ambiet Temperature V DD V D CMS4S32AxxxxS Special to +6 CMS4S32AxxxxC CMS4S32AxxxxE Commercial Exteded to to V to 3.3V.65V to V DD CMS4S32AxxxxI Idustrial 4 to +85 DC EECTRICA CARACTERISTICS AND OPERATING CONDITIONS [2.22.] Parameter / Coditio Symbol Mi Max Uits Supply Voltage V DD V I/O Supply Voltage V D V Iput igh Voltage : ogic All Iputs [23.] V I.8* V D V D +.3 V Iput ow Voltage : ogic All Iputs [23.] V I.3.3 V Data Output igh Voltage : ogic : All Iputs(.mA) V O.9* V D V Data Output ow Voltage : ogic : All Iputs(.mA) V O.2 V Iput eakage Curret : Ay Iput V=V IN=V DD (All other pis ot uder test=v) II 5 5 μa Output eakage Curret : s are disabled ; V= V OUT=V D l OZ 5 5 μa Table 7. AC OPERATING CONDITIONS [ ] Parameter / Coditio Symbol Value Uits Iput igh Voltage : ogic All Iputs V I.9* V D V Iput ow Voltage : ogic All Iputs V I.2 V Iput ad Output Measuremet Referece evel.5*v D V 5

16 CMS4S32Ax 75xx Table 8. I DD Specificatios ad Coditios [ ]. Parameter Descriptio 75 Uits I DD Operatig Curret: Active Mode; Burst =2 ; Read or Write ; t RC t RC(mi); CAS atecy =3 [ ], tck=s ma I DD2P Precharge Stadby Curret i power dow mode : CKE V I (max), tck=s.8 ma I DD2N Precharge Stadby Curret i o power dow mode : CKE V I (mi), /CS V I (mi) [ ,3.],tCK=s 24 ma I DD3P Active Stadby Curret i power dow mode; CKE V I (max) [28.29,3.3.], tck=s 6 ma I DD3N Active Stadby Curret i o power dow mode (Oe Active); CKE V I (mi), /CS V I (mi) [28.29,3.3.], tck=s 4 ma I DD4 Operatig Curret: Burst Mode: Cotiuous Burst ; Read or Write : All baks Active, CAS atecy =3 [ ], tck=s ma I DD5 Auto Refresh Curret : t RC t RC(mi), tck=s 26 ma I DD6 Self Refresh Curret : CKE.2V, 4 s, tck= Self Refresh Curret : CKE.2V, 2 s, tck= 9 7 μaμa Self Refresh Curret : CKE.2V, s, tck= 6 μa I DD7 Deep power dow, tck= 2 μa Note : 2. The miimum specificatios are used oly to idicate cycle time at which proper operatio over the full temperature rage (4 C = TA = +85 C for IT parts) is esured. 22. A iitial pause of µs is required after powerup, followed by two AUTO REFRES commads, before proper device operatio is esured. (V DD ad VD must be powered up simultaeously. VSS ad V SSQ must be at same potetial.) The two AUTO REFRES commad wakeups should be repeated ay time the t REF refresh requiremet is exceeded. 23. All states ad sequeces ot show are illegal or reserved. 24. I additio to meetig the trasitio rate specificatio, the clock ad CKE must trasit betwee VI ad V I (or betwee V I ad V I) i a mootoic maer. 25. tz defies the time at which the output achieves the ope circuit coditio; it is ot a referece to VO or VO. The last valid data elemet will meet to before goig ighz. 26. AC timig ad IDD tests have VI ad VI, with timig refereced to VI/2 = crossover poit. If the iput trasitio time is loger tha tt (MA), the the timig is refereced at VI (MA) ad VI (MIN) ad o loger at the VI/2 crossover poit. 27. IDD specificatios are tested after the device is properly iitialized. 28. IDD is depedet o output loadig ad cycle rates. Specified values are obtaied with miimum cycle time ad the outputs ope. 29. The IDD curret will icrease or decrease proportioally accordig to the amout of frequecy alteratio for the test coditio. 3. Iput sigals are chaged oe time durig 2s. 3. Uless otherwise ote, iput swig level is CMOS(V I /V I =V D /V SSQ ). 32. CKE is IG durig refresh commad period trfc (MIN) else CKE is OW. The IDD 6 limit is actually a omial value ad does ot result i a fail value Capacitace [] Parameter Descriptio Test Coditios Max Uits C IN C OUT Iput Capacitace 8 T A=25, f=mhz, V DD(typ) Output Capacitace 6 pf pf AC Test oads VD/2 OUTPUT Z=5Ω 5Ω 3pF 6

17 CMS4S32Ax 75xx AC Characteristics AC Characteristics Parameter Symbol Mi 75 Max Uits Clock Period [33.] tcks3 tcks2 7.5 s Clock igh Time tc 2.5 s Clock ow Time tc 2.5 s Setup Time to Clock tcas 2. s old Time to Clock tca. s CKE Setup Time to Clock tcks 2. s CKE old Time to Clock tck. s C=3 tac(3) 6 s [34, 35] Clock Access Time C=2 tac(2) 7 s C= tac() 2 s Output old Time from Clock to 2.5 s Data I Setup Time to Clock tcds 2. s Data I old Time to Clock tcd. s /CS, /RAS, /CAS, /WE, /M Setup Time to Clock tcms 2. s /CS, /RAS, /CAS, /WE, /M old Time to Clock tcm. s Data igh Impedace Time [25.] t Z s Active to Precharge tras 45 2 s Active to Active Period trc 7 s Active to Read/Write Delay trcd 8 s Refresh Period(496 rows) tref 64 ms Auto Refresh Period trfc 7 s Precharge Period trp 8 s Active a to Active b trrd 5 s Trasitio Time [36.] tt.5.2 s Write Recovery Time [37.] twr tck + 3s tck Exit Self Refresh to Active [38.] tsr 8 s READ/WRITE commad to READ/WRITE commad [39.] tccd tck CKE to clock disable or powerdow etry mode [4.] tcked tck CKE to clock eable or powerdow exit setup mode [4.] tped tck M to iput data delay [39.] td tck M to data mask durig WRITEs [39.] tm tck M to data highimpedace durig READs [39.] tz 2 tck WRITE commad to iput data delay [39.] tdwd tck Datai to ACTIVE commad [4.] tda 4 s Datai to PRECARGE commad [42.] tdp tck ast datai to burst STOP commad [39.] tbd tck 7

18 CMS4S32Ax 75xx AC Characteristics AC Characteristics Parameter Symbol Mi 75 Max Uits ast datai to ew READ/WRITE commad [39.] tcd tck ast datai to PRECARGE commad [42.] trd 2 tck OAD MODE REGISTER commad to ACTIVE or REFRES commad [43.] tmrd 2 tck C=3 tro(3) 3 tck Dataout to highimpedace from PRECARGE commad [4.] C=2 tro(2) 2 tck C= tro() tck Note : 33. The clock frequecy must remai costat (stable clock is defied as a sigal cyclig withi timig costraits specified for the clock pi) durig access or precharge states (READ, WRITE, icludig t WR, ad PRECARGE commads). CKE may be used to reduce the data rate. 34. tac for 33Mhz at C=3 with o load is 4.5s ad is guarateed by desig. 35. tac for 33Mhz at C=3 ad V DD of.8v is 6.5s. 36. AC characteristics assume tt = s. 37. Auto precharge mode oly. The precharge timig budget (trp) begis at 7s for 33Mhz after the first clock delay, after the last WRITE is executed. May ot exceed limit set for precharge mode. 38. CK must be toggled a miimum of two times durig this period. 39. Required clocks are specified by JEDEC fuctioality ad are ot depedet o ay timig parameter. 4. Timig actually specified by tcks; clock(s) specified as a referece oly at miimum cycle rate. 4. Timig actually specified by twr plus trp; clock(s) specified as a referece oly at miimum cycle rate. 42. Timig actually specified by twr. ( tdp is CK at Mhz or tdp is 2CK at 33Mhz ) 43. JEDEC ad PC specify three clocks. 8

19 CMS4S32Ax 75xx Operatio BANK / ROW ACTIVATION Before ay READ or WRITE commads ca be issued to a bak withi the SDRAM, a row i that bak must be opeed (activated). This is accomplished via the ACTIVE commad, which selects both the bak ad the row to be activated. A READ or WRITE commad may the be issued to that row, subject to the t RCD specificatio. t RCD (MIN) should be divided by the clock period ad rouded up to the ext whole umber to determie the earliest clock edge after the ACTIVE commad o which a READ or WRITE commad ca be etered. For example, a t RCD specificatio of 2s with a 25 Mz clock (8s period) results i 2.5 clocks, rouded to 3. (The same procedure is used to covert other specificatio limits from time uits to clock cycles.) A subsequet ACTIVE commad to a differet row i the same bak ca oly be issued after the previous active row has bee closed (precharged). The miimum time iterval betwee successive ACTIVE commads to the same bak is defied by t RC. A subsequet ACTIVE commad to aother bak ca be issued while the first bak is beig accessed, which results i a reductio of total rowaccess overhead. The miimum time iterval betwee successive ACTIVE commads to differet baks is defied by t t RRD. READs READ bursts are iitiated with a READ commad, as show i Figure 3. The startig colum ad bak addresses are provided with the READ commad, ad auto precharge is either eabled or disabled for that burst access. For the geeric READ commads used i the followig illustratios, auto precharge is disabled. Durig READ bursts, the valid dataout elemet from the startig colum address will be available followig the CAS latecy after the READ commad. Each subsequet dataout elemet will be valid by the ext positive clock edge. Figure 2. shows geeral timig for each possible CAS latecy settig. Upo completio of a burst, assumig o other commads have bee iitiated, the s will go ighz. A fullpage burst will cotiue util termiated. (The burst will wrap aroud at the ed of the page). A cotiuous flow of data ca be maitaied by havig additioal Read Burst or sigle Read. The first data elemet from the ew burst follows either the last elemet of a completed burst or the last desired data elemet of a loger burst that is beig trucated. The ew READ commad should be issued x cycles before the clock edge at which the last desired data elemet is valid, where x equals the CAS latecy mius oe. This is show i Figure 4. for CAS latecies of oe, two ad three; data elemet + 3 is either the last of a burst of four or the last desired of a loger burst. Fullspeed radom read accesses ca be performed to the same bak, as show i Figure 5., or each subsequet READ may be performed to a differet bak. Read CK CKE igh /CS /RAS /CAS /WE AA8 Colum A9, A A BA, Eable Auto Precharge Disable Auto Precharge Do t Care Figure 3. Read 9

20 CMS4S32Ax 75xx T T T2 T3 T4 T5 CK Read Read Col =cycles Col b b CAS atecy= T T T2 T3 T4 T5 T6 CK =cycles Read Read Col Col b b CAS atecy=2 Figure 4. Cosecutive Burst Reads Trasitio from Burst of 4 Read to a Sigle read for CAS atecy,2,3 2

21 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 T7 CK Read Read =2cycles Col Col b b CAS atecy=3 Figure 4. Cosecutive Burst Reads Trasitio from Burst of 4 Read to a Sigle read for CAS atecy,2,3 T T T2 T3 T4 CK Read Read Read Read Col Col a Col x Col m a x m CAS atecy= Figure 5. Radom Read Accesses for CAS atecy =,2,3 2

22 CMS4S32Ax 75xx T T T2 T3 T4 T5 CK Read Read Read Read Col Col a Col x Col m a x m CAS atecy=2 T T T2 T3 T4 T5 T6 CK Read Read Read Read Col Col a Col x Col m a x m CAS atecy=3 Figure 5. Radom Read Accesses for CAS atecy =,2,3 A Read Burst ca be termiated by a subsequet Write commad, ad data from a fixed legth READ burst may be immediately followed by data from a WRITE commad (subject to bus turaroud limitatios). The WRITE burst may be iitiated o the clock edge immediately followig the last (or last desired) data elemet from the READ burst, provided that I/O cotetio ca be avoided. I a give system desig, there may be a possibility that the device drivig the iput data will go owz before the SDRAM s go ighz. I this case, at least a siglecycle delay should occur betwee the last read data ad the WRITE commad. The M iput is used to avoid I/O cotetio, as show i Figure 6. ad Figure 7.. The M sigal must be asserted (IG) at least two clocks prior to the WRITE commad (M latecy is two clocks for output buffers) to suppress dataout from the READ. Oce the WRITE commad is registered, the s will go ighz (or remai ighz), regardless of the state of the M sigal, provided the M 22

23 CMS4S32Ax 75xx was active o the clock just prior to the WRITE commad that trucated the READ commad. The M sigal must be asserted prior to the WRITE commad (M latecy is zero clocks for iput buffers) to esure that the writte data is ot masked. Figure 6. shows the case where the clock frequecy allows for bus cotetio to be avoided without addig a cycle, ad Figure 7. shows the case with the additioal cycle. T T T2 T3 T4 CK M t CK Read Write Col Col b t Z b CAS atecy=3 t DS Figure 6. Read to Write 23

24 CMS4S32Ax 75xx T T T2 T3 T4 T5 CK M t CK Read Write Col Col b t Z CAS atecy=3 b t DS Figure 7. Read to Write with extra clock cycle T T T2 T3 T4 T5 T6 T7 T8 CK CMD Read Write Read masked by write M CMD Read Write Read masked by M M CMD M Read Write Read CAS= Figure 8. Read Iterrupted by Write with M ; CAS atecy =2 24

25 CMS4S32Ax 75xx A fixedlegth READ burst or a fullpage burst may be followed by, or trucated with, a PRECARGE commad to the same bak. The PRECARGE commad should be issued x cycles before the clock edge at which the last desired data elemet is valid, where x equals the CAS latecy mius oe. This is show i Figure 9. for each possible CAS latecy; data elemet + 3 is either the last of a burst of four or the last desired of a loger burst. Followig the PRECARGE commad, a subsequet commad to the same bak caot be issued util t RP is met. Note that part of the row precharge time is hidde durig the access of the last data elemet(s). The BURST TERMINATE commad should be issued x cycles before the clock edge at which the last desired data elemet is valid, where x equals the CAS latecy mius oe. This is show i Figure. for each possible CAS latecy; data elemet + 3 is the last desired data elemet of a loger burst. T T T2 T3 T4 T5 T6 T7 CK t RP Read Precharge Active =cycles a Col (a or all) a Row CAS atecy= T T T2 T3 T4 T5 T6 T7 CK t RP Read Precharge Active =cycles a Col (a or all) a Row CAS atecy=2 Figure 9. Read to Precharge 25

26 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 T7 CK t RP Read Precharge Active =2cycles a Col (a or all) a Row CAS atecy=3 Figure 9. Read to Precharge T T T2 T3 T4 T5 T6 T7 CK Read Burst Termiate =cycles a Col CAS atecy= Figure. Termiatig a Read Burst 26

27 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 T7 CK Read Burst Termiate =cycles a Col CAS atecy=2 T T T2 T3 T4 T5 T6 T7 CK Read Burst Termiate =2cycles a Col CAS atecy=3 Figure. Termiatig a Read Burst 27

28 CMS4S32Ax 75xx COCK CKE /CS t RC *ote 45. IG /RAS /CAS t RCD *ote 46. t RP ADDR RAa CAa RAb CAb BA BA A/AP RAa RAb t O C=2 Qa Qa Qa2 Qa3 Qb Qb Qb2 Qb3 t RAC *ote 47. t AC t Z *ote 48. t DP t O C=3 Qa Qa Qa2 Qa3 Qb Qb Qb2 Qb3 t RAC *ote 47. t AC t Z *ote 48. t DP /WE M Row Active (A) Read (A) Precharge (A) Row Active (A) Write (A) Precharge (A) Do t Care Note : 45. Miimum row cycle times is required to complete iteral DRAM operatio. 46. Row precharge ca iterrupt burst o ay cycle.[cas atecy ] umber of valid output data is available after Row precharge. ast valid output will be iz(t SZ) after the clock. 47. Access time from Row active commad. t CK *(t RCD + CAS latecy ) + t AC 48. Out put will be iz after the ed of burst. (,2,3,8 & Full page bit burst) Figure. Read & Write Cycle at egth=4, t DP = CK (Mhz) / t DP = 2CK (33Mhz) 28

29 CMS4S32Ax 75xx COCK CKE /CS t RC *ote 45. IG t RCD t RP /RAS *ote 46. /CAS ADDR RAa CAa RAb CAb BA BA A/AP RAa RAb t O C=2 Qa Qa Qa2 Qa3 Qb Qb Qb2 Qb3 t RAC *ote 47. t AC t Z *ote 48. t DP C=3 t O Qa Qa Qa2 Qa3 Qb Qb Qb2 Qb3 t RAC *ote 47. t AC t Z *ote 48. t DP /WE M Row Active (A) Read (A) Precharge (A) Row Active (A) Write (A) Do t Care Figure 2. Read & Write Cycle at egth=4, t DP= CK (Mhz) / t DP= 2CK (33Mhz) 29

30 CMS4S32Ax 75xx COCK CKE IG /CS /RAS *ote 49. /CAS ADDR RAa RBb CAa RCc CBb RDd CCc CDd BA BA A/AP RAa RBb RCc RDd C=2 QAa QAa QAa2 QBb QBb QBb2 QCc QCc QCc2 QDd QDd QDd2 C=3 QAa QAa QAa2 QBb QBb QBb2 QCc QCc QCc2 QDd QDd QDd2 /WE M Row Active (A) Read (A) Read (B) Read (C) Read (D) Precharge (D) Row Active (B) Row Active (C) Precharge (A) Precharge (B) Precharge (C) Do t Care Note : 49. Row precharge will iterrupt writig. ast data iput, t DP before Row precharge, will be writte. Figure 3. Page Read Cycle at Burst egth=4 WRITE WRITE bursts are iitiated with a WRITE commad,as show i Figure 4. The startig colum ad bak addresses are provided with the WRITE commad, ad auto precharge is 3

31 CMS4S32Ax 75xx either eabled or disabled for that access. If auto precharge is eabled, the row beig accessed is precharged at the completio of the burst. Durig WRITE bursts, the first valid datai elemet will be registered coicidet with the WRITE commad. Subsequet data elemets will be registered o each successive positive clock edge. Upo completio of a fixedlegth burst, assumig o other commads have bee iitiated, the s will remai ighz ad ay additioal iput data will be igored (see Figure 5.). A fullpage burst will cotiue util termiated. (wrap aroud at the ed of the page) A example is show i Figure 6.. Data + is either the last of a burst of two or the last desired of a loger burst. A WRITE commad ca be iitiated o ay clock cycle followig a previous WRITE commad. Fullspeed radom write accesses withi a page ca be performed to the same bak, as show i Figure 7., or each subsequet WRITE may be performed to a differet bak. Write CK CKE igh /CS /RAS /CAS /WE AA8 Colum A9, A A BA, Eable Auto Precharge Disable Auto Precharge Do t Care Figure 4. Write 3

32 CMS4S32Ax 75xx T T T2 T3 CK Write Col + Figure 5. Write Burst Burst legth of 2 T T T2 CK Write Write Col Col b + b Figure 6. Write to Write Trasitio from a burst of 2 to a sigle write Data for a fixedlegth WRITE burst a fullpage WRITE burst may be followed by, or trucated with, a PRECARGE commad to the same bak.the PRECARGE commad should be issued t WR after the clock edge at which the last desired iput data elemet is registered. The auto precharge mode requires a t WR of at least oe clock plus time, regardless of frequecy. I additio, whe trucatig a WRITE burst, the M sigal must be used to mask iput data for the clock edge prior to, ad the clock edge coicidet with, the PRECARGE commad. A example is show i Figure 9. Data + is either the last of a burst of two or the last desired of a loger burst. Followig the PRECARGE commad, a subsequet commad to the same bak caot be issued util t RP is met. 32

33 CMS4S32Ax 75xx T T T2 T3 CK Write Write Write Write Col Col a Col x Col m a x m Figure 7. Radom Write Cycles T T T2 T3 T4 T5 CK Write Read Col Col b + b b+ Figure 8. Write to Read Burst of 2 Write ad Read(CAS atecy =2) 33

34 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 CK M t CK >=5s t RP Write Precharge Active Col (a or all) a Row t WR M t CK <=5s + t RP Write Precharge Active Col (a or all) a Row t WR + Figure 9. Write to Precharge T T T2 CK Write Burst Termiate Next Col () (Data) Figure 2. Termiatig a Write Burst Fixedlegth or fullpage WRITE bursts ca be trucated with the BURST TERMINATE commad. Whe trucatig a WRITE burst, the iput data applied coicidet with the BURST TERMINATE commad will be igored. The last data writte (provided that M is OW at that time) will be the iput data applied oe clock previous to the BURST TERMINATE 34

35 CMS4S32Ax 75xx commad. This is show i Figure 2., where data is the last desired data elemet of a loger burst. PRECARGE The PRECARGE commad (see Figure 2. ) is used to deactivate the ope row i a particular bak or the ope row i all baks. The bak(s) will be available for a subsequet row access some specified time (t RP) after the PRECARGE commad is issued. Iput A determies whether oe or all baks are to be precharged, ad i the case where oly oe bak is to be precharged, iputs BA, BA select the bak. Whe all baks are to be precharged, iputs BA, BA are treated as Do t Care. Oce a bak has bee precharged, it is i the idle state ad must be activated prior to ay READ or WRITE commads beig issued to that bak. POWERDOWN Powerdow occurs if CKE is registered OW coicidet with a or COMMAND INIBIT whe o accesses are i progress. If powerdow occurs whe all baks are idle, this mode is referred to as precharge powerdow; if powerdow occurs whe there is a row active i ay bak, this mode is referred to as active powerdow. Eterig powerdow deactivates the iput ad output buffers, excludig CKE, for maximum power savigs while i stadby. The device may ot remai i the powerdow state loger tha the refresh period (64ms) sice o refresh operatios are performed i this mode. The powerdow state is exited by registerig a or COMMAND INIBIT ad CKE IG at the desired clock edge(meetig t CKS). See Figure

36 CMS4S32Ax 75xx Precharge CK CKE igh /CS /RAS /CAS /WE AA9 All baks A Selected BA, Do t Care Figure 2. Precharge 36

37 CMS4S32Ax 75xx CK t CKS >=t CKS CKE Active All baks Idle Iput buffers gated off t RCD t RAS t RC Eter Power Dow Mode Exit Power Dow Mode Figure 22. Power Dow COCK SUSPEND The clock susped mode occurs whe a colum access/ burst is i progress ad CKE is registered OW. I the clock susped mode, the iteral clock is deactivated, freezig the sychroous logic. For each positive clock edge o which CKE is sampled OW, the ext iteral positive clock edge is suspeded. Ay commad or data preset o the iput pis at the time of a suspeded iteral clock edge is igored; ay data preset o the pis remais drive; ad burstcouters are ot icremeted, as log as the clock is suspeded. (See examples i Figure 23. ad Figure 24..) Clock susped mode is exited by registerig CKE IG; the iteral clock ad related operatio will resume o the subsequet positive clock edge. BURST READ/SINGE WRITE I this mode, all WRITE commads result i the access of a sigle colum locatio (burst of oe), regardless of the programmed burst legth. The burst read/sigle write mode is etered by programmig the write burst mode bit (M9) i the mode register to a logic. READ commads access colums accordig to the programmed burst legth ad sequece. 37

38 CMS4S32Ax 75xx T T T2 T3 T4 T5 CK CKE Iteral CK Write Col + +2 Figure 23. Clock Susped Durig Write Burst 38

39 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 CK CKE Iteral CK Read Col Figure 24. Clock Susped Durig Read Burst Burst of 4 (CAS latecy =2) Cocurret Auto Precharge If a access commad with Auto Precharge is beig executed ; a access commad (either a Read or Write ) is ot allowed by SDRAM s. If this feature is allowed the the SDRAM supports Cocurret Auto Precharge. Fidelix SDRAMs support Cocurret Auto Precharge. Four cases where Cocurret Auto Precharge occurs are defied below. Read With Auto Precharge. Iterrupted by a Read(with or without auto precharge): A read to bak m will iterrupt a Read o bak, CAS latecy later. The precharge to bak will begi whe the Read to bak m is registered. (Figure 25. ) 2. Iterrupted by a Write(with or without auto precharge): A Write to bak m will iterrupt a Read o bak whe registered. M should be used two clocks prior to the Write commad to prevet bus cotetio. The Precharge to bak will begi whe the write to bak m is registered. (Figure 26. ) Write with Auto Precharge 3. Iterrupted by a Read(with or without auto precharge): A Read to bak m will iterrupt a Write o bak whe registered, with the dataout appearig CAS latecy later. The Precharge to bak will begi after t WR is met, where t WR begis whe the Read to bak m is registered. The last valid Write to bak will be datai registered oe clock prior to the Read to bak m.(figure 27. ) 4. Iterrupted by a Write ( with or without auto Precharge): A Write to bak m will iterrupt a Write o bak whe registered. The Precharge to bak will begi after t WR is met,where t WR begis whe the Write to bak m is registered. The latest valid data Write to bak will be data registered oe clock prior to a Write to bak m.( Figure 28. ) 39

40 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 T7 CK ReadAP ReadAP m Iteral States t RP t RP m Page Active Read with a Burst of 4 Iterrupt Burst, Precharge Idle m Page Active Read with Burst of 4 Precharge Col a m Col d a a+ d d+ CAS atecy=3( ) CAS atecy=3( m) Figure 25. Read with Auto Precharge Iterrupted by a Read(CAS atecy =3) T T T2 T3 T4 T5 T6 T7 CK ReadAP WriteAP m Iteral States t RP t WR m Page Active Read with a Burst of 4 Iterrupt Burst, Precharge Idle m Page Active Write with Burst of 4 Write Col a m Col d M a d d+ d+2 d+3 CAS atecy=3( ) Figure 26. Read With Auto Precharge Iterrupted by a Write(Read CAS atecy =3) 4

41 CMS4S32Ax 75xx T T T2 T3 T4 T5 T6 T7 CK WriteAP ReadAP m Iteral States t WR t RP m Page Active Write with a Burst of 4 Iterrupt Burst, Write Precharge t RP m Page Active Read with Burst of 4 Precharge Col a m Col d a a+ d d+ CAS atecy=3( m) Figure 27. Write with Auto Precharge Iterrupted by a Read(CAS atecy =3) T T T2 T3 T4 T5 T6 T7 CK WriteAP WriteAP m Iteral States Page Active Write with a Burst of 4 t WR t RP Iterrupt Burst, Write Precharge t WR m m Page Active Write with Burst of 4 Write Col a m Col d a a+ a+2 d d+ d+2 d+2 Figure 28. Write with Auto Precharge Iterrupted by a Write 4

42 CMS4S32Ax 75xx DEEP POWER DOWN MODE ENTRY The Deep Power Dow Mode is etered by havig burst termiatio commad, while CKE is low. The Deep Power Dow Mode has to be maitaied for a miimum of us. The followig diagram illustrates Deep Power Dow mode etry. CK CKE t RP Precharge All Burst Termiate Precharge If eeded Deep Power Dow Etry Figure 29. Deep Power Dow Mode Etry DEEP POWER DOWN MODE EIT SEQUENCE The Deep Power Dow Mode is exited by assertig CKE high. After the exit, the followig sequece is eeded to eter a ew commad. Maitai iput coditios for a miimum of 2us 2. Issue precharge commads for all baks of the device 3. Issue 8 or more auto refresh commads 4. Issue a mode register set commad to iitialize the mode register 5. Issue a exteded mode register set commad to iitialize the exteded mode register The followig timig diagram illustrates deep power dow exit sequece CK CKE Precharge All AREF MRS EMRS Active A Key Key a Row 2 us t RP Deep Power Dow Exit Precharge All Normal MRS Exteded MRS Row Active A Figure 3. Deep Power Dow Mode Exit 42

43 CMS4S32Ax 75xx Table 9. CKE [ ]. CKE CKE Curret State Actio Power Dow Maitai Power Dow Self Refresh Maitai Self Refresh Clock Susped Maitai Clock Susped Power Dow [54.] Self Refresh [55.] Ihibit or Ihibit or Exit Power Dow Exit Self Refresh Clock Susped [56.] Exit Clock Susped All s Idle Ihibit or Power Dow Etry All s Idle Readig or Writig Auto Refresh Valid Self Refresh Etry Clock Susped Etry See Table. Note : 5. CKE is the logic state of CKE at clock edge ; CKE was the state of CKE at the previous clock edge. 5. Curret State is the state of the SDRAM immediately prior to the clock edge. 52. is the commad registered at clock edge, ad Actio is a result of. 53. All states ad sequeces ot show are illegal or reserved. 54. Exitig power dow at clock edge will put the device i all the baks idle state i time for clock edge +(provided the t CKS is met) 55. Exitig self refresh at clock edge will put the device i all the baks idle state oce t SR is met. Ihibit or commads should be issued o ay clock edges occurig durig the t SR period. A miimum of two commads must be provided durig the tsr period. 56. After exitig clock susped at clock edge, the device will resume operatio ad recogize the ext commad at clock edge +. Table. Curret State, to [ ]. Curret State CS# RAS# CAS# WE# (Actio) Ay COMMAND INIBIT (/Cotiue previous operatio) NO OPERATION (/Cotiue previous operatio) ACTIVE (Select ad activate row) Idle AUTO REFRES [63.] OAD MODE REGISTER [63.] PRECARGE [67.] Note : 57. This table applies whe CKE was IG ad CKE is IG (see Table 9. ) ad after t SR has bee met (if the previous state was self refresh). 58. This table is bakspecific, except where oted; i.e., the curret state is for a specific bak ad the commads show are those allowed to be issued to that bak whe i that state. Exceptios are covered i the otes below. 59. Curret state defiitios: Idle: The bak has bee precharged, ad t RP has bee met. Row Active: A row i the bak has bee activated, ad t RCD has bee met. No data bursts/accesses ad o register accesses are i progress. Read: A READ burst has bee iitiated, with auto precharge disabled, ad has ot yet termiated or bee termiated. Write: A WRITE burst has bee iitiated, with auto precharge disabled, ad has ot yet termiated or bee termiated. 6. The followig states must ot be iterrupted by a commad issued to the same bak. COMMAND INIBIT or commads, or allowable commads to the other bak should be issued o ay clock edge occurrig durig these states. Allowable commads to the other bak are determied by its curret state ad Table. ad accordig to Table.. Prechargig: Starts with registratio of a PRECARGE commad ad eds whe t RP is met. Oce t RP is met, the bak will be i the idle state. Row Activatig: Starts with registratio of a ACTIVE commad ad eds whe t RCD is met. Oce t RCD is met, the bak will be i the row active state. Read w/auto Precharge Eabled: Starts with registratio of a READ commad with auto precharge eabled ad eds whe t RP has bee met. Oce t RP is met, the bak will be i the idle state. Write w/auto Precharge Eabled: Starts with registratio of a WRITE commad with auto precharge eabled ad eds whe t RP has bee met. Oce trp is met, the bak will be i the idle state. 6. The followig states must ot be iterrupted by ay executable commad; COMMAND INIBIT or commads must be applied o each positive clock edge durig these states. Refreshig: Starts with registratio of a AUTO REFRES commad ad eds whe t RC is met. Oce t RC is met, the SDRAM will be i the all baks idle state. Accessig Mode Register: Starts with registratio of a OAD MODE REGISTER commad ad eds whe t MRD has bee met. Oce t MRD is met, the SDRAM will be i the all baks idle state. Prechargig All: Starts with registratio of a PRECARGE A commad ad eds whe t RP is met. Oce trp is met, all baks will be i the idle state. 62. All states ad sequeces ot show are illegal or reserved. 63. Not bakspecific; requires that all baks are idle. 64. May or may ot be bakspecific; if all baks are to be precharged, all must be i a valid state for prechargig. 65. Not bakspecific; BURST TERMINATE affects the most recet READ or WRITE burst, regardless of bak. 66. READs or WRITEs listed i the (Actio) colum iclude READs or WRITEs with auto precharge eabled ad READs or WRITEs with auto precharge disabled. 67. Does ot affect the state of the bak ad acts as a to that bak. 43