Sequential logic implementation Implementation random logic gates and FFs programmable logic devices (PAL with FFs) Design procedure state diagrams state transition table state assignment next state functions Autumn 23 CSE37 - VIII - Sequential Logic Technology Median filter FSM emove single s between two s (output = NS3) eset I PS PS2 PS3 NS NS2 NS3 X X X X X X Autumn 23 CSE37 - VIII - Sequential Logic Technology 2
Median filter FSM (cont d) ealized using the standard procedure and individual FFs and gates I PS PS2 PS3 NS NS2 NS3 X X X X X X NS = eset (I) NS2 = eset ( PS + PS2 I ) NS3 = eset PS2 O = PS3 Autumn 23 CSE37 - VIII - Sequential Logic Technology 3 Median filter FSM (cont d) But it looks like a shift register if you look at it right eset eset Autumn 23 CSE37 - VIII - Sequential Logic Technology 4
Median filter FSM (cont d) An alternate implementation with S/ FFs eset In D S Q D S Q D S Q Out = eset S = PS2 I NS = I NS2 = PS NS3 = PS2 O = PS3 CLK The set input (S) does the median filter function by making the next state whenever the input is and PS2 is ( input to state xx) Autumn 23 CSE37 - VIII - Sequential Logic Technology 5 Implementation using PALs Programmable logic building block for sequential logic macro-cell: FF + logic D-FF two-level logic capability like PAL (e.g., 8 product terms) D Q Q Autumn 23 CSE37 - VIII - Sequential Logic Technology 6
Vending machine example (Moore PLD mapping) D D OPEN = reset'(q'n + QN' + QN + QD) = reset'(q + D + QN) = QQ CLK Q N Seq Q D Seq Open eset Com Autumn 23 CSE37 - VIII - Sequential Logic Technology 7 Vending machine (synch. Mealy PLD mapping) OPEN = reset'(qqn' + QN + QD + Q'ND + QN'D) CLK Q N Seq Q D Seq OPEN Open eset Seq Autumn 23 CSE37 - VIII - Sequential Logic Technology 8
22V PAL Combinational logic elements (SoP) Sequential logic elements (D-FFs) Up to outputs Up to FFs Up to 22 inputs Autumn 23 CSE37 - VIII - Sequential Logic Technology 9 22V PAL Macro Cell Sequential logic element + output/input selection Autumn 23 CSE37 - VIII - Sequential Logic Technology
Light Game FSM Tug of War game 7 s, 2 push buttons (L, ) ESET (6) L (5) L (4) L (3) L (2) L () () Autumn 23 CSE37 - VIII - Sequential Logic Technology Light Game FSM Verilog module Light_Game (S, LPB, PB, CLK, ESET); input LPB ; input PB ; input CLK ; input ESET; output [6:] S ; reg [6:] position; reg left; reg right; sequential logic always @(posedge CLK) begin left <= LPB; right <= PB; if (ESET) position = 7'b; else if ((position == 7'b) (position == 7'b)); else if (L) position = position << ; else if () position = position >> ; end endmodule combinational logic wire L, ; assign L = ~left && LPB; assign = ~right && PB; assign S = position; Autumn 23 CSE37 - VIII - Sequential Logic Technology 2
Example: traffic light controller A busy highway is intersected by a little used farmroad Detectors C sense the presence of cars waiting on the farmroad with no car on farmroad, light remain green in highway direction if vehicle on farmroad, highway lights go from Green to Yellow to ed, allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these are met, farm lights transition from Green to Yellow to ed, allowing highway to return to green even if farmroad vehicles are waiting, highway gets at least a set interval as green Assume you have an interval timer that generates: a short time pulse (TS) and a long time pulse (TL), in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights Autumn 23 CSE37 - VIII - Sequential Logic Technology 3 Example: traffic light controller (cont ) Highway/farm road intersection farm road car sensors highway Autumn 23 CSE37 - VIII - Sequential Logic Technology 4
Example: traffic light controller (cont ) Tabulation of inputs and outputs inputs description outputs description reset place FSM in initial state HG, HY, H assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, F assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired Tabulation of unique states some light configurations imply others state HG HY FG FY description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red) Autumn 23 CSE37 - VIII - Sequential Logic Technology 5 Example: traffic light controller (cont ) State diagram (TL C)' eset HG TL C / ST TS / ST TS' HY FY TS' TS / ST FG TL+C' / ST (TL+C')' Autumn 23 CSE37 - VIII - Sequential Logic Technology 6
Example: traffic light controller (cont ) Generate state table with symbolic states Consider state assignments output encoding similar problem to state assignment (Green =, Yellow =, ed = ) Inputs Present State Next State Outputs C TL TS ST H F HG HG Green ed HG HG Green ed HG HY Green ed HY HY Yellow ed HY FG Yellow ed FG FG ed Green FG FY ed Green FG FY ed Green FY FY ed Yellow FY HG ed Yellow SA: HG = HY = FG = FY = SA2: HG = HY = FG = FY = SA3: HG = HY = FG = FY = (one-hot) Autumn 23 CSE37 - VIII - Sequential Logic Technology 7 Logic for different state assignments SA NS = C TL' PS PS + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS NS = C TL PS' PS' + C TL' PS PS + PS' PS ST = C TL PS' PS' + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS H = PS H = PS' PS F = PS' F = PS PS SA2 NS = C TL PS' + TS' PS + C' PS' PS NS = TS PS PS' + PS' PS + TS' PS PS SA3 ST = C TL PS' + C' PS' PS + TS PS H = PS F = PS' NS3 = C' PS2 + TL PS2 + TS' PS3 NS = C TL PS + TS' PS H = PS PS' F = PS PS NS2 = TS PS + C TL' PS2 NS = C' PS + TL' PS + TS PS3 ST = C TL PS + TS PS + C' PS2 + TL PS2 + TS PS3 H = PS3 + PS2 H = PS F = PS + PS F = PS3 Autumn 23 CSE37 - VIII - Sequential Logic Technology 8
Sequential logic implementation summary Models for representing sequential circuits finite state machines and their state diagrams Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure deriving state diagram deriving state transition table assigning codes to states determining next state and output functions implementing combinational logic Implementation technologies random logic + FFs PAL with FFs (programmable logic devices PLDs) Autumn 23 CSE37 - VIII - Sequential Logic Technology 9