6.5 mω, Bi-Dirctional Battry Switch in Compact WCSP DESCRIPTION Th SiP321, SiP322, and SiP323 bidirctional switchs fatur rvrs blocking capability to isolat th battry from th systm. Th intrnal switch has an ultra-low 6.5 mω (typ at 3.3 ) on-rsistanc and oprats from a +2.3 to +5.5 input voltag rang, making th dvics idal battry-disconnct switchs for high-capacity battry applications. Th SiP321, SiP322, and SiP323 hav slw rat control, making thm idal in larg load capacitor as wll as high-currnt load switching applications. Ths dvics ar also highly fficint, consuming a mr pa (typ.) currnt in shutdown and 15 pa whil oprating. Th SiP321 and SiP323 hav an activ low nabl and th SiP322 has an activ high nabl. Thy can intrfac dirctly with a low voltag control signal. Th SiP321, SiP322, and SiP323 ar availabl in an ultra compact 12-Bump, 1.3 mm x 1.7 mm, 0.4 mm pitch WCSP packag with top sid lamination. Th dvic oprats ovr th tmpratur of -40 C to +85 C. FEATURES Bi-dirctional ON and OFF 7 A continuous currnt capability Ultra low R on, 6.5 mω (typ.) at 3.3 Wid input voltag, 2.3 to 5.5 Slw rat controlld turn on Ultra-low quiscnt currnt: 15 pa (SiP321, SiP322) EN pin with intgratd pull up or pull down rsistor Availabl in both logic high and logic low nabl options Compact 12-Bump, 1.3 mm x 1.7 mm x 0.55 mm WCSP packag Matrial catgorization: for dfinitions of complianc plas s www.vishay.com/doc?99912 APPLICATIONS Smartphons and tablts Digital still / vido camras Portabl mtrs and tst instrumnts Communication dvics with mbddd battris Portabl mdical and halthcar systms Data storag Battry bank TYPICAL APPLICATION CIRCUIT Systm Connctor Powr Input Systm Charging Block Charging Control and Rgulator Systm Powr Input Chargr Output To Battry Pack EN, EN Slw Rat Gat Driv Logic LvlShift SiP321, SiP322 Not GE1 dnots halogn-fr and RoHS-compliant MARKING Fig. 1 - Typical Application Circuit ORDERING INFORMATION PART NUMBER MARKING ENABLE ENABLE PULL RESISTOR PACKAGE TEMPERATURE SiP321DB-T1-GE1 321 Low nabl Pull Low SiP322DB-T1-GE1 322 High nabl Pull Low 12-Bump, 1.3 mm x 1.7 mm, 0.4 mm pitch SiP322DB-T5-GE1 322 High nabl Pull Low WCSP packag -40 C to +85 C SiP323DB-T1-GE1 323 Low nabl Pull High SiP321EB - - - - SiP322EB - - - Evaluation Board - SiP323EB - - - - 1 2 3 4 A B C FYWL 321 S15-0598-Rv. G, 30-Mar-15 1 Documnt Numbr: 62617
ABSOLUTE MAXIMUM RATINGS PARAMETER CONDITIONS LIMIT UNIT Rfrnc to -0.3 to +6 PA, PB Puls at 1 ms rfrnc to a -1.6 EN Rfrnc to -0.3 to +6 Maximum Continuous Switch Currnt 7 Maximum Puls Currnt 0 μs puls 15 A ESD (HBM) 8000 Oprating Tmpratur -40 to +85 Oprating Junction Tmpratur 125 C Storag Tmpratur -65 to +150 Thrmal Rsistanc (θ JA ) b 73 C/W Powr Dissipation (P D ) b, c T A = 70 C 96 mw Nots a. Ngativ currnt injction up to 300 ma. b. All bumps soldrd to 1 inch x 1 inch, 2 oz. coppr, 4 layrs PC board. c. Drat 13.7 mw/ C abov T A = 70 C. Strsss byond thos listd undr "Absolut Maximum Ratings" may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of th spcifications is not implid. Exposur to absolut maximum rating/conditions for xtndd priods may affct dvic rliability. SPECIFICATIONS TEST CONDITIONS UNLESS SPECIFIED LIMITS PARAMETER SYMBOL IN = PA / PB = 2.3 to 5.5, T A = -40 C to 85 C (Typical valus ar at PA, PB = 4.2, MIN. a TYP. b MAX. a UNIT C PA, C PB = 0.1 μf, T A = 25 C) Powr Supply Oprating oltag c PA/PB 2.3-5.5 Quiscnt Currnt I Q EN = 0 (for SiP321), EN = IN (for SiP322), no load EN = 0 (for SiP323), no load Shutdown Currnt I SHDN EN = 0 (for SiP322), EN = IN (for SiP321), no load Intrnal FET Nots a. Th algbraic convntion whrby th most ngativ valu is a minimum and th most positiv a maximum. b. Typical valus ar for DESIGN AID ONLY, not guarantd nor subjct to production tsting. c. For IN outsid this rang consult typical EN, EN thrshold curv. - 0.015 300 na - 8.2 15 μa - 0.0 300 na PA / PB = 2.3, I L = 500 ma, T A = 25 C - 8 13 On-Rsistanc R DS(on) PA / PB = 3.3, I L = 500 ma, T A = 25 C - 6.5 mω Control EN / EN Input Logic-Low oltag c IL - - 0.4 EN / EN Input Logic-High oltag c IH 1.4 - - EN / EN Pull Rsistor R EN PA / PB = 5.5, EN (or EN ) = 2.3-500 700 kω Timing Output Turn-On Dlay Tim t d(on) - 0.5 - Output Turn-On Ris Tim t r - 1 - IN = 4.2, R L = 0 Ω, C L = 0.1 μf, T A = 25 C Output Turn-Off Dlay Tim t d(off) - 2.4 - ms Output Turn-Off Fall Tim t f - 1 - S15-0598-Rv. G, 30-Mar-15 2 Documnt Numbr: 62617
BUMP CONFIGURATION 1 2 3 4 A A2 A3 A4 /EN B B1 B2 B3 B4 C C1 C2 C3 C4 Top viw (soldr bumps on bottom) Fig. 2 - WCSP12, 1.3 mm x 1.7 mm BUMP DESCRIPTION BUMP NUMBER NAME FUNCTION, B1, A3, B3, C3 PB Powr port B C1 Ground A2, B2, C2, B4, C4 PA Powr port A A4 EN / EN FUNCTIONAL BLOCK DIAGRAM Switch nabl input, activ low for SiP321 and SiP323, activ high for SiP322 Intrnal Bias Circuit Intrnal Bias Circuit EN, SiP321 EN, SiP322 Slw Rat Gat Driv Logic Lvl Shift EN, SiP321 Slw Rat Gat Driv Logic Lvl Shift SiP321, SiP322 SiP323 S15-0598-Rv. G, 30-Mar-15 3 Documnt Numbr: 62617
TYPICAL CHARACTERISTICS (intrnally rgulatd 25 C, unlss othrwis notd) - Quiscnt Currnt (na) I QPA /I QPB 0.24 0.22 0.20 SiP321, SiP322 0.18 0.16 0.14 0.12 0. 0.08 0.06 0.04 0.02 0.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 PA / PB () Fig. 3 - Quiscnt vs. Input oltag I QPA /I QPB - Quiscnt Currnt (na).00 1.00 0. SiP321, SiP322 PA / PB = 5.0 PA / PB = 2.7 0.01 Fig. 6 - Quiscnt vs. Tmpratur 16 14 EN = 0 (SiP323) 16 14 EN = 0 (SiP323) I QPA / IQPB - Quiscnt Currnt (μa) 12 8 6 4 2 I QPA /I QPB - Quiscnt Currnt (μa) 12 8 6 4 2 PA / PB = 5.0 PA / PB = 2.7 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 PA / PB () 0 Fig. 4 - Quiscnt vs. Input oltag Fig. 7 - Quiscnt vs. Tmpratur I SHDN-PA /I SHDN-PB - Shutdown Currnt (na) 0.12 0. 0.08 0.06 0.04 0.02 = PA / PB (SiP321, SiP322) EN R DS - On-Rsistanc (mω) 9 8 7 6 5 4 3 I L = 0.5 A 0.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 PA / PB () Fig. 5 - Shutdown Currnt vs. Input oltag Fig. 8 - On Rsistanc vs. Tmpratur S15-0598-Rv. G, 30-Mar-15 4 Documnt Numbr: 62617
TYPICAL CHARACTERISTICS (intrnally rgulatd 25 C, unlss othrwis notd) 1.15 I SHDN-PA /I SHDN-PB - Shutdown Currnt (na) 1 0.1 0.01 PA / PB = 4.2 PA / PB = 5 PA / PB = 2.7 R DS(norm) - Normalizd On -Rsistanc 1.1 1.05 1 T A = 25 C PA / PB = 2.7 PA / PB = 3.3 PA / PB = 4.35 PA / PB = 5 0.001 Fig. 9 - Shutdown Currnt vs.tmpratur 0.95 1 2 3 4 5 6 7 I OUT (A) Fig. 12 - Normalizd On Rsistanc vs. Load Currnt 0 9-2 R DS - On-Rsistanc (mω) 8 7 6 I L = 0.5 A I PB /I PA - Input Currnt (na) - 4-6 - 8 - - 12 5-14 PB / PA = 2.3 4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 PA / PB () Fig. - On Rsistanc vs. Input oltag - 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 PA / PB () Fig. 13 - Rvrs Blocking Currnt (I RB ) vs. Output oltag 600 1.30 R /EN - /EN Pull down / Pull up Rsistanc (kω) 580 560 540 520 500 480 460 440 420 EN = 2.3 PA / PB = 5.5 400 t r - Ris Tim (ms) 1.20 1. 1.00 0.90 C L = 0.1 μf R L = Ω 0.80 Fig. 11 - EN Pull down Rsistanc vs. Tmpratur Fig. 14 - Ris Tim vs. Tmpratur S15-0598-Rv. G, 30-Mar-15 5 Documnt Numbr: 62617
TYPICAL CHARACTERISTICS (intrnally rgulatd 25 C, unlss othrwis notd) 0.9 3.0 EN, EN - Thrshold oltag () 0.85 0.8 0.75 0.7 0.65 0.6 0.55 IH IL t d(off) - Turn-Off Dlay Tim (ms) 2.8 2.6 2.4 2.2 2.0 C L = 0.1 μf R L = Ω 0.5 2.0 3.0 4.0 5.0 6.0 PA / PB () Fig. 15 - EN, EN Thrshold oltag vs. Input oltag 1.8 Fig. 17 - Turn-off Dlay Tim vs. Tmpratur 0.7 1.2 t d(on) - Turn-On Dlay Tim (ms) 0.65 0.6 0.55 0.5 0.45 C L = 0.1 μf t f - Fall Tim (ms) 1.1 1.0 0.9 0.8 0.7 C L = 0.1 μf R L = Ω 0.4 Fig. 16 - Turn-on Dlay Tim vs. Tmpratur 0.6 Fig. 18 - Fall Tim vs. Tmpratur S15-0598-Rv. G, 30-Mar-15 6 Documnt Numbr: 62617
DETAILED DESCRIPTION Th SiP321, SiP322, and SiP323 bidirctional switchs fatur rvrs blocking capability to isolat th battry from th systm. Th intrnal switch has an ultra-low 6.5 mω (typ. at 3.3 ) on-rsistanc and oprats from a +2.3 to +5.5 input voltag rang, making th dvic idal battry-disconnct switch for high-capacity battry applications. Th parts can handl 7 A continuous currnt at both dirctions. Th SiP321, SiP322, and SiP323 hav slw rat control, making thm idal in larg load capacitor as wll as high-currnt load switching applications. Th SiP321, SiP322, and SiP323 ar availabl in an ultra compact 12-Bump, 1.3 mm x 1.7 mm, 0.4 mm pitch WCSP packag with top sid lamination. Th dvic oprats ovr th tmpratur of -40 C to +85 C. REERSE CURRENT BLOCKING Th SiP321, SiP322, and SiP323 ar bidirctional switchs that prvnt currnt flowing from ithr port to th othr whn th dvic is disabld. EN, EN INPUT SiP321 and SiP323 hav an activ-low nabl pin which can intrfac with low voltag GPIO dirctly. Th switch is on whn EN is low and off whn EN is high. Th SiP322 has an activ-high nabl pin that turns th switch on whn high and off whn low. Th SiP321 and SiP322 hav an intgratd pull down rsistor at EN pin. Th SiP323 EN pin intgrats a pull up rsistor that will automatically connctd to ithr port A or port whichvr is of highr voltag. SWITCH ON AND OFF PERFORMANCE Th SiP321, SiP322, and SiP323 hav slw rat control. This minimizs th inrush currnt and provids a soft turn on. DEICE PIN OUT Fig. 20 - Turn-Off Tim ( PA = 4.2, R L = Ω, C L = 0.1 μf) Dvic pin out is dsignd for as of layout. Currnt B1 A2 B2 A3 B3 /EN A4 B4 /EN ) C1 C2 C3 C4 Fig. 21 - Proposd Layout Fig. 19 - Turn-On Tim ( PA = 4.2, R L = Ω, C L = 0.1 μf) maintains worldwid manufacturing capability. Products may b manufacturd at on of svral qualifid locations. Rliability data for Silicon Tchnology and Packag Rliability rprsnt a composit of all qualifid locations. For rlatd documnts such as packag/tap drawings, part marking, and rliability data, s www.vishay.com/ppg?62617. S15-0598-Rv. G, 30-Mar-15 7 Documnt Numbr: 62617
Packag Information WCSP12: 12 Bumps (3 x 4, 0.4 mm pitch, 208 μm bump hight, 1.71 mm x 1.31 mm di siz) Indx Bump b FYWL ABCDE D A4 B4 C4 A3 B3 C3 A2 B2 C2 B1 C1 s s E Top iw s s Bottom iw Not 4 A Not 3 Sid iw Bump Not 2 RECOMMENDED LAND PATTERN (NSMD) MILLIMETERS (5) INCHES DIMENSION MIN. NOM. MAX. MIN. NOM. MAX. A 0.515 0.530 0.545 0.0203 0.0209 0.0215 0.183 0.208 0.233 0.0072 0.0082 0.0092 b 0.234 0.260 0.312 0.0092 0.02 0.0123 0.400 0.0157 s 0.235 0.255 0.275 0.0093 0.00 0.08 D 1.270 1.3 1.350 0.0500 0.0516 0.0531 E 1.670 1.7 1.750 0.0657 0.0673 0.0689 Nots (unlss othrwis spcifid) (1) Lasr mark on th silicon di back coatd with an poxy film. (2) Bumps ar SAC396. (3) 0.050 max. co-planarity. (4) Laminat tap thicknss is 0.022 mm. (5) Us millimtrs as th primary masurmnt. ECN: S13-25-Rv. B, 16-Dc-13 DWG: 6017 Rvision: 16-Dc-13 1 Documnt Numbr: 62592
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