Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

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1 Security Evlution of DPA Countermesures Using Dul-Ril Pre-chrge Logic Style Disuke Suzuki Minoru Seki Mitsuishi Electric Corportion, Informtion Technology R&D Center 1

2 Summry - Motivtion nd results Outline Wht is Dul-Ril Pre-chrge Logic Style? - Bsic construstion of DRP logic style - DPA countermesure using DRP (WDDL nd MDPL) Security Evlution of WDDL nd MDPL - Lekge cused y the difference in dely time etween input signls Experimentl Results using FPGA - Demonstrte the lekge of WDDL nd MDPL gte on FPGA - These results fully gree with our considertions Conclusion 2

3 Summry (1/2) How cn we design secure logic circuits? Dul-Ril Pre-chrge (DRP) Logic Style is one of the good solutions. Is DRP logic style secure without ny constrint? No. Need to lnce loding cpcitnce [7][9]. Need to lnce dely time etween input signls. (Our Work) 3

4 Summry (2/2) We evlute previously known countermesures using DRP logic style. LSI designers need to djust the dely of signls. Loding cpcitnce Dely time etween input signls WDDL[6] MDPL[9] : secure under extr constrints : secure without extr constrints 4

5 Wht is the DRP logic style?(1/4) Norml (Single-Ril) logic style Comintionl circuit input output The trnsition counts (power consumption) of the circuit depend on vlue of input dt. insecure ginst DPA 5

6 Wht is the DRP logic style?(2/4) DRP logic style input positive logic Dul-Ril Comintionl circuit output input negtive logic output pre-chrge signl The trnsition counts re fixed nd do not depend on vlue of input dt. DPA-resistnce 6

7 Wht is the DRP logic style?(3/4) Wve Dynmic Differentil Logic (WDDL) [6] WDDL-AND gte WDDL-OR gte The numer of trnsitions occurring in ll circuits during n opertion cycle is constnt without depending on the vlues of input signls. However, WDDL need extr constrints to lnce the loding cpcitnce etween two complementry wires [7][11]. 7

8 Wht is the DRP logic style?(4/4) Msked Dul-Ril Pre-chrge Logic (MDPL) [9] c c Mjority logic (MAJ) gte q q = MAJ(,,c) m m m m m m MDPL-AND gte MAJ gte c MAJ gte c m = m, m = m, q m = MAJ( m, m,m) = q q q m q m m The proposers of MDPL clim tht MDPL does not need extr constrints on the plce-nd-route. 8

9 Security Evlution of WDDL (1/7) Secure cse Ech of complementry logic gtes consumes n equl mount of power in ny time. WDDL gte AND gte Averge power wveform in AND gte OR gte Averge power wveform in OR gte 9

10 Security Evlution of WDDL (2/7) Secure cse Ech of complementry logic gtes consumes n equl mount of power in ny time. WDDL gte AND gte DPA trce OR gte 10

11 Security Evlution of WDDL (3/7) Alredy-known prolem In cse tht there is difference in loding cpcitnce etween two complementry wires WDDL gte AND gte Averge power wveform in AND gte C (AND ) C (OR ) > C (AND) OR gte C (OR ) Averge power wveform in OR gte 11

12 Security Evlution of WDDL (4/7) Alredy-known prolem In cse tht there is difference in loding cpcitnce etween two complementry wires WDDL gte AND gte C (AND ) C (OR ) > C (AND) OR gte C (OR ) DPA trce We need to lnce the loding cpcitnce with extr constrints on the plce-nd-route. 12

13 Security Evlution of WDDL (5/7) New prolem In cse tht there is difference of dely time etween input signls WDDL gte AND gte Averge power wveform in AND gte dely, > dely, OR gte phse shift Averge power wveform in OR gte 13

14 Security Evlution of WDDL (6/7) New prolem In cse tht there is difference of dely time etween input signls WDDL gte AND gte DPA trce (Differentil power wveform) dely, > dely, OR gte Dely time of input signls depends on not only plce-nd-route ut lso the numer of logic steps. 14

15 Security Evlution of WDDL (7/7) In dul-ril circuits, the numers of logic steps etween complementry signls (e.g. nd ) re equl. The difference in dely time etween complementry signls minly occurs depending on the plce-nd-route. The difference in dely time etween other signls (e.g. nd ) minly occurs depending on logic formul. WDDL gte WDDL gte 15

16 Security Evlution of MDPL (1/5) We nlyzed the trnsition timing of n MDPL gte under ll possile input dely conditions. Exmple. Phse : Evlution phse Dely Condition : dely (m) < dely ( m ) < dely ( m ) MDPL-AND gte m m m c MAJ gte q q0 m m m m c MAJ gte q q m 0 16

17 Security Evlution of MDPL (2/5) When = 0, the trnsition of q m only occurs t the timing tht m switches to 1. Exmple. = 0 Phse : Evlution phse Dely Condition : dely (m) < dely ( m ) < dely ( m ) MDPL-AND gte m m m c MAJ gte q q0 m m m m c MAJ gte q q m 0 17

18 Security Evlution of MDPL (3/5) When = 1, the trnsition of q m only occurs t the timing tht m switches to 1. Exmple. = 1 Phse : Evlution phse Dely Condition : dely (m) < dely ( m ) < dely ( m ) MDPL-AND gte m m m c MAJ gte q q0 m m m m c MAJ gte q q m 0 18

19 Security Evlution of MDPL (4/5) The lekge occurs under ny dely condition! C1: dely( m ) < dely( m ) < dely(m) C2: dely( m ) < dely(m) < dely( m ) C3: dely(m) < dely( m ) < dely( m ) 19

20 Security Evlution of MDPL (5/5) The spike polrity is fixed in ech phse. C1: dely( m ) < dely( m ) < dely(m) C2: dely( m ) < dely(m) < dely( m ) C3: dely(m) < dely( m ) < dely( m ) 20

21 Experimentl Results on FPGA (1/7) The model circuit used for our evlution 21

22 Experimentl Results using FPGA (2/7) We evlute following two setting: E1: Difference in loding cpcitnce (Comprison etween WDDL nd MDPL) We use vriety of constrints in the plce-nd-route to the circuits of WDDL nd tht of MDPL respectively. We implement ech circuit nd run DPA. We compre the otined DPA trces of WDDL nd MDPL. E2: Difference in dely time etween input signls (Reltion etween dely time nd lekge) We insert dely elements (LUTs) into the pths of input signls of MDPL gtes to stisfies the dely conditions (C1 - C3). We implement ech circuit nd run DPA. We compre DPA trces of MDPL otined from E1 nd E2. 22

23 Experimentl Results using FPGA (3/7) E1 : DPA trces of WDDL AND gtes Voltge (0.4mV/div) DPA trce (Constrint 1) DPA trce (Constrint 2) DPA trce (Constrint 3) Averge Power (x 1/20) Evlution Phse Pre-Chrge Phse Time (2.0ms/div) 250MHz smpling 23

24 Experimentl Results using FPGA (4/7) E1 : DPA trces of WDDL AND gtes Voltge (0.08mV/div) Time (2.0ms/div) 250MHz smpling 24

25 Experimentl Results using FPGA (5/7) E1 : DPA trces of MDPL AND gtes Voltge (0.4mV/div) DPA trce (Constrint 1) DPA trce (Constrint 2) DPA trce (Constrint 3) Averge Power (x 1/20) Evlution Phse Pre-Chrge Phse Time (2.0ms/div) 250MHz smpling 25

26 Experimentl Results using FPGA (6/7) E1 : DPA trces of MDPL AND gtes Voltge (0.08mV/div) Time (2.0ms/div) 250MHz smpling 26

27 Experimentl Results using FPGA (7/7) E2 : DPA trces of MDPL AND gtes Voltge (0.8mV/div) <Dely Condition C1> DPA selection function = DPA selection function = <Dely Condition C2> DPA selection function = DPA selection function = <Dely Condition C3> DPA selection function = DPA selection function = Averge Power (x 1/20) Evlution Phse Time (2.0ms/div) Pre-Chrge Phse 250MHz smpling 27

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29 Conclusion We evluted previously known countermesures using DRP logic style. LSI designers need to djust the dely of signls. Loding cpcitnce Dely time etween input signls WDDL[6] MDPL[9] : secure under extr constrints : secure without extr constrints 29

30 Thnks for Listening 30

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