100GE PCS Modeling. Oded Trainin, Hadas Yeger, Mark Gustlin. IEEE HSSG September 2007

Transcription

1 100GE PCS Modeling Oded Trainin, Hadas Yeger, Mark Gustlin IEEE HSSG September 2007

2 How Random is the PCS Data? The Proposed 100G PCS has the concept of virtual lanes A 100G stream is scrambled and then distributed and muxed to many lanes How does the distribution, muxing and skew affect the randomness of the streams? We rely on the scrambling to provide clock transitions for clock recovery, to control baseline wander etc Can t prove or disprove the randomness (at least easily?) So run some simulations 2

3 How Random is the PCS Data? Maximum run lengths Maximum burst of ones or zeros throughout the simulation Running disparity (# of ones) (# of zeros) in a 64,000bits sliding window Number of transitions within a window No of transitions in 128 bits sliding window 3

4 Model Block Diagram - Transmit * - statistics are collected at these points VL0 VL1 * Tx EM0 Input 100G scrambler * framing **** VLn * Tx EM9 Self synchronous with polynomial X 58 +X Random number is picked for seed Framing Adding sync bits and alignment words Round- Robin of 66b words between Virtual lanes Virtual lanes Configurable no of VLs Bit mux Transmit Electrical media - configurable: -number - latency per SerDes Tx Gearbox Round-Robin between electrical media and between optical lanes Optical lanes configurable: - number - latency per lane 4

5 Model Block Diagram Receive * Rx EM0 VL0 VL1 Output 100G * Rx EM9 VLn Rx Gearbox Round-Robin between optical lanes and between output electrical media Receive electrical media - configurable: - number - latency per SerDes Bit demux Virtual lanes (same no as input VLs) -Word delimiter -Word alignment -Lane muxing Verification compare output with input 5

6 Used Self synchronous Polynomial: X 58 +X (10GBASE-R) out in

7 Various Input Patterns All simulation were run with 10 transmit and receive electrical media, 4 optical and 20 Virtual lanes, and with various inputs Simulations length: 75x10 10 bits (075 second at 100Gbps) Random input data Random generated with Mersenne Twister Idle data input Repeating 0x1e All zero input All ones input Square wave patterns SW1: 0b SW2: 0b SW4: 0b SW8: 0xFF00FF00 7

8 Results: Max Run Length Random Idle All zero All ones Sw1 Sw2 Sw4 Sw8 max Tx EM 0 Tx EM Tx EM 2 Tx EM 3 30 Tx EM 4 30 Tx EM 5 30 Tx EM Tx EM 7 30 Tx EM 8 Tx EM 9 Optical Optical1 Optical 2 Optical 3 Rx EM Rx EM 1 30 Rx EM 2 Rx EM 3 Rx EM 4 Rx EM Rx EM 6 Rx EM 7 30 Rx EM 8 30 Rx EM 9 30 Maximum

9 Results: Max Run Length Maximum Run Lengths 45 Maximum Run Length Tx EM 6 Optical 3 Rx EM 2 Max Random Idle All zero All ones Sw1 Sw2 Sw4 Sw8 Input Pattern 9

10 Results: Max Running Disparity Random Idle All zero All ones Sw1 Sw2 Sw4 Sw8 max Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Optical Optical Optical Optical Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Max

11 Results: Max Running Disparity Running Disparity Running Disparity Tx EM 4 Optical1 Rx EM 1 Max Random Idle All zero All ones Sw1 Sw2 Sw4 Sw8 Input Pattern 11

12 Results: Min Running Disparity Random Idle All zero All ones Sw1 Sw2 Sw4 Sw8 min Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Tx EM Optical Optical Optical Optical Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Rx EM Min

13 Transitions in 128 bits Window Output 008 percentage idle sw1 random sw8 sw4 all one all zero sw no of transitions in window 13

14 Transitions in 128 bits Window optical and electrical media with skew * Electrical optical 006 electrical optical percentage percentage These graphs were very similar for the various input scenarios no of transitions in 128b w indow no of transitions * Skew was added only for input Electrical media Average skew is 23 bits, maximal skew is 56 bits 14

15 Stage 2 - Long Simulation, Setup A Simulations length: bits, 10 seconds 10 input and output Electrical media, 4 optical Skew: None in electrical media Max skew in optical: 5 bits (latencies in bit-time: 1, 2, 4, 6) Input scenarios: Random input All ones input All ones input, scrambler seed randomized every 6x10 6 bits (every 60µs, total times) 15

16 Random Input (128b window) Tx EM 0 Tx EM 1 Max run length Min running disparity Max running disparity Electrical media Tx EM 2 Tx EM 3 Tx EM 4 Tx EM Tx EM optical media scrambler Tx EM 7 Tx EM 8 Tx EM 9 Optical Optical1 Optical Optical Rx EM Rx EM Rx EM 2 Rx EM Rx EM Rx EM Rx EM Rx EM 7 Rx EM Rx EM Max (min) (-15)

17 All Ones Input (128b window) Tx EM 0 Tx EM 1 Max run length 39 Min running disparity Max running disparity Electrical media scrambler Tx EM 2 Tx EM 3 Tx EM 4 Tx EM optical media Tx EM 6 Tx EM 7 Tx EM 8 Tx EM Optical Optical1 Optical Optical 3 Rx EM Rx EM Rx EM 2 Rx EM Rx EM 4 Rx EM Rx EM Rx EM Rx EM Rx EM Max (min) (-1460)

18 Stage 3 - Long Simulation, Setup B Simulations length: bits, 10 seconds 4 transmit and receive electrical media, 2 optical Skew: Possible future evolution None in electrical media Skew in optical: 7 bits (latencies in bit-time: 1, 8) Input scenarios: Random input All ones input 18

19 Random Input Electrical Max run length Min running disparity Max running disparity Tx EM Tx EM 1 Tx EM Tx EM 3 Optical 0 Optical1 Rx EM 0 Rx EM 1 Rx EM 2 Rx EM InEM0 Optic0 OutEM Optic Max (min) (-1602)

20 All Ones Input Electrical Max run length Min running disparity Max running disparity Tx EM Tx EM Tx EM Tx EM 3 Optical Optical1 InEM Rx EM 0 Rx EM 1 Rx EM 2 Optical1 OutEM Rx EM Optic Max (min) (-1446)

21 Conclusion The multiplexing of the Universal PCS has a negligible effect on the scrambler properties for the various data paths 21