Thyristor Based HVDC with Forced Commutation

Transcription

1 1 Thyristor Based HVDC with Fored Commutation D. Jovi, Member IEEE Abstrat This paper presents a novel onverter onfiguration, based solely on onventional thyristors and aimed for the use with High Voltage DC (HVDC) Transmission. The onverter utilizes resonant turn off and fored ommutation with auxiliary thyristors to aid ommutation in the onverter swithes. The PSCAD/EMTDC simulation onfirms that the HVDC inverter is apable of operating with a wide range of firing angles, inluding operation with reative power export. Further simulation proves that the system is immune to ommutation failure even in the ase of most severe lose single-phase faults. The harmoni generation is omparable to the onventional onverter and also the thyristor voltage stress is not signifiantly inreased. The auxiliary thyristors do inrease osts, but this is offset by the elimination of reative power support and the improvements in performane. Index Terms HVDC transmission, HVDC onverters, ommutated iruits, reative power. I. INTRODUCTION HVDC has found many appliations in ountries worldwide sine the first installation in There are however well known limitations that have hampered further proliferation of onventional HVDC transmission [1]: The need for reative power support and in partiular variable reative support whih inreases osts. Even modest (around 1%) voltage derease at the inverter AC terminals will ause ommutation failure. Commutation failure auses a short-iruit on DC voltage and thus power transfer is interrupted. The inability to operate with weak inverter AC systems, whih is indiretly aused by poor ontrol apabilities at the inverter side and the above two issues. Reently, HVDC transmission based on Voltage Soure Converters has been introdued and some medium-power systems have been installed [2]. VSC Transmission has none of the above issues with onventional HVDC, however other notable limitations are present: The rating of the onverters is limited, presently to around 36MW. The losses are notieably higher than with onventional HVDC, aused primarily by the inreased swithing losses. The ost of this tehnology is high. In parallel with the developments in VSC transmission, there has been a stream of researh on improving D. Jovi is with Department of Engineering, University of Aberdeen, Aberdeen, AB24 3UE, UK d.jovi@abdn.a.uk onventional, thyristor based, HVDC. In partiular the onept of Capaitor Commutated Converters (CCC) has shown promising results [3-7]. The researhers in [3] have onluded that only series apaitor onfiguration might be of pratial importane for improving ommutation in HVDC onverters. The CCC tehnology was further investigated and improved in a series of projets [4-7] and reently it has been installed in a pratial bak-to-bak HVDC at Garabi station Brasil. [8]. The CCC onept offers HVDC onverters that ould operate at an improved power fator and with redued ommutation failure probability. However the following issues with CCC HVDC have been identified: The ourrene of ferromagneti resonane [7]. Researh shows that this an be resolved using thyristor ontrolled apaitors or advaned feedbak ontrol [5,7], but at the inreased osts. Typially CCC ahieves around 1-15% reative power onsumption. In order to operate with a leading power fator, and to ompletely eliminate ommutation failure, very large series apaitors would be needed. This inreases voltage stress, harmonis and osts. The inreased voltage stress on thyristors, whih an be 2 p.u. or even 3p.u with very large apaitors, The insulation of series ommutating apaitors, The harmoni generation is somewhat inreased, and in partiular DC harmonis are signifiantly larger. It is lear that there is inentive and the sope for further development of HVDC transmission and that the potential benefits are signifiant. Ideally, the researh on HVDC onverters would improve HVDC tehnology: To operate at higher firing angles enabling reative power export, To eliminate ommutation failure issues, if possible inluding most severe single-phase faults, Not to signifiantly inrease harmoni pollution, or thyristor voltage stress or osts. In this paper, a new HVDC onverter that potentially meets the above goals is studied. The onept is based on ombining fored ommutation and the resonant turn off methods. The basi priniples of these tehniques are known sine they have been used with some low power DC-DC hoppers [9-11], although suh tehniques have not been employed in high power, three-phase iruits. The paper will further give detailed analysis of operation and the method of alulating optimum parameters. A wide range of PSCAD/EMTDC simulation results will be presented to evaluate performane of the new sheme in terms of: reative power exhange, ommutation failure resiliene, harmoni generation and stability aspets.

2 2 II. CIRCUIT DESCRIPTION Figure 1 shows the proposed onverter and the AC system at the inverter side of an HVDC. There are two six-pulse bridges in Y and transformer onnetions. Thyristors TY1- TY6 and T 1-T 6 are the main thyristors in the onventional Graetz onnetion. Eah main thyristor has one auxiliary thyristor to aid ommutation (TY1a-TY6a and T 1a-T 6a). There are also three ommutating apaitors and a single resonant apaitor Cs (per 6-pulse bridge). The omplete HVDC test system is based on the CIGRE HVDC Benhmark model and all parameters an be found in [12]. This is a monopolar 12-pulse HVDC system with 1MW, 5kV, A rating, and with weak AC systems at both ends. It is desired to keep the test systems as lose as possible to the original CIGRE model, to enable omparisons. Some minor modifiations are made, however. Sine the new onverters enable zero reative power exhange, implying higher AC voltage, the reative power support apaitors are removed, and also the transformer ratio is hanged. In this way the same DC voltage level is ahieved, the same power transfer and with a similar AC voltage level. The remaining iruit inluding the filters is idential to that in CIGRE Benhmark model. The swithable load z load is added in some tests to simulate large disturbanes. All the standard labeling for HVDC variables is used [1]. III. RESONANT TURN-OFF FOR HVDC Some onverters in low power appliations use resonant turn-of priniple to enable low urrents and voltages at swithing instants. As a result, thyristor swithing stresses are lower implying less heating and losses [9,1]. This method has not been used in high power appliations primarily beause large osillations (resonant onditions) would not be aeptable to the omponents. However, with 12-pulse HVDC the 6-pulse bridge osillation may be indued in suh way to enable anellation between Y and groups. With HVDC onverters eah thyristor onduts for 12deg intervals, one per yle. In order to have the minimum urrent at the end of eah thyristor ondution interval, the frequeny of the osillations f should be triple multiple of the fundamental frequeny. Considering further an osillatory iruit on any phase, where two thyristors are involved, the ondition for frequeny of osillations is: f = n 6 f, f = 5Hz, n = 1,2,... (1) The seond ondition is that the osillations mutually anel in a 12-pulse onfiguration. Sine the Y and thyristor groups are displaed by 3deg, their osillations ould be anelled if half the period is a multiple of (1/f)2π/12. This ondition is same as that that in (1) and therefore the final formula for frequeny in the resonant iruit is (1). The resonant ondition is reated on eah 6-pulse bridge between the transformer impedane Ltr and the resonant apaitors Cs. The value for the apaitane is alulated from the resonant frequeny for a LC iruit: C s 1 = (2) L tr ( 2πf ) 2 I d Ls V d Cs V TY 2 TY2a I TY2a I TY2 I TY2 I TY6a TY6 TY4a TY4 a b Y Ltr V TY5 TY3 TY1 V TY5a TY3a TY1a fault V d2 Cs T 2a T 2 T 6a T 6 T 4a T 4 a b Ltr a b V ainv P inv, T 5 T 3 T 1 z f Q inv CB l z load T 5a T 3a T 1a z inv P load, Q load Figure 1. The proposed inverter onverters and the AC system onfiguration.

3 3 Assuming that n=1, and using the transformer impedane value Xtr=18%, (Ltr=.512H) as given in the PSCAD tutorial model, the apaitane is alulated as Cs=5.5µF. This is a theoretial value assuming ideal LC resonant iruit. By observing the harmoni level during PSCAD simulations, it was found that the best value is lower, around Cs=4.5µF. Note that the resonant iruit is also affeted by impedane of the inverter AC system and other parameters, but this influene is not signifiant, as it will be shown in the simulation setion. A remark is also made that there is no benefit in seleting larger n in (1), sine at larger frequenies the osillations are more attenuated and the urrent minima are higher. Higher swithing urrent implies higher harmonis. Figure 2 shows traes of the variables (PSCAD simulation) in the resonant iruit. In Figure 2a) we see that the AC urrent has two full yles in eah 12deg interval and it is at its minimum (almost zero) at the instant of ommutation. The DC urrent has no osillations beause of the Y- anellation. In Figure 2b) it is observed that eah 6-pulse group has large osillations on the DC voltage but the main DC voltage is unaffeted by these osillations and the profile is similar to the onventional inverter iruit. This is important onlusion sine DC able insulation is normally vulnerable to AC urrents. It should be noted that the simulation in Figure 2 uses the final iruit, i.e. it also inludes the fored ommutation iruit presented in Setion IV (hene distortion at the end of ondution). Figure 3 shows the benefits of the resonant turn-off iruit by omparing with the onventional inverter. In this figure, the inverter firing angle (α) is gradually inreased from 145deg to 18deg. With the onventional inverter the ommutation failure ours below 15deg beause of the large ommutation overlap and the lak of suffiient ommutation margin. With the resonant iruit, better responses are observed. As a onsequene of smaller thyristor swithing urrents, the ommutation overlap is smaller, and smaller ommutation margin an be allowed. The ommutation failure ours at larger angles, lose to 18deg. Current [ka] 4. I I T4I 3. DC I T I C a) Currents b) Voltages V d V Time [s] time [s] V d2 Figure 2. The resonant turn off priniple. A) DC and valve side AC Currents, b) DC voltages and ommutating apaitor voltages. Harmonis [% of fund] THD Conventional Inv. Commutation failure THD Alpha inv Commutation failure Figure 3. Variation in THD, Gamma and Inverter power as Alpha at inverter inreases. Case with only resonant apaitors. Note that these results are appliable only at steady state, and beause of the presene of disturbanes in the atual iruit muh larger pratial margins should be allowed. As seen in Figure 3, the Total Harmoni Distortion (THD) on the AC voltage is somewhat inreased with the resonant iruit. Sine the resonant iruit gives only limited improvement in performane, an additional fored ommutation iruit is inluded. IV. FORCED COMMUTATION A. Priniples of operation There are a number of fored ommutation iruits for onventional thyristors [9,11]. In pratie they have been primarily used at very low-power, low-ost iruits and with DC-DC onverters. The main issue with fored ommutation is the ost of additional thyristors and the inrease in harmoni pollution. Nevertheless, with HVDC appliations, the additional ost might be offset by the savings in the reative power supply and signifiant improvement in the performane like stability and the resiliene to ommutation failures. The fored ommutation iruit shown in Figure 1 is found to be most suitable for HVDC appliations. The priniple of operation is explained with referene to Figure 4, and onsidering the ommutation from valve TY2 to TY4. Figure 4a) shows the iruit onfiguration at the instant of ending TY2 ondution and losing TY2a. Prior to this ommutation it is assumed that the ommutating apaitor is harged to the polarity as shown. At the same instant of firing T4, the auxiliary thyristor TY2a is also fired and this brings the V aross the thyristor TY2, implying that athode of TY2 beomes positive. Sine the apaitor brings the highest positive voltage at phase, the apaitor will take over the load urrent. Consequently, urrent through TY2 redues to zero and assuming that it stays zero for at least the interval equal to the extintion period, thyristor TY2 regains bloking state. In a short time apaitor hanges polarity, reduing the apaitor urrent. At this stage, Thyristor TY4 takes over the load urrent and ommutation is omplete. At the end of ommutation, apaitor is harged to the reverse polarity as shown in Figure 4b). It is now ready to assist ommutation of thyristor TY5. The instant of turning off TY5 (i.e starting of ondution in TY1) is shown in Figure 4b). Figure 5 shows the firing sequene for the main thyristors Alpha [deg]

4 4 I d Ls - Cs TY2a - TY5a TY5 TY2 I I d Ls - Cs TY2a - TY5a TY5 TY2 a) Ciruit at the instant of b) Ciruit at the instant of losing TY2a losing TY5a Figure 4. The fored ommutation. a) Swithing TY2a to turn off TY2, b) Swithing TY5a to turn off TY5. Gate pulses Phase C Phase B Phase A TY6 TY5a TY1 TY2 TY6a TY3 TY1a TY2a TY4 TY5 TY3a TY4a ωt [deg] Figure 5 Firing sequene for the main and the auxiliary thyristors. and the auxiliary thyristors. The ondution intervals for the main thyristors are shown shaded. The pulses for the auxiliary thyristors are supplied at the firing instant of the next thyristor on the same half bridge. The auxiliary thyristors ondut for short periods, usually 1-15deg. Figure 6 shows the atual urrents and voltages during the ommutation from TY2 to TY4. In Figure 6a) it is seen that the urrent in the outgoing thyristor TY2 is rapidly brought to zero when the auxiliary thyristor TY2a fires. This implies that there is no ommutation overlap in the proposed onverter. Note that ommutation overlap in onventional onverters is usually 15-25deg [1], whih deteriorates power fator. It is also seen in Figure 6a) and 2a) that the urrent in the auxiliary thyristors is small, and the RMS value is alulated to around 12% of the RMS urrent of the main thyristors. Considering that the voltage aross the ommutating thyristors is similar to the main thyristors, the ommutating thyristors will have below 1/8 of the power rating of main thyristors. In Figure 6b) we observe that the voltage aross the main thyristors (Vt2) reverses during the ommutation, as the result of the onnetion of ommutating apaitors, and this enables thyristor turn-off. The additional benefit is that this reverse voltage will also aelerate regrouping of harges on p-n juntion and it will shorten the thyristor extintion time [9,1]. To appreiate the benefit of the proposed onverter, it is emphasized that the ommutating apaitors are harged from the DC voltage. If the DC voltage is at a required level, the apaitors will be harged enabling ommutation of the main thyristors, regardless of the atual AC voltage levels. The ommutating voltage is therefore provided from the DC side, rather than from the AC side as in onventional inverters. I I T2 I =I T I =I I DC T Y2a firing I T Y4 firing I T4.5. T Y2 turn off T Y2a turn off -.5. a) urrents Current [ka] 5 4 V d V T2 V - V b) Voltages time [s] Figure 6. Fored ommutation between TY2 and TY4, a) orresponding urrents, b) orresponding voltages. This is very important for HVDC appliations sine DC faults are rare, whereas AC faults more frequent. B. Sizing of ommutating apaitors The size of the ommutating apaitors is determined onsidering the required performane. Theoretially, ommutating apaitors should be large enough to store energy required to sustain the load urrent for the interval larger than the extintion time of thyristors Te. As seen in Figure 2b), the voltage on ommutating apaitors hanges polarity at eah ommutation, but only the first half of the voltage hange interval enables reverse voltage aross main thyristors. A simplified alulation for the apaitor is [11]: dv = idt (3) dt 1 t2 = idt V V (4) t1 ( ) 2 1 where the apaitor voltage hanges from V 1 to V 2, in the interval t 2 -t 1 assuming the apaitor urrent is i. The time interval for apaitor voltage reversal is: t t = 2( T e T ) (5) 2 1 m where T e is the extintion time, and T m is the ommutating margin in seonds. The extintion time for high-power thyristors varies widely with the power rating, the iruit onditions, the manufaturer and type, and in general it is between few tens of miroseonds and several hundreds of miroseonds [1]. Sine the fored ommutation introdues fast voltage reversal aross thyristors, the extintion time will be smaller than with onventional inverters and it is initially taken as T e =µs. The additional margin for safe ommutation T m, is required to enable thyristors ahieving bloking state even under disturbanes when urrent might inreases or DC voltages redues, and simulation tests indiate

5 5 that around 1-1.5deg is adequate. This is signifiant improvement sine in onventional inverters the ommutation margin is usually over 1deg. The total interval for the voltage V reversal is therefore taken as (t 2 -t 1 )=5µs. The hange in apaitor voltage is lose to twie the 6-pulse bridge DC voltage, and it an be taken as approximately (V 2 - V 1 )=4kV. The apaitor urrent I is assumed as: I = I I sin( 6ω t), (6) m o o where: Io=1.7kA - the peak urrent, Im=2kA the DC urrent, ω o =314.15rad/s, - the fundamental frequeny. Replaing (6) in (4) we obtain the formula for apaitor : 2π Io os( π ( t2 t1) ) os( π) Im t t = 1/3 ( 2 1) (7) V 6ω V The required apaitor value is initially alulated as =3.4µF. The final value for the apaitane is determined using simulation testing. By reduing the value of ommutating apaitors the harmonis are redued, but too low value would jeopardize safe ommutation during faults. A series of test is performed by varying the apaitor size and onsidering a range of values for the extintion time (5<Te<3µs). The following observations are made: The harmoni level on AC and DC voltage (individual harmonis and total harmoni distortion (THD)) The inidene of ommutation failure during single and three-phase faults, and urrent step hanges. In the ommutation failure tests, the value of the inverter firing angle is limited to 19deg and the most severe zeroimpedane single-phase faults at the inverter terminal are applied. The apaitor value that enables operation without ommutation failure is reorded. The summary of these results is shown in Figure 7. The test results show that, as an example, seleting =4.µF, the onverter an operate with no ommutation failure if the thyristor extintion time is µs. Note that this system would be able to operate with larger extintion angles at steady-state but the ommutation failure would our if the voltage on a single phase drops to some low values. The Figure also shows the THD level assuming operation at zero reative power exhange. It is seen that total harmoni level is higher but it is of the same order of magnitude as with equivalent onventional inverter. Table 1 speifies further the values of individual harmonis. We an onlude that the filtering osts would not be signifiantly inreased. Furthermore, the DC side harmonis are lower beause of the additional apaitors. The overall harmoni generation would be similar or better than with CCC HVDC. The low THD level might be surprising onsidering the additional spikes introdued by the ommutating thyristors, but the following design aspets redue harmonis: The proposed onverter operates at firing angles loser to 18deg where the harmoni generation is lowest beause of small differene between phase voltages. Conventional inverters operate around 14deg. There is no ommutation overlap beause of the fast turn-off of the thyristors. Conventional inverters have ommutation overlap of 15-25deg, whih deteriorate voltage profile. Analysing the results in Figure 7, the system with =4.µF is seleted as the base model for all further tests, sine it has good overall performane. With this system the maximum extintion time should be below µs to enable operation without ommutation failure under most sever faults. The system is apable of operating at high firing angles orresponding to around 5MVar reative power export. THD Extintion time THD onventional inverter Figure 7. The AC voltage total harmoni distortion [THD] and the maximum extintion time as the funtion of the ommutating apaitane. TABLE 1. INDIVIDUAL HARMONICS AS THE FUNCTION OF COMMUTATING CAPACITOR SIZE. Harm. [%].22µF 1.2µF 4µF 1µF Conv. Invert. 5 th AC side th AC side th AC side th AC side THD AC volt th DC side th DC side C. The operating parameters The results for the harmoni level in Figure 7 are obtained by assuming steady-state operation at around neutral reative power exhange. As with onventional onverters, the harmoni level will hange as the operating point hanges. In Figure 8, the inverter firing angle is inreased in the interval deg, while keeping the inverter AC voltage onstant (an AVR is used at the AC soure). The operating point at approximately 2.65s (with around 165deg angle) orresponds to the results in Figure 7. Note that the neutral reative power exhange is ahieved at around 165deg sine the series onneted ommutating apaitors ontribute to the additional reative power generation. Also, over 5Mvar is exported at 19deg as seen in Figure 8b. We observe in Figure 8a) that the harmonis are minimal around 165deg and they inrease with the inrease or derease of the firing angle. As an example if 3MVar is exported the harmoni level would be 3 times that with onventional inverter. It is presumed that suh system would be normally

6 6 operated around neutral reative power exhange and only transient variations in a ertain firing angle range would be allowed. If a permanent operation at a wide range of firing angles is adopted, filtering would be more demanding and adaptive/ative filtering might be needed. The system already has a set of filters and therefore the results serve for relative omparison with onventional inverters. Note also that the DC voltage level follows the os(α) relationship and therefore the ative power redues on either side of the 18deg operating point, as seen in Figure 8b). Harmonis [% of fund] th 12thDC THD Alpha inv a) Harmoni level and inverter firing angle Power [MW], [MVar] 5th 11th 7th Q-inv P-inv b) Inverter power Time [s] Figure 8. Variation in harmonis level and power with the inrease in inverter alpha 16-19deg. V. DYNAMIC STUDY The proposed inverter inludes the resonant apaitors Cs, and also the ommutating apaitors, that influene dynamis at the system level. Also, there is no ommutation overlap, implying very low ommutating resistane R=6fL tr [1], whih is assumed zero. A redution in the ommutating resistane has negative influene on the stability [1,14]. The inverter ontroller gain also hanges beause of the different operating point. On the positive side, the proposed onverter has no ommutation failure issues, therefore the inverter firing angle an be varied in a wide range, and this implies possibility for versatile large-gain inverter feedbak ontrol. The HVDC-HVAC, MATLAB-based, small-signal analytial model [13] is used to study stability of the proposed onverter. A simplified model is developed assuming that only the DC side apaitane and the ommutating reatane is hanging. Table 1 shows the loation of most dominant eigenvalues, assuming onstant firing angle operation (no ative ontrol) at the inverter onverter. It is seen that with fored ommutation the eigenvalue real parts are smaller, and stability is slightly degraded as expeted. The system stability an be improved if a feedbak ontroller at the inverter side is used, like AC voltage or Alpha [deg] reative power regulation, although this is not ommon in HVDC. The proposed inverter ontroller struture is shown in Figure 9, where the gains are obtained using model in [13] and they are given in the Appendix. The ontroller onsists of two independent units: the low-gain AC voltage PI ontroller and the fast stabilizing feedbak loop. The stabilizing feedbak loop is based on the AC urrent angle feedbak, sine this signal was found to be most benefiial in improving stability of HVDC systems [14]. Assuming that the AC voltage is lose to the nominal value suh system will operate with the inverter firing angle around 165deg. During fast disturbane the stabilizing ontroller (whih has high gain) will have dominant influene. If the AC voltage hanges, the slowating AC voltage PI ontroller will modify the firing angle thus hanging the reative power injetion in order to return the voltage to nominal level. TABLE 2 LOCATION OF DOMINANT EIGENVALUES Conventional inverter With fored ommutation -38.6±433.7j -32±435.2j -19.6±633.4j ±632j -19.3±217.5j -69.7±215.1j -19.6±9.5j -3.96±5.18j ±4.67j -8.1 V ainvref V ainv - 1/(Tis1) Θ ai kv Kvi/s 145 Θ ai 1/(Tis1) k a Stabilising feedbak loop - AC urrent angle Figure 9. Inverter ontroller. VI. SIMULATION RESULTS 194 α inv This setion presents the PSCAD/EMTDC simulation of HVDC with the proposed onverter iruit. The extintion time for all thyristors is set to µs, and a low simulation step (1µs) is used to improve auray. Figure 1 shows the eletrial and ontrol variables following a.5s zero-impedane single phase fault at the inverter terminal. Phase A voltage redues to zero during the fault, but as it is seen in Figure 1) DC voltage remains positive and there is no ommutation failure. For omparison, the onventional onverter response is also shown, and it is evident that ommutation failure is present beause of the short iruit on the DC voltage. The extintion angle shows transient dip but it returns to the nominal value of around 5deg as seen in Figure 1b). Figure 1d) shows the power, where it is evident that the new onverter shows muh better power delivery during the fault. Figure 11 shows simulation of a.1s three-phase lowimpedane fault at the inverter terminal. It is evident that there is no ommutation failure and that the responses are muh better than with the onventional onverter. The simulation with a weak AC system, in Figure 12, is also given sine HVDC normally have diffiulties when inverter AC system has low Short Ciruit Ratio (SCR) (say

7 7 SCR<2) [1]. The inverter AC impedane (z a in Figure 1) is modified to represent a iruit with SCR=1.2, at 75deg. The onsidered system is therefore extremely weak, at the margin of AC transfer apability, and an HVDC with onventional onverters would not be able to maintain stable operation. At.1s an additional large load (4MW, MVAR) is onneted to the inverter AC bus (as shown in Figure 1). Finally at.9s a low-impedane single phase fault is applied. The purpose of this test is to demonstrate that the AC iruit parameter hanges an not affet the proposed onverter to a degree that jeopardize stable operation. Note that minimal hange in the resonant iruit frequeny does our but the normal operation is maintained. It is onluded that the proposed onverter is suitable for very weak AC systems and that omplete resiliene to ommutation failure is maintained. Gamma [deg] Vinva Vinvb Vinv a) AC voltages Inverter firing angle Gamma Y Gamma D b) Inverter Gamma and Alpha DC ) DC voltage and DC urrent Power [MW, MVAr] d) Power Vd Id Vd - Conventional Inv Alpha [deg] DC urrent [ka] time [s] Q inv P - Inv Conventional Inv. P inv Figure 1. System response after a.5s zero impedane single-phase fault at inverter AC terminal. In this Figure the apability of fast regulation of AC voltage using HVDC onverters is also demonstrated. In this aspet, the proposed onept an be ompared with VSC based HVDC transmission. To enable full omparison with the onventional onverters, the voltage aross main thyristors during steady-state operation is analysed as shown in Figure 13. It is evident that there is only 3-4% inrease in the peak forward bloking level. Contrasting further this onverter against onventional inverters it is mentioned that reliability is degraded beause of the inreased number of omponents Vinva Vinvb Vinv a) AC voltages DC Vd Vd - Conventional Inv b) DC voltage Power [MW, MVAr] ) Power AC Q inv P inv Conventional Inv. P inv d) Inverter AC voltage Vainv 19 Vainv Conventional Inv Alpha inv time [s] Figure 11. System response after a.1s low impedane three-phase fault at inverter AC terminal. aplpha [deg]

8 8 Power [MW, MVAr] Q load P inv P load Q inv a) Inverter power and load power AC Vainv Alpha inv b) AC voltage and Inverter alpha Time [s] Figure 12. Simulation results with very weak inverter AC system (SCR=1.2). At.1s, a 4MW, MVAr load, is onneted, and at.9s there is a zero impedane single phase fault Vt2 Vt2 - onventional aplpha [deg] Time [s] Swith on Vt2 Figure 13. Comparison of voltage stress aross main thyristors. VII. CONCLUSIONS Swith on Vt2 This paper proposes a onverter for HVDC systems, whih is based solely on onventional thyristors, and is apable of operating with firing angles that provide leading power fator. It enables HVDC to have wide range of reative power exhange in exporting and importing region. For the minimal harmoni generation the operating point should be linked with the neutral reative power exhange, whih is lose to 165deg in the proposed iruit. The HVDC system with suh onverters will have approximately 5% inreased harmoni ontent and slightly inreased thyristor voltage stress ompared with onventional onverters. The PSCAD/EMTDC simulation with µs thyristor extintion time is used to test the proposed onverter. The results demonstrate that even for zero impedane single-phase faults at the inverter AC bus, ommutation failure will not our. The tests with very weak AC systems onfirm good operation and unhanged resiliene to ommuniation failure. Considering the auxiliary thyristors and apaitors, the proposed onverter will have higher osts and redued reliability ompared with onventional onverters. However signifiant ost savings are also introdued beause of the elimination of reative power support, downsizing of onverter transformers and the muh-improved performane. VIII. REFERENCES [1] P. Kundur: Power System Stability and Control MGraw Hill [2] Kjell Erisson "Operational Experiene of HVDC Light" Seventh International Conferene on AC-DC Power Transmission IEE. 1, pp London, UK [3] J. Reeve, J.A. Baron, G.A. Hanley, Tehnial assessment of Artifiial Commutation of HVDC Converters With Series Capaitors IEEE Transations on Power Apparatus and Systems Vol 8 no 1 Otober 1968, pp [4] M.Meisingset, A.M. Gole, A Comparison of Conventional and Capaitor Commutated Converters Based on Steady State and Dynami Considerations Proeedings, IEE 7 th onferene on AC-DC transmission, London November 1, pp49-54 [5] Sadek, K.; Pereira, M.; Brandt, D.P.; Gole, A.M.; Daneshpooy, A. Capaitor ommutated onverter iruit onfigurations for DC transmission IEEE Transations on Power Delivery, Vol. 13 (4) Ot 1998 Pp: [6] Gomes, S., Jr.; Martins, N.; Jonsson, T.; Menzies, D.; Ljungqvist, R Modeling apaitor ommutated onverters in power system stability studies IEEE Transations on Power Systems, Volume 17 (2) May 2, Pp [7] D.A. Woodfford, Solving the Feroresonnae problem When Compensating a DC onverter Station with a Series apaitor IEEE transations on Power systems, Vol 11, no 3, pp [8] N Ottosson, L Kjellin, Modular bak-to-bak HVDC with apaitor Commutated onverters (CCC) IEE 7 th onferene on AC-DC transmission, London November 1, pp55-59 [9] C. Lander Power Eletronis MGraw Hill, 1987 [1] N. Mohan, T. M. Undeland, W. P. Robbins Power Eletronis Converters, Appliations and Design, John Wiley & Sons, 1995 [11] R.M.Davies, J.R.Melling, Quantitative Comparison of Commutation iruits for bridge inverters Proeedings of IEE, Vol 124 (3) 1977, pp [12] M. Szehman, T. Wess and C.V. Thio, April 1991, "First Benhmark model for HVDC ontrol studies", CIGRE WG 14.2 Eletra No. 135, pages: [13] D. Jovi N. Pahalawaththa, M. Zavahir Analytial Modelling of HVDC-HVAC Systems. IEEE Trans. on PD, Vol. 14, No 2, pp , April 1999 [14] D.Jovi N.Pahalawaththa, M.Zavahir, Inverter Controller for Very Weak Reeiving AC Systems IEE Proeeding Gen., Transmission and Distribution, Vol. 146, no 3, May 1999, pp IX. APPENDIX INVERTER CONTROLLER GAINS Comment Gain value AC voltage ontrol Kv.3 [deg/kv] Kvi 5 [deg/kvs] Stabilising ontrol Ka -.14 Filter Ti.8 [s] X. BIOGRAPHY Dragan Jovi (S 97, M ) obtained a B.S. in Control Engineering from the University of Belgrade, Yugoslavia in 1993 and a Ph.D. degree in Eletrial Engineering from the University of Aukland, New Zealand in He is urrently a leturer with the University of Aberdeen, Sotland where he has been sine 4. He also worked as a leturer with University of Ulster, in period -4 and as a design Engineer in the New Zealand power industry in period His researh interests lie in the areas of FACTS, HVDC and ontrol systems.