A Low-Cost Efficient Hardware-in-the-Loop Testbed for Distributed Generation Penetration Analysis

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1 Journal of Energy and Power Engineering 11 (017) doi: / / D DVID PUBLISHING Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis Kourosh Sedghisigarhi 1, Yadollah Eslami and asd Davari 1. Eletrial and Computer Engineering Department, California State University, Northridge 910, US. Eletrial and Computer Engineering Department, West Virginia University Institute of Tehnology, Montgomery 516, US Reeived: Deember 6, 016 / epted: January 04, 017 / Published: pril 0, 017. bstrat: In this paper a real-time testbed using hardware-in-the-loop for the analysis of the effets of DGs (distributed generators) on mirogrids is presented. The distribution network is implemented in SIMULINK using the IEEE 15-node distribution feeder onneted to two DGs feeding the grid using two smart inverters. The inverters ative and reative power ontrol is performed by TI C000-based ontrollers and the hardware onnetions to the system are done through dspce interfae module. The system is designed suh that it an easily be modified to hange the loation of the DGs and/or to hange the number of DGs onneted to the grid. Several ase study results are presented and ompared against simulations to verify the effetiveness and auray of the system, model, and the employed power ontrol shemes. Key words: Distributed generation, inverter, real-time ontrol, ommuniation, oordinated ontrol. 1. Introdution s renewable energy generation, suh as solar and wind, beomes more affordable, popular, and widespread, more of these small power generators will be onneted to the distribution grid at any given time. These DGs (distributed generators) will ontinuously affet the distribution network state and stability, espeially the mirogrids [1] whih will be the future eletri power system infrastruture. dvaned monitoring and ontrol systems are to be deployed in mirogrids to avoid issues aused by the unertainty and variability of the renewable energy soures that feed the DGs and to have a stable and reliable power distribution system [1]. The signifiant R/X ratio in distribution lines suggests the importane of the line resistane; R, and its effets on the power flow ontrol on mirogrids and mirogrid power ontrol equations [, ]. Supplying Corresponding author: Kourosh Sedghisigarhi, Ph.D., assistant professor, researh fields: power systems, mirogrids, power eletronis, renewable energy, smart grids. power from the end users at the end of the line side, however, will redue on transmission lines and improve voltage and frequeny stability, if the DGs are ontrolled properly. This an be ahieved through deployment of inverter-based DGs whih an respond to the system variations muh faster than their rotation-based generator ounter parts. In reent years, signifiant researhes on the ontrol and operation of mirogrids have been onduted and both entralized and deentralized ontrol shemes have been proposed and studied [4-9]. The newer generation of inverters used as part of the DGs, alled smart inverters, annot only ontrol the ative power, but also the reative power, and hene, improve the system power fator. In this paper the development of an HIL (hardware-in-the-loop) system for the analysis and study of the behavior of a distribution network in the presene of two smart-inverter-based DGs is presented. The atual DG voltages are fed to the system using the dspce I/O module [10] and all the measurement and ommuniations are performed by the dspce Control Desk tool.

2 70 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis The proposed hardware and software are designed suh that they an be easily modified to aommodate more/less DGs on any nodes of the mirogrid. The IEEE 15-node distribution feeder model [11, 1] implemented in SIMULINK is the ore of the system, augmented by the DG models representing atual loal DGs to ontrol the ative and reative power onsumption/prodution at seleted nodes and analysis and measurement of penetration levels. The measured and simulated values are ompared to verify the validity of the system behavior and the employed power ontrol algorithms in the DGs.. IEEE Distribution Test Feeder n inverter power flow ontrol method was presented by authors in Ref. [6] in the grid-onneted mode. These inverters operate in low voltage distribution level system where R/X ratio of line is muh greater ompared to transmission system line parameters. The inverters ative and reative power ontrol is performed by TI C000-based ontrollers and the hardware onnetions to the system are done through dspce interfae module. The system is designed suh that it an easily be modified to hange the loation of the DGs and/or to hange the number of DGs onneted to the grid. Figs. 1 and indiate the IEEE 15 Bus node feeder [10] developed in MTLB Simpowersystem toolbox and its voltage profile results [1, 14]. Obtained load flow results are as below: Total generation: P = 1, kw, Q = 1, kvar. Total Zshunt load: P = 1,16.01 kw, Q = 1, kvar. Total losses: P = kw, Q = 47.7 kvar. The model has been simulated for three ase studies as follows. Fig. 1 IEEE 15 bus distribution feeder developed in MTLB simpowersystem toolbox.

3 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis 71 Fig. Voltage profile for IEEE 15-bus distribution network..1 Case 1: DG1 Is Conneted to Bus #1 DG1 whih is a VSI (voltage soure inverter) [15] based distributed generator provides ative and reative power for the following set points: Case 11: P1 = 10 kw; Q1 = 0 kvar; Case 1: P = 10 kw; Q = 80 kvar. The load voltage profiles for the following ase studies is plotted in Fig... Case : DG Is Conneted to Bus #5 DG whih is an inverter based distributed generator provides ative and reative power for the following set points: Case 1: P1 = 110 kw; Q1 = 0 kvar; Case : P = 00 kw; Q = 80 kvar. The load voltage profiles for ase studies 1 and are plotted in Fig. 4.. Case : DG1/DG re Conneted to Buses #5 and #1 s shown in Fig. 5, both DG1 and DG are feeding power to buses 5 and 1. The load voltage profiles for the following ase studies are plotted in Fig. 6. Case 1: P1 = 10 kw; Q1 = 0 kvar; P = 10 kw; Q = 0 kvar; Case : P1 = 10 kw; Q1 = 0 kvar; P = 10 kw; Q = 50 kvar. as proposed in Refs. [7, 9] and depited in blok diagram in Fig. 7. This set up is a hardware-in-the-loop whih inludes three main modules: (1) The inverters; () The inverters ontroller; () The grid model. Inverters, loal loads and ontrollers are hardware modules whih are from Labvolt [0] and Texas Instruments. Eah inverter is being ontrolled by a TMS0F85-based TI (texas instrument) development board [17] that implements the P-Q ontrol algorithm proposed and presented by the authors in Ref. [8]. The test feeder model and measurement devies are depited in Fig. 8. The test feeder (IEEE 15 bus system) is shown in blok C of Fig. 8. The interfae blok between the inverters and the grid is a dspce DS1104 I/O module whih has several analog and digital I/O ports and serial interfaes. This I/O module is the interfae between the atual hardware setup and the system model developed in MTLB. Fig. Voltage profile omparison for ase 1.. Hardware Implementation The system hardware is ustom designed by authors Fig. 4 Voltage profile omparison for ase.

4 1 7 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis a b a b a b a b Fig. 5 IEEE distribution feeder with DGs on buses 5 and 1. DG inverters, respetively. The grid supply voltage is modeled as a slak bus in the software and its waveform, frequeny, and amplitude are aurately set by this approah. Inverters power interfaing setions are Fig. 6 Voltage distribution profile for ase studies. The test distribution network model is augmented with the measurement devies used at eah node for monitoring purposes. s shown in Fig. 8, the voltage and urrent (to the loal load) at eah node is measured. The ative (P) and reative (Q) power are alulated at eah node load. Notie that as shown in Fig. 8, on this experiment, node 1 of the distribution model is fed by the grid voltage and nodes 5 and 1 by both DG1 and Fig. 7 System hardware blok diagram.

5 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis 7 Fig. 8 Simulink model of the system. Fig. 9 Inverters power interfae setion.

6 74 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis Fig. 11 DSPCE I/O module. Fig. 10 Developed Hardware-in-the-loop. Fig. 1 DSPCE ontrol desk waveforms. presented in Fig. 9. Eah inverter output inludes a loal load and an isolating transformer. The inverters an be isolated or synhed to the grid using a breaker module. Connetion to the grid happens when the inverter voltage output at one side of the breaker is synhronized to the voltage of the grid on the other side of the breaker. In order to have the inverter operating at the grid-onneted mode, it must be synhronized first. Synhronization bloks used for grid-inverter synhronization are desribed in Refs. [8, 9]. Fig. 10 shows the hardware system built at the WVUIT (West Virginia University Institute of tehnology). This work station onsists of DC supply, inverter modules, loal loads, filters, inverter ontrollers; step down transduers and onnetion to the dspce I/O module as shown in Fig. 11. TI Miroontrollers [16-19] are used for synhronization, ative and reative power ontrol (The details of these boards and the algorithms are provided in Refs. [8, 9]). The system ontrol panel is designed using dspce ontrol desk developer onsisting of three major windows that are waveform monitor, inverter monitor and ontrol, node power monitoring windows as shown in Fig. 1 and explained in details in Ref. [11]. 4. Experimental Results ll simulated ase studies presented in Setion are tested on the real-time HIL system in this setion. The presented infrastruture was apable of handling two simultaneous grid-onneted inverters with a sampling interval of s. The power alulations bloks are using a large sampling interval of 0.01 s. Fig. 1 illustrates the ontrol desk window for the test feeder when there is no DG onneted. Figs. 14 and 15 represent DG1 output onneted to the bus #1 while DG is isolated and supplying only the loal load. The DG1 output is illustrated for the following ase studies: Case 11: P1 = 10 kw; Q1 = 0 kvar; Case 1: P = 10 kw; Q = 80 kvar. Figs. 16 and 17 represent DG output onneted to the bus #5 while DG1 is isolated and supplying only the loal load for ases 1 and, respetively.

7 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis 75 Fig. 1 Grid output with no DGs onneted. Fig. 14 DG outputs for ase #11. Fig. 15 DG outputs for ase #1.

8 76 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis Fig. 16 DG outputs for ase 1. Fig. 17 DG outputs for ase. Case 1: P1 = 110 kw; Q1 = 0 kvar; Case : P = 00 kw; Q = 80 kvar. Figs. 18 and 19 depit system operation for ases 1 and while both DG1 and DG outputs are onneted to buses 1 and 5, respetively. Case 1: P1 = 10 kw; Q1 = 0 kvar; P = 10 kw; Q= 0 kvar; Case : P1 = 10 kw; Q1= 0 kvar; P = 10 kw; Q= 50 kvar. The output ative and reative power from the main grid (P grid, Q grid) has been shown in the middle of eah window in Figs These figures learly indiate proper operation of the ontroller sine inverter outputs follow the ontroller set point. When inverter is isolated, it provides power to the loal load only so the synhronization indiator (green light) is off. 5. Results Comparison The grid ative and reative power outputs (P grid, Q grid) have been ompared to one another in Table 1. The simulation and experimental obtained data are very lose with a minor error for all ase studies. The voltage profile experimental data as well as power flow of the lines showed similar behavior as illustrated in Setion.

9 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis 77 Fig. 18 DG outputs for ase 1. Fig. 19 DG outputs for ase. Table 1 Comparison between experimental and simulation results. Case # Simulation Experimental P/Q P grid P grid Q grid Q grid (kw) (kw) (kvar) (kvar) No DG 1,177 1,00 1,18 1,197 Case 11 1,101 1,156 1,10 1,178 Case 1 1,014 1,070 1,060 1,10 Case 1 1,10 1,166 1,11 1,190 Case 1,0 1,076 1,057 1,18 Case ,109 1,18 Case 1,044 1,075 1,074 1,156 Inrease in DG s penetration resulted in less power demand from the main grid in both experimental and simulation modes. In addition, the voltage profile was improved more in buses 5 and 1 due to more power output generation from the distributed generators. 6. Conlusions This paper introdued a real-time hardware-in-the-loop testbed to analyze the impat of distributed generations on low voltage distribution level system where R/X ratio is not small. The IEEE 15-bus node distribution feeder has been hosen as the test feeder. Two real time inverter based distributed generators through the dspce hardware interfae have been onneted to the test system. The inverters ative and reative power ontrol is performed by TI

10 78 Low-Cost Effiient Hardware-in-the-Loop Testbed for Distributed Generation Penetration nalysis C000-based ontrollers and the hardware onnetions to the system are done through dspce interfae module. The system is designed suh that it an easily be modified to hange the loation of the DGs and/or to hange the number of DGs onneted to the grid. Several ase study results are presented and ompared with simulations to verify the effetiveness and auray of the system, model, and the employed power ontrol shemes. Referenes [1] Lasseter, R. 00. Mirogrids. In Proeedings of the IEEE Power Engineering Soiety Winter Meeting, [] Peças Lopes, J.., Silvan,., Polenz, C. L., and Cherkaoui, M. R Identifiation of Control and Management Strategies for LV Unbalaned Mirogrids with Plugged-in Eletri Vehiles. Eletri Power Systems Researh 80 (8): [] Li, Y. W., and Kao, Ch.-N n urate Power Control Strategy for Power-Eletronis-Interfaed Distributed Generation Units Operating in a Low-Voltage Multibus Mirogrid. IEEE Transations on Power Eletronis 4 (1): [4] Li, Y., and Li, Y. W Deoupled Power Control for an Inverter Based Low Voltage Mirogrid in utonomous Operation. In Proeedings of the IEEE 6th International Power Eletronis and Motion Control Conferene, [5] Sedghisigarhi, K Power Flow Control of Inverter Based Distributed Generators in LV Mirogrids. IEEE Power & Soiety General Meeting, Detroit, MI. [6] Sedghisigarhi, K., Eslami, Y., and Davari,. 01. Real-Time Power Controller for Grid-Conneted Inverters in LV Smart Mirogrids. 01 CIGRE Canada Conferene, Montreal, ON. [7] Sedghisigarhi, K., Eslami, Y., and Davari,. 01. Real-time Power Controller for Grid-Conneted Inverters in LV Smart MiroGrids. Journal of Energy and Power Engineering 7 (11): [8] Sedghisigarhi, K., Eslami, Y., and Davari, Real-Time Testbed for Coordinated Control of Inverters in LV Mirogrids. IEEE International Energy Conferene (ENERGYCON 014), Dubrovnik, Croatia. [9] Satyanarayana, S., Ramana, T., Sivanagaraju, S., and Rao, G. K. 00. Voltage Stability nalysis for Radial Distribution Networks with and without Compensation. International Journal of Water and Energy 60 (1): [10] DSPCE DSPCE-DS rd/ds1104.fm. [11] Singh, M., Panigrahi, B. K., bhynkar,. R., Mukherjee, R., and Kundu, R. 01. Optimal Loation, Size and Protetion Coordination of Distributed Generation in Distribution Network. IEEE Symposium on Swarm Intelligene. [1] Sedghisigarhi, K., Eslami, Y., and Davari, Hardware in the Loop Testbed for Distributed Energy Generation Penetration nalysis. IEEE Energy Conferene, Leuven, Belgium. [1] MathWorks Simulink. [14] MathWorks SimPower Systems. [15] Mohan, N., Undeland, T. M., and Robbins, W. P. 00. Power Eletronis: Converters, ppliations, and Design, rd Edition. John Wiley and Sons. ISBN: [16] Texas Instruments C000 Real-Time Miroontrollers. essed Nov [17] Texas Instruments SPRS49I. essed Ot [18] MathWorks Embedded Coder. essed Sep [19] Texas Instruments CCstudio IDE. essed Sep studio.html. [0] Labvolt. essed Nov