MPEN 411 VLSI Digital ircuits Spring 2012 Lecture 06: Static MOS Logic [dapted from Rabaey s Digital Integrated ircuits, Second Edition, 2003 J. Rabaey,. handrakasan,. Nikolic] Sp12 MPEN 411 L06 S.1
Review: MOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts One full photolithography sequence per layer (mask) uilt (roughly) from the bottom up 4 metal 2 polysilicon exception! 3 source and drain diffusions 1 tubs (aka wells, active areas) reate contact and via windows Deposit and pattern metal layers Sp12 MPEN 411 L06 S.2
MOS ircuit Styles Static complementary MOS - except during switching, output connected to either or GND via a lowresistance path high noise margins - full rail to rail swing - V OH and V OL are at and GND, respectively low output impedance, high input impedance no steady state path between and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic MOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise Sp12 MPEN 411 L06 S.3
Static omplementary MOS Pull-up network (PUN) and pull-down network (PDN) In 1 In 2 In N In 1 In 2 In N PUN PDN PMOS transistors only pull-up: make a connection from to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pull-down: make a connection from F to GND when F(In 1,In 2, In N ) = 0 NMOS transistors only Question : How many transistors are used to implement N-input function F(In1,In2, InN)? Sp12 MPEN 411 L06 S.4
onstruction of PDN NMOS devices in series implement a NND function NMOS devices in parallel implement a NOR function + Sp12 MPEN 411 L06 S.5
Dual PUN and PDN PUN and PDN are dual networks DeMorgan s theorems + = [!( + ) =!! or!( ) =! &!] = + [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN omplementary gate is naturally inverting (NND, NOR, OI, OI) Number of transistors for an N-input logic gate is 2N Sp12 MPEN 411 L06 S.6
MOS NND F 0 0 1 0 1 1 1 0 1 1 1 0 Sp12 MPEN 411 L06 S.7
MOS NOR + F 0 0 1 0 1 0 1 0 0 1 1 0 Sp12 MPEN 411 L06 S.8
omplex MOS Gate D D OUT =!(D + ( + )) Sp12 MPEN 411 L06 S.10
Static omplementary MOS Naturally inverting, implementing only functions such as NND, NOR, and XNOR in a single stage. In 1 In 2 In N In 1 In 2 In N PUN PDN PMOS transistors only pull-up: make a connection from to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pull-down: make a connection from F to GND when F(In 1,In 2, In N ) = 0 NMOS transistors only Question1: why PUN are PMOS only and PDN are NMOS only? Sp12 MPEN 411 L06 S.11
Threshold Drops PUN S D D 0 V GS S 0 - V Tn L L PDN 0 V Tp D L V GS S L S D Sp12 MPEN 411 L06 S.13
Standard ell Layout Methodology Routing channel signals GND What logic function is this? Sp12 MPEN 411 L06 S.14
OI21 Logic Graph j X PUN X =!( ( + )) X i i j GND PDN Sp12 MPEN 411 L06 S.15
Two Stick Layouts of!( ( + )) crossover requiring vias X X GND GND uninterrupted diffusion strip Sp12 MPEN 411 L06 S.16
onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X X i j Sp12 MPEN 411 L06 S.18 GND For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
OI22 Logic Graph X PUN D D X =!((+) (+D)) X D D GND PDN Sp12 MPEN 411 L06 S.19
OI22 Layout D X GND Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) Sp12 MPEN 411 L06 S.20
XNOR/XOR Implementation XNOR XOR Sp12 MPEN 411 L06 S.21 How many transistors in each? an you create the stick transistor layout for the lower left circuit?
Static MOS Full dder ircuit (page 565) out =+ in + in Sum = in +! out (++ in ) in in! out!sum in in in out = in & ( ) ( & ) Sum =! out & ( in ) ( & & in ) Sp12 MPEN 411 L06 S.24 # transistors = 24+4
Two chips you are seeing today Microprocessor SI (pplication Specific I) Sp12 MPEN 411 L06 S.25
Standard ell Library NND INV Sp12 MPEN 411 L06 S.26
Standard ell Library NND INV NND Sp12 MPEN 411 L06 S.27
The design flow VHDL (decoder.vhd) Simulation Synthesis Verilog netlist (decoder.v) Standard ell Lib Place/Route Physical layout (decoder.cif) Sp12 MPEN 411 L06 S.28
The IM SI Design Flow Sp12 MPEN 411 L06 S.29
Next Lecture and Reminders Next lecture Pass transistor logic - Reading assignment Rabaey, et al, 6.2.3 Sp12 MPEN 411 L06 S.30