CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 15: Dynamic CMOS [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN 411 L15 S.1
Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T Sp12 CMPEN 411 L15 S.2
Industry Example: IBM Cu11 (0.13 um) Dual-VDD (Voltage Island) ASIC Cu11 (130nm) Library : Dual-vt library Nominal Vt level (~300mv) Low Vt level (~210mv) Low-vt version has same physical footprint ~15% improvement in gate delay ~10x increase in leakage power Sp12 CMPEN 411 L15 S.3
How about Gate Leakage? multiple gate oxide (Sylvester et.al., DATE-2004) Sp12 CMPEN 411 L15 S.4
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Dynamic CMOS In circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of N requires devices circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires only transistors takes a sequence of and conditional phases to realize logic functions Sp12 CMPEN 411 L15 S.6
Dynamic Gate M p Out M p off on 1 Out!((A&B) C) In 1 In 2 In 3 PDN M e C L A B M e off on C Two phase operation ( = 0) ( = 1) Sp12 CMPEN 411 L15 S.7
Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make transition(s) during evaluation. Output state is stored on C L Sp12 CMPEN 411 L15 S.8
Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is (versus 2N for static complementary CMOS) should be smaller in area than static complementary CMOS Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed - sizing of the devices is not important for proper functioning (only for performance) Faster switching speeds reduced load capacitance due to lower number of transistors per gate (C int ) so a reduced logical effort reduced load capacitance due to smaller fan-out (C ext ) no I sc, so all the current provided by PDN goes into discharging C L Ignoring the influence of precharge time on the switching speed of the gate, t plh = 0 but the presence of the evaluation transistor slows down the t phl Sp12 CMPEN 411 L15 S.9
Properties of Dynamic Gates, con t Power dissipation should be lower no power consumption since the pull-up path is not on when evaluating lower - both C int (since there are fewer transistors connected to the drain output) and C ext (since there the output load is one per connected gate, not two) by construction can have at most one transition per cycle no But power dissipation can be significantly higher due to extra load on Needs a precharge clock Sp12 CMPEN 411 L15 S.10
Dynamic Behavior Out 2.5 Evaluate In 1 In 2 1.5 In 3 In 4 0.5-0.5 In & Out Precharge 0 0.5 1 Time, ns #Trns V OH V OL V M NM H NM L t phl t plh t pre 6 2.5V 0V V Tn 2.5-V Tn V Tn 110ps 0ns 83ps Sp12 CMPEN 411 L15 S.11
Power Consumption of Dynamic Gate M p Out In 1 In 2 In 3 PDN M e C L Power only dissipated when previous Out = 0 Sp12 CMPEN 411 L15 S.13
Dynamic Power Consumption is Data Dependent Dynamic 2-input NOR Gate A B Out 0 0 1 0 1 0 1 0 0 1 1 0 Assume signal probabilities P A=1 = 1/2 P B=1 = 1/2 Then transition probability P 0 1 = P out=0 x P out=1 = Switching activity can be higher in dynamic gates! P 0 1 = Sp12 CMPEN 411 L15 S.14
Issues in Dynamic Design : Charge Leakage M p Out A=0 C L M e V Out Evaluate Precharge Leakage Minimum clock rate of a few khz Sp12 CMPEN 411 L15 S.15
Voltage (V) Impact of Charge Leakage Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage. 2.5 1.5 Out 0.5-0.5 0 20 40 Time (ms) Sp12 CMPEN 411 L15 S.17
A Solution to Charge Leakage Keeper compensates for the charge lost due to the pulldown leakage paths. Keeper M p M kp A B C L!Out M e Same approach as level restorer for pass transistor logic Sp12 CMPEN 411 L15 S.18
Issues in Dynamic Design : Charge Sharing A B=0 M p M e C a C b C L Out Charge stored originally on C L is redistributed (shared) over C L and C A leading to static power consumption by downstream gates and possible circuit malfunction. When V out = - V DD (C a / (C a + C L )) the drop in V out is large enough to be below the switching threshold of the gate it drives causing a malfunction. Sp12 CMPEN 411 L15 S.19
Solution to Charge Redistribution A M p M kp Out B M e Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) Sp12 CMPEN 411 L15 S.22
Issues in Dynamic Design : Cascading Gates V In M p M e Out1 M p M e Out2 In Out1 Out2 V Tn V t Only a single 0 1 transition allowed at the inputs during the evaluation period! Sp12 CMPEN 411 L15 S.27
Domino Logic In 1 In 2 M p PDN 1 1 1 0 Out1 0 0 0 1 In 4 M p M kp PDN Out2 In 3 In 5 M e M e Sp12 CMPEN 411 L15 S.28
Why Domino? In 1 In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! Sp12 CMPEN 411 L15 S.29
Domino Zero Detector In 7 In 6 In 5 In 4 In 3 In 2 In 1 In 0 not zero How would you build it in static CMOS? Sp12 CMPEN 411 L15 S.31
Properties of Domino Logic Only non-inverting logic can be implemented, fixes include can reorganize the logic using Boolean transformations use differential logic (dual rail) use np-cmos (zipper) Very high speed t phl = 0 static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances) Sp12 CMPEN 411 L15 S.33
Differential (Dual Rail) Domino Out = AB off on M p M kp M kp M p 1 0 1 0 A B!A!B!Out =!(AB) M e Due to its high-performance, differential domino is very popular and is used in several commercial microprocessors! Sp12 CMPEN 411 L15 S.34
Other Domino Variations Multiple output domino logic exploits the fact that certain outputs are subsets of other outputs to generate a number of logic functions in a single gate. Compound domino M p M p M p A D B C E F G H M e M e M e Sp12 CMPEN 411 L15 S.35
np-cmos (Zipper) In 1 In 2 In 3 M p PDN M e 1 1 1 0 Out1! In 4 In 5! M e PUN M p 0 0 0 1 Out2 (to PDN) to other PDN s to other PUN s Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN Sp12 CMPEN 411 L15 S.36
DCVS Logic (Differential Cascade Voltage Switch 1 0 on off off on 0 1 Out!Out In 1!In 1 In 2!In 2 PDN1 off on PDN2 on off PDN1 and PDN2 are mutually exclusive Sp12 CMPEN 411 L15 S.39
DCVSL Example!Out Out B!B B!B A!A Sp12 CMPEN 411 L15 S.40
How to Choose a Logic Style Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing Style # Trans Ease Ratioed? Delay Power Comp Static 8 1 no 3 1 CPL* 12 + 2 2 no 4 3 domino 6 + 2 4 no 2 2 + clk DCVSL* 10 3 yes 1 4 * Dual Rail 4-input NAND Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling. Sp12 CMPEN 411 L15 S.41
Itanium 2 Domino Circuitry Integer execution unit Multimedia execution unit 2 Floating point units Register Files Out of order control issue logic Source: Advanced Domino Circuit Design, Intel, Tom Grutkowski, DATE 2004 Sp12 CMPEN 411 L15 S.42
What is Soft Error Soft errors are circuit errors caused due to excess charge carriers induced primarily by external radiations These errors cause an upset event but the circuit it self is not damaged. Same a SEU (single event upset) Sp12 CMPEN 411 L15 S.43
Soft Errors The Phenomena G Current A particle strike n+ n channel + - + - + - +- + - + - + - + - + - p substrate n+ B Sp12 CMPEN 411 L15 S.44
Soft Errors The Phenomena V DD A particle strike Bit Flip!!! V in V out!b L B L C L 1->0 0 0->1 W L A particle strike Sp12 CMPEN 411 L15 S.45
What cause Soft Errors? At ground level, there are three major contributors to Soft errors. 1. Cosmic Ray induced neutrons 2. Alpha particles emitted by decaying radioactive impurities in packaging or interconnect materials. 3. Neutron induced 10 B fission which releases a Alpha particle and 7 Li Sp12 CMPEN 411 L15 S.46
Evidence of Cosmic Ray Strikes Documented strikes in large servers found in error logs Normand, Single Event Upset at Ground Level, IEEE Transactions on Nuclear Science, Vol. 43, No. 6, December 1996. Sun Microsystems, 2000 Cosmic ray strikes on L2 cache with no error detection or correction - caused Sun s flagship servers to suddenly and mysteriously crash! Companies affected - Baby Bell (Atlanta), America Online, Ebay, & dozens of other corporations - Verisign moved to IBM Unix servers (for the most part) Sp12 CMPEN 411 L15 S.47
Reactions from Companies Fujitsu SPARC in 130 nm technology 80% of 200k latches protected with parity compare with very few latches protected in Mckinley ISSCC, 2003 IBM declared 1000 years system MTBF as product goal very hard to achieve this goal in a cost-effective way Sp12 CMPEN 411 L15 S.48
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Space redundancy: Redundant Logic Logic 1 Logic 2 Voter Logic3 Point of failure!! Sp12 CMPEN 411 L15 S.50
Next Lecture and Reminders Next lecture Timing metrics, static sequential circuits - Reading assignment Rabaey, et al, 7.1-7.2 Sp12 CMPEN 411 L15 S.51