Towards a PowerSoC Solution for Automotive Microcontroller Applications Christoph Sandner, Gerhard Maderbacher, Karlheinz Kogler, Joachim Pichler, Federico Capponi, Herbert Gruber, Sylvia Michaelis, Dietrich Michaelis, Frank Prämassing, Anamaria Anca, Franz Reininger (Infineon Technologies Austria AG, Villach), Andreas Einwanger, Gottfried Beer (Infineon Technologies AG, Regensburg) EU FP7-ICT-2011-8 PowerSWIPE Project no.: 318529 Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014)
2 Outline Automotive uc Application Power Conversion Requirements Demonstrator System Architecture High-Voltage (HV) DC-DC Low-Voltage (LV) DC-DC Challenges: Efficiency, packaging, ringing, EMI, cost Conclusions
3 Universal Power Management Specs Take Up No Space Cost Nothing Last Forever Zero Power Loss [Cian Ó Mathúna, Tyndall National Institute, Ireland]
PowerSwipe Project Partners Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 4
5 Motivation [L.S. Ming, Architecture Trends Body Electronics, 2010]
6 Automotive uc Application Increasing Power + Complexity State-of-the-Art Next Generation High-End ILoad>1A Eff>90% Performance Driven DC/DC is a must LC-DC/DC dominates External passives 4-5 Voltage Domains DC/DC is a must LC-DC/DC dominates Integrated passives, PwrSiP External passives for very high-end only 5-10 Voltage Domains Distributed power concepts Mid-Range ILoad~0.5A Eff>80% Few DC/DC used but LDOs dominate External passives 2-4 Voltage Domains DC/DC takes over Both LC- and Switched-cap DC/DC used Integrated passives, PwrSiP, PwrSoC 5-10 Voltage Domains Distributed power concepts Low-End ILoad<0.3A Cost-driven No DC/DC used LDOs dominate External passives 1-3 Voltage Domains Both DC/DC and LDO used LDO-only for very low-end Devices Integrated passives, PwrSiP, PwrSoC 2-5 Voltage Domains 2012 2013 2014 2015 2016 2017 2011 2018 2019 2020
7 Automotive uc Application Increasing Power + Complexity State-of-the-Art Next Generation High-End ILoad>1A Eff>90% Performance Driven DC/DC is a must LC-DC/DC dominates External passives 4-5 Voltage Domains DC/DC is a must LC-DC/DC dominates Integrated passives, PwrSiP External passives for very high-end only 5-10 Voltage Domains Distributed power concepts Mid-Range ILoad~0.5A Eff>80% Few DC/DC used but LDOs dominate External passives 2-4 Voltage Domains DC/DC takes over Both LC- and Switched-cap DC/DC used Integrated passives, PwrSiP, PwrSoC 5-10 Voltage Domains Distributed power concepts Low-End ILoad<0.3A Cost-driven No DC/DC used LDOs dominate External passives 1-3 Voltage Domains Both DC/DC and LDO used LDO-only for very low-end Devices Integrated passives, PwrSiP, PwrSoC 2-5 Voltage Domains 2012 2013 2014 2015 2016 2017 2011 2018 2019 2020
8 Automotive uc Application Typical Engine Management Module: 2 4x shrink in footprint
9 AURIX Engine Management System 12V Car Battery (45V 6V) 1 st Voltage Conversion to 3.3/5V 2 nd Voltage Conversion to Vcore
10 VBAT Voltage Conversion Alternatives to 2-step fixed Vint approach: 1-step not really 2-step flex Vint: Vbat 45 6V 1st stage: open loop Vint 5 3V 2nd stage: closed loop to provide Vout regulation Vout 1 1.3V
Fibonacci SC-DCDC as 1 st Stage [P. Alou, J. Oliver, UPM] 6 5.5 5 4.5 Gains: 5/8, 3/8, 2/8, 1/8 4 3.5 3 10 15 20 25 30 35 40 45 Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 11
12 Sytem Overview Demonstrator HV-Chip: 130nm BCD CMOS LV-Chip: 40nm (Flash) CMOS
13 Specifications High-Voltage (HV) Chip: Vin: 16V 6V Vout: 5.0 3.3V Iout_max: 500mA η_peak: 80% PFM, CCM, DCM Low-Voltage (LV) Chip: Vin: 5V 3.3V Vout: 1.0 1.3V Iout1_max: 500mA Iout2_max: 200mA η_peak: 90% PFM, CCM, DCM (Embedded with uc) Technology: Automotive qualified Temp range junction: -40deg +150deg
14 Outline Automotive uc Application Power Conversion Requirements Demonstrator System Architecture High-Voltage (HV) DC-DC Low-Voltage (LV) DC-DC Challenges: Efficiency, packaging, ringing, EMI, cost Conclusions HV-Chip: 130nm BCD CMOS LV-Chip: 40nm (Flash) CMOS
15 HV DC-DC Simulated Efficiency Vin=12V, fsw=10mhz, ESR L =500mΩ, ESR COUT =50mΩ, ESR CHS =100mΩ, ESR CLS =50mΩ
16 Outline Automotive uc Application Power Conversion Requirements Demonstrator System Architecture High-Voltage (HV) DC-DC Low-Voltage (LV) DC-DC Challenges: Efficiency, packaging, ringing, EMI, cost Conclusions HV-Chip: 130nm BCD CMOS LV-Chip: 40nm (Flash) CMOS
17 Efficiency Optimization: Device Dimensioning NMOS vs. PMOS Width: NMOS vs. PMOS Vgs:
Efficiency Optimization (CCM) Efficency vs. Load: Oct. 6, 2014 Efficiency vs. Switching Frequency: 4th International Power Supply on Chip Workshop (PwrSoC2014) 18
Efficiency Optimization Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 19
LV DCDC CCM/DCM Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 20
Package Parasitics: HF Issue 10Vpp supply ringing Without SiP integration such HF switching is not possible at all due to ringing! Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 21
LV Switched-Capacitor DCDC Theoretical Efficiency of an SC DCDC with Different Gain Modes (Vout=1.3V) Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 22
Switched-Cap DC-DC Converter Topology: Series-Parallel Cfly: 8x 30nF Cout: 260nF Top level block diagram Gain modes: 1/2 ( Vdd=3.3V ) 1/3 ( Vdd=5V ) 4 Interleaved Stages: 2 Cfly/stage 9 Switches/stage fsw = 5 MHz max. Controller: Pulse Frequency Modulation (PFM) Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 23
SC DC-DC Converter: Efficiency Simulation (Vin = 5V: Gain=1/3; Vin = 3.3V: Gain=1/2; Vout=1.3V) Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 24
ewlb Packaging Face to face with Cu-Pillar/ Sn-cap Submodule 2 4 HV / LV PMIC 3 Inductor 5 1 Functional Interposer incl. caps 1: Functionalized Silicon interposer with integrated Caps and TSVs. Routing plane on bottom side 2: Active die with Cu-pillar/Sn-cap die to interposer wafer bonded 3: Thinfilm inductor on Silicon die to wafer bonded 4: molded artifcial wafer 5: redistribution layer (RDL) and solder balls Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 25
Conclusions - Main threats towards a product: - Maintain the performance: - - Concept: Chose optimum partitioning Efficiency: Improve DCR of L, ESR of C, power switches Ringing: Optimize loop inductances in chip/package High energy density thermal issues COST, COST, COST for high volume products Get rid of TSVs, reduce cost of inductor and capacitor topology - Main Potential: - Footprint and space constraint products EMI critical products: EMI expected to improve due to much shorter current loops on both DCDC-Cin and uc decap Exploit concepts with multiple passive components (SC-DCDC) no pincount constraints Oct. 6, 2014 4th International Power Supply on Chip Workshop (PwrSoC2014) 26
Acknowledgements PowerSwipe Partners: Tyndall National Institute / University College Cork, Ireland Infineon Technologies AG, Germany Infineon Technologies Austria AG, Austria IPDiA, France Universidad Politécnica de Madrid (UPM), Spain Robert Bosch GmbH, Germany Université de Lyon, Claude Bernard (UCBL), Lyon This work is funded by: EU Oct. 6, 2014 FP7-ICT-2011-8 PowerSWIPE Project no.: 318529 4th International Power Supply on Chip Workshop (PwrSoC2014) Page 27