Test Scheduling for Circuits in Micron to Deep Submicron Technologies

Transcription

1 Test Scheduling for Circuits in Micron to Deep Submicron Technologies Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan Department of Electrical and Computer Engineering, University of Wisconsin-Madison 1415 Engineering Drive, Madison,WI Abstract We discuss the test scheduling problem in this paper. We first provide a historical perspective of the original test scheduling formulation that dealt only with resource conflicts, followed by the consideration of power constraint test scheduling. We then move on to the recent formulations which include dealing with thermal constraint. We explain solutions, their limitations and the challenges that remain. With the emergence of on-chip sensors, in future it may be possible to leverage the use of such sensors to arrive at more efficient schedules. The paper explains these new opportunities and suggests research directions. This paper also contains an exhaustive list of references that may help the researchers and practitioners dealing with this problem. I. INTRODUCTION A major objective of the research in Very-Large-Scale Integration (VLSI) circuits testing is to reduce the total test time thus the test cost. Test parallelism is one of the main techniques to shorten the test time. However, during the testing of a complex integrated circuit (IC), digital board, or system, not all tests may be applied at the same time due to constraints of the circuit and the test. The test scheduling problem is to minimize the total test time while meeting all the constraints. The test scheduling problem can be described as follows: A test set S, consisting of n tests t i, i = 1 to n, needs to be applied to a device under test. Each test t i has 1) test length l i, which often is related to the number of test vectors in test t i, 2) test power consumption P i, which indicates the power consumption when test t i alone is applied to the device, 3) test compatibility with the other tests in the test set S. A test t i is compatible with test t j if there is no resource conflict between t i and t j and they can be applied to the device simultaneously. The most general formulation of the test scheduling problem is to find a test schedule such that: i) The total test application time is minimized. Total test application time is defined as the earliest time at which all tests have completed. ii) There is no test resource conflict between any two simultaneously running tests. iii) The total power consumption of the device at all times is smaller than the power constraint, P max. iv) The temperature at every location in the device at all times is smaller than the temperature constraint, T max. Test scheduling problem has been addressed for over twenty-five years and was developed in three stages according to the constraints being considered. Figure 1 shows a history timeline of the research in test scheduling problem. Test resource conflict was the only concern of the original test scheduling problem. With scaling of technology and increasing design sizes, power consumption during test and test data volume have grown dramatically. The power-aware test scheduling problem considers both test power consumption budget of the entire chip and also the test resource conflicts. Under the deep submicron technologies, the dramatic increase in power density can result in the chip temperatures exceeding the operating temperature limit. The thermal-aware test scheduling problem considers the test resource conflicts, the power constraint, and the temperature constraint. Resource Constrained Power Constrained Thermal Constrained Fig. 1. History of test scheduling problem Based on different scheduling schemes, test scheduling techniques can also be divided into the following three categories, as shown in Figure 2: i) Session-based test scheduling ii) Sessionless test scheduling with run-to-completion iii) Sessionless test scheduling with preemptive testing a) Session-based schedule b) Sessionless schedule Fig. 2. Test scheduling techniques categorization c) Preemptive schedule Early test session based test scheduling techniques resulted in long test time due to unnecessary idle time. Most of the recent test scheduling methods use sessionless scheduling schemes as it reduces total test application time. Preemptive testing can potentially decrease the test time but it requires preemption overhead and not all tests may be preemptable. The rest of the paper is organized as follows: Section II reviews resource constrained test scheduling. Section III describes power constrained test scheduling and Section IV explains thermal constrained static test scheduling. Sensorbased test scheduling can provide dynamic solution and it is discussed in Section V. Future directions are suggested in Section VI.

2 II. RESOURCE CONSTRAINED TEST SCHEDULING Test resource conflict was the only concern of the test scheduling problem when it was originally addressed [1]-[11]. Sharing of test resources, such as pattern generator, response compactor, test paths cause test resource conflicts. A number of scenarios are possible for core testing at the system level. The embedded cores in an SoC or multi-core system may be tested using 1) external testing 2) Built-in Self-Test (BIST) or a combination of the two methods. For external testing, the test buses that are used for test access may be shared among multiple cores. If BIST is used, the core user may design BIST logic that is shared by multiple cores to save area overhead. A core based system is shown in Figure 3. It consists of a shared external bus and six cores. Some cores share the same BIST logic, such as core 4 and core 5, and it is said that they have test resource conflict and can not be scheduled to test simultaneously. Fig. 3. An example of core based system The test scheduling problem with resource constraints has been proven to be equivalent to the open shop scheduling problem and is NP-complete. In the early test scheduling paper by Kime et al. [1], they adopted the algorithms from graph theory to solve the test scheduling problem. Firstly, a test compatibility (or incompatibility) graph (TCG) of the test resource is constructed. In the graph, each node represents a test. An edge between two nodes in a compatibility graph shows that the two tests have no resource conflict and can be run concurrently. An example of test compatibility graph is shown in Figure 4. a recent work Sugihara et al. [10] formulated the resource constrained test scheduling as a combinatorial optimization problem and then solved it using a heuristic method. In the original test scheduling problem with only resource conflict, the term test session is defined as a subset of the test set S such that all the tests in the test session are compatible and can be applied to the device at the same time. The test length of a test session is defined as the maximum test length among all the tests in that test session and the total test application time of the test set S is defined as the latest completion time among all test sessions. The major drawback of test session based test scheduling is that it only suits for the tests with equal length. Test session based scheduling assumes the next test session can start only after the previous entire test session is completed. In the case that the test length of each individual test in the test session is unequal, no new test can be scheduled even when there are tests in the test session that have completed. The advantage of session-based test scheduling is its simple test control logic but the obvious disadvantage is its longer total test time due to unnecessary large idle time. As a result, most of the recent test scheduling methods adopt the sessionless schemes. III. POWER CONSTRAINED TEST SCHEDULING Continued scaling of IC technology has resulted in substantial increase in the power densities. For example, the recent International Technology Roadmap for Semiconductors (ITRS) projects an increase in power density from about 0.57 W/mm 2 in 2007 to over 1.19 W/mm 2 by Power consumption in test mode are of even more concern as compared to normal mode because testing typically involves large switching activities. In particular, when several modules in a System-on- Chip (SoC) or in a multi-core system are tested simultaneously, the total power consumption may exceed design limits. In the deep submicron era, the situation becomes worse because there is leakage power consumption even by the idle cores. The power-aware test scheduling problem considers both test power consumption budget of the entire chip and also the test resource conflicts [12]-[74]. A set of tests cannot be scheduled together if the sum of their test power consumption exceeds the power consumption limit of the chip, even if there is no test resource conflict among them. Fig. 4. An example of test compatibility graph The clique cover heuristic is used to solve the scheduling problem based on the constructed graph. A clique is a maximal complete subgraph of a graph. In the example, (t 1,t 3,t 4 ) and (t 1,t 3,t 5 ) are two cliques in the graph. The clique cover problem is to cover all nodes by minimum number of cliques. One test scheduling solution of the example graph is {(t 1,t 3,t 4 ),(t 5 ),(t 2,t 6 )}. Besides clique cover heuristic, other graph-based algorithms, such as graph coloring, have also been used to solve the resource constrained problem. In Fig. 5. An example test compatibility graph with power information Graph-based algorithms are still popular to solve the power constrained test scheduling problem. Chou et al. [12][13] constructed test compatibility graph with power information, as shown in Figure 5. In the figure, each test t i is associated

3 with a test power P(t i ) and test length l(t i ). They divided the problem into equal test length scheduling and unequal test length scheduling and used the minimum cover table approach to find an optimum or heuristic driven schedule of power compatible tests. Rectangle (or bin) packing heuristic is another popular approach adopted to solve power constrained test scheduling problem [29][31][36]. In the rectangle packing formulation, each test is formulated into a rectangle such that the length of rectangle represents the test length of the test and the height of the rectangle represents the test power of the test, as shown in Figure 6. In the figure, the x-axis is the test time and the y- axis is the test power consumption. The test schedule is found by packing all the tests (bins) under the power limit line. In addition, we can see that this is a sessionless test scheduling scheme which reduces unnecessary idle time. Fig. 6. Rectangle packing heuristic for power constrained test scheduling Substantial research has been done to address the test scheduling problem under power constraint. Iyengar and Chakrabarty et al. discussed precedence-based, preemptive, and power constrained test scheduling [20] and formulated it into a mixed-integer linear programming (MILP) [26]. Test scheduling schemes using simulated annealing [34], genetic [60], and ant colony [67] algorithms were developed. In SoC and Network-on-Chip (NoC) test, test scheduling is often combined with test wrapper and test access mechanism (TAM) optimization [28][66][73]. Test scheduling for chips using multi-clock domain [54], multi-supply and multi-voltage [64] have also been explored. Defect-aware test scheduling in an abort-on-fail environment was also developed [23][48]. Most of the power-aware test scheduling schemes assume uniform power consumption during the lifetime of each individual test. However, the power consumption for a test varies in every clock cycle in reality. The uniform power consumption value can be either the maximum power consumption or the average power consumption of the test. This assumption works well under a loose power constraint. However, with the sharply increased power density and tighter power constraint, a more realistic model is needed. Recent works have considered the actual power consumption in every test cycle within each individual test [55]. In our recent research [88], we also include the leakage and wakeup power consumption of idle cores in the power-aware test scheduling problem. By using the cycle-accurate power model, each test will have a power profile which contains the test power at each test cycle. Comparing with the uniform power model in which each test only associates with one constant power value, the power constrained test scheduling problem becomes much more complex because the power constraint needs to be checked at each test cycle. IV. THERMAL-AWARE STATIC TEST SCHEDULING Higher power densities lead to increase in operating temperatures of the devices. Increases in operating temperature adversely affect device reliability and performance. For instance, transistor reliability decreases exponentially with an increase in its operating temperature. It has been argued that o C increase in operating temperature can cause a factor of two reduction in device lifetime. Furthermore, since electron mobility decreases with increase in temperature, there is a corresponding increase in gate delays and thus a commensurate decrease in circuit performance. Leakage power also increases with temperature; a 30 o C increase in operating temperature is expected to increase leakage current by about 30%. Overheating can also lead to timing errors during the testing process, resulting in yield loss. Industry-accepted maximum operating temperatures exist for most types of packaged ICs. However, the solution of the power constrained test scheduling problem can not guarantee that the test schedule is thermal safe. As a result, several recent papers have addressed the thermal-aware test scheduling problem which considers the test resource conflicts, the power consumption constraint, and the temperature constraint [75]-[93]. As an example, in Figure 7, the solid line shows the thermal profile for an example power-aware test schedule in which the highest temperature exceed the temperature limit 100 o C. The dash line in Figure 7 shows the thermal profile of a thermal-aware test schedule which satisfies the thermal constraint. Fig. 7. e ( O C ) Temperature Temperature profile for power aware test schedule Temperature profile for thermal aware test schedule Test time Thermal profile for power- and thermal- aware test scheduling Rosinger et al. [75] addressed this problem and proposed a method for generating thermal-safe test schedules. In their later work [79], they adopted the clique cover algorithm to find an initial test schedule meeting resource and power constraints, then eliminated the cliques which violate the temperature constraint by running thermal simulations. They also proposed a thermo-resistance model to approximately and quickly compute the thermal profile of the chip. Liu et al. [76] proposed a thermal-aware test scheduling scheme based on rectangle packing heuristic and also a scheme to spread the heat more evenly over the chip and reduce hot spots. He et al. [78] assumed that running an individual long test will exceed the temperature constraint so they proposed a test set partitioning and interleaving technique and employed constraint logic programming (CLP) to generate thermal-aware

4 test schedules. In their later work [87], they proposed a heuristic which also took into consideration of the thermal impact on neighboring modules. Yu et al. [82] presented a thermal-safe TAM and Wrapper co-design methodology for SoCs while optimizing the test schedule. Bild et al. [84] developed an optimal MILP formulation for the thermal-aware test scheduling problem. They also proposed a seed-based clustering test scheduling heuristic with a phased steady-state thermal model to reduce the thermal simulation time. The complexity of thermal simulation has become a bottleneck of the thermal-aware test scheduling problem. Two common ways to perform thermal simulation are: 1) Invoke thermal simulation tools. The advantage of this method is the accuracy but the obvious shortcoming is the execution time. 2) Develop simplified thermal model. This method can integrate the thermal simulation into the test scheduling algorithm and reduce the entire execution time. However, those models are not very accurate and will affect the performance of the thermal-aware test scheduling. The popular model used in thermal simulation is RC model, which is well known as a linear model. In our recent research [88][89][92], we exploit a method to compute the thermal profile rapidly and accurately using the superposition principle. By using the superposition principle, the thermal simulation tool is run only once at the beginning and then the computation of thermal profile becomes simple arithmetic operations, which significantly reduce the execution time of thermal simulation. We also propose a test scheduling algorithm that allows tests to start at arbitrary time along with a test partition based method to further reduce the total test time of the test schedule. V. SENSOR-BASED DYNAMIC TEST SCHEDULING IC manufacturers are researching to integrate thermal sensors into ICs and locate them strategically to monitor temperature of the IC. At present the number of such devices is limited but it is certain to grow. In particular it is expected that large number of low cost sensing devices will be integrated in future generation ICs. Traditional test schedules based on thermal simulations are often static. These static schedules often overor under- estimate the chip temperature and result in longer test time or may exceed of the temperature constraint. With the help of on-chip thermal sensors which can provide actual IC temperature, a dynamic run-time thermal aware test scheduling is possible. In our recent research [93], we proposed a dynamic thermalaware test scheduling scheme guided by the on-chip thermal sensors. Based on the fact that temperature readings are stored in the sensor registers, we proposed a method to scan the temperature data out by making all sensor registers scanable. Figure 8 shows a basic structure of temperature sensor reading scan-out. All the sensor registers are connected as a shift register. The temperature data is scanned out to the TAM and then the TAM transfers the data back to the Automatic Test Equipment (ATE). Even though a single TAM architecture is used in the example shown in the figure, the sensor reading scan-out methodology can be applied to multiple TAMs scenario easily. With the temperature readings from the sensors, a dynamic test scheduler can schedule the test dynamically according to temperature and also resource and power constraints. In our research, we also proposed two heuristics to generate the initial static test schedule for on-line dynamic adaption based on the measurements from the on-chip thermal sensors. Our simulation results showed that the performance of the thermal-aware test scheduling can be substantially improved with the help of on-chip thermal sensors, especially for chips with many cores. Fig. 8. ATE Core1 Core2 Core3 Sensor Registers Test Access Mechanism (TAM) Mechanism(TAM) Core4 Core5 Core6 Test architecture for sensor-based dynamic test scheduling VI. FUTURE DIRECTIONS We are already in a multi-core era and the number of cores is continuously increasing. Test scheduling problem will become even more important for the successful implementation of current and future IC designs. Although much research has been done, many aspects of test scheduling problem still need to be addressed. When CMOS technology moves into below 32nm, thermal issues cannot be ignored by the test scheduling problem. However, in all existing thermal-aware test scheduling schemes, tests are assumed to be run-to-completion. Preemptive testing can potentially reduce test time thus benefiting the test schedule. The difficulty in preemption-allowed thermal-aware test scheduling is thermal profile computation of preempted tests. If cycle-accurate power model is used, separate thermal profile is needed for each partial length of the test thus the computation complexity (and data storage) will increase significantly. New techniques need to be developed for fast and accurate estimation of thermal profile of preemptive tests. In the future, number of embedded thermal sensors are expected to substantially increase. Sensor-based thermal-aware test scheduling is sure to draw more attentions. To improve the efficiency of dynamic scheduling, estimation of temperature information using only sensor readings needs to be developed. Preemptive testing can also be adopted into sensor-based dynamic test scheduling to further improve the scheduling performance. With increasing number of cores, test scheduling techniques for homogeneous cores and heterogeneous cores need to be developed. Opportunities also exist in the areas of test scheduling on Network-on-Chip (NoC) systems and 3-D IC designs, especially for thermal-aware test scheduling.

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