GRID TIED PV/BATTERY SYSTEM ARCHITECTURE AND POWER MANAGEMENT FOR FAST ELECTRIC VEHICLE CHARGING. A Dissertation. Presented to

Transcription

1 GRID TIED PV/BATTERY SYSTEM ARCHITECTURE AND POWER MANAGEMENT FOR FAST ELECTRIC VEHICLE CHARGING A Dissertation Presented to The Graduate Faculty of The University of Akron In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Mohamed O Badawy August 2016

2 GRID TIED PV/BATTERY SYSTEM ARCHITECTURE AND POWER MANAGEMENT FOR FAST ELECTRIC VEHICLE CHARGING Mohamed O Badawy Dissertation Approved: Accepted: Adviser Dr. Yilmaz Sozer Interim Department Chair Dr. Joan Carletta Committee Member Dr. Malik Elbuluk Committee Member Dr. Seungdeog Choi Interim Dean of the College of Engineering Dr. Donald P. Visco Jr. Dean of the Graduate School Dr. Chand Midha Committee Member Dr. Ping Yi Date Committee Member Dr. Kevin L. Kreider ii

3 ABSTRACT The prospective spread of electric vehicles (EV) and plug-in hybrid electric vehicles leads to the need for fast charging rates. Higher charging rates lead to high power demands, which cannot be supported by the electrical grid. Thus, the use of on-site sources alongside the electrical grid for EV charging is a rising area of interest. In this dissertation, a photovoltaic (PV) source is used to support high power EV charging. However, the PV output power has an intermittent nature that is dependent on the weather conditions. Thus, battery storage is combined with the PV in a grid-tied system, providing a steady source for on-site EV charging in a renewable energy based fast charging station. Renewable energy based fast charging stations should be cost effective, efficient, and reliable to support the high charging rates demanded when a large number of EVs are connected to the electrical grid. Thus, this dissertation proposes a novel power flow management topology that aims to decrease the running cost along with innovative hardware configurations and control structures for the developed architecture. A power flow management topology is developed to operate the PV/battery hybrid station at the minimum running cost while extending the battery lifetime. An optimization problem is formulated and two stages of optimization, i.e online and offline stages, are adopted to optimize the scheduling of the batteries state of charge (SOC) while compensating for the forecasting errors. The proposed power flow management topology iii

4 is validated with two metering systems and the power electronic interfacing system is designed accordingly. High power bi-directional DC/DC converters are analyzed, and an interleaved cascaded buck-boost (CBB) converter is chosen and tested under 80 kw power flow rates. Improving the system power quality requires correcting the electrical grid power factor and extracting the maximum power from the PV sources efficiently. To improve the electrical grid power factor, a novel dual switch control structure applied on the developed CBB AC/DC converter is proposed. The developed structure enables a non-distorted input current at overlapping output voltage levels while decreasing the system losses and increasing the conversion efficiency. Lastly, a new proposed PV converter architecture is developed in this dissertation to efficiently track the maximum power provided by the PV sources. The proposed architecture enables each PV element to operate at its local maximum power point (MPP) while processing a small portion of its total generated power through the distributed integrated converters (DICs). This leads to higher energy capture at an increased conversion efficiency while overcoming the difficulties associated with unmatched MPPs of the PV elements. iv

5 ACKNOWLEDGEMENTS I wish to express my sincere gratitude to my adviser, Dr. Yilmaz Sozer, for his guidance, encouragement and support during my graduate studies. His technical and motivational skills have been a source of inspiration throughout my graduate studies and will remain with me for my future career. I am thankful to my professor, Dr. Malik Elbuluk for his technical help and valuable opinions that certainly enriched my research during my studies at the University of Akron. I would like to thank my committee member, Dr. Seungdeog Choi for his help in different times during my PhD studies and for his continuous advice that helped me in shaping my work and planning my research. I am grateful to my professor, Dr. Ping Yi for his continuous advice and for serving in my PhD committee. I am thankful for Dr. Kevin Kreider for his valuable comments and suggestions that enhanced the quality of this work. I would like also to acknowledge my colleague students for their continuous help and for providing the best educational atmosphere and for the enjoyable moments that we spent together during our work. Finally, I would like to thank my family and specifically my parents for their unconditional help and encouragement all the time. v

6 TABLE OF CONTENTS Page LIST OF TABLES... ix LIST OF FIGURES... x CHAPTER I. INTRODUCTION Conventional EV Charging Stations The Evolution of Distributed Generators The Rise of Renewable Sources Photovoltaic Sources as an On-Site Source The Incorporation of the Battery Storage on the Load Side Dissertation Objective Dissertation Organization...10 II. LITERATURE REVIEW The Use of The Battery Storage with PV Systems Power Flow Management of the PV/Battery Grid Tied System The Overall System Architecture Active Power Factor Correction Techniques PV String Power Processing Architectures...26 III. POWER FLOW MANAGEMENT Introduction...38 vi

7 3.2 System Presentation Problem Formulation Power Flow Optimization Validation Results Net Metering and System Configuration Conclusion...71 IV. FAST DC CHARGERS CONFIGURATION Introduction System Configuration Modular Power Interface Design Considerations Using an Interleaving Converter Thermal Management of the Charging System Experimental Implementation Conclusion...94 V. POWER FACTOR CORRECTION USING CBB CONVERTER Introduction DCVM Principle of Operation Converter Design Equations and Characteristics Simultaneous Dual Switch Control Low Frequency and Small Signal Modeling The Construction of The Lookup Table for The Boost Stage Components Design and Simulations Results Experimental Results vii

8 5.9 The PFC Extension for Three Phase Systems Conclusion VI. PV STRING POWER PROCESSING ARCHITECTURE Introduction DPP Concept Proposed DPP Topology System Modeling and Comparison Analysis Experimental Results Conclusion VII. SUMMARY Conclusion Research Contributions Future Work BIBLIOGRAPHY APPENDIX viii

9 LIST OF TABLES Table Page 2.1 Mean inductor current values for current balancing converters in DPP architectures Minimum required components and voltage stress for the DPP configurations Simulation parameters Inductor current ratings for dual stage converters Capacitor voltage ratings for the dual stage converters Efficiency comparison of the bi-directional converters Equations governing the current ripple in the presented CBB converter Sizing of the passive elements in the presented interleaving CBB converter Maximum voltage and current stress applied on the converter elements Comparison of the THD values of the input current for different peak values of I ip. 125 ix

10 LIST OF FIGURES Figure Page 1.1 Three levels of chargers for EV charging stations Conventional centralized electric grid structure Renewable electricity generation by fuel type, (Billion kilowatt-hours) [11] Historical dollars per gasoline gallon in U.S The share of grid connected and off-grid installations [13] An overall image of the proposed hybrid system A conventional configuration for PV/battery grid tied systems Uncontrolled single phase rectifier Simulation waveforms of an uncontrolled rectifier Fully controlled rectifier Bridgeless boost rectifier Single switch active PFC converters Conventional configurations for DICs. A) String controlled. B) Micro-inverters. C) DC/DC optimizers. D) Cascaded DC/DC converters Classification of the DPP Configurations DPP Current balancing converter configurations. A) PV to main bus (non-isolated). B) PV to the main bus (isolated). C) PV to the central inductor. D) PV to PV (ladder). E) PV to the auxiliary bus. F) The non-isolated voltage fed converter x

11 2.10 DPP voltage balancing converter configurations The overall configuration of the hybrid system Forecasting block diagram Battery lifetime for different operating temperatures C BD due to temperature impact C SOC at different SOC averages C DOD at different DOD values Power flow optimization methods block diagram PSO block diagram to optimize the system running cost Batteries SOC space example for DP Error compensation procedure in the DP stage Flowchart of the proposed power flow management structure PV power and load power forecasted for one day of operation Battery SOC scheduling and GT for one day of operation Optimized battery power and grid power for one day of operation The convergence of the global cost in the PSO problem PV power measured over one hour of operation Load power measured over one hour of operation Battery power optimized over one hour of operation Battery SOC scheduling over one hour of operation The power flow results for low load conditions scenario Experimental setup for the proposed PV/battery system Experimental waveforms at the starting conditions for the PV/battery grid tied system Dynamic grid tariff used for the presented scenario during the experimental implementation 65 xi

12 3.24 The optimized simulated and experimental load power scenario results The optimized simulated and experimental grid power scenario results The optimized simulated and experimental battery power scenario results The optimized simulated and experimental PV power scenario results Experimental results for 20s/div (1- Grid converter current, 2- Battery converter current, 3- PV converter current & 4- DC bus voltage) Optimized battery power and grid power for one day of operation using dual metering system A novel reliable configuration for the hybrid system Individual charger modules Various bi-directional converters considered for the comparison study and their classifications Single stage bi-directional DC/DC converters CBB type bi-directional converter CHB type bi-directional converter The simulated interleaving inductor currents and the output current The interleaving CBB converter used for the BCS system Equivalent circuit model of Li-ion battery Li-ion battery operating temperature at different discharging rates BCS experimental setup Input line voltage, current and power from the grid Operation of the DC-DC converter at switching instants DC-DC converter input voltage, output voltage and charging current 93 xii

13 4.14 AC-DC converter efficiency curve with respect to the charging current DC-DC converter input and output voltages and charging current for variable charging commands (0-50A-90A) DC-DC converter input and output voltages and charging current for variable charging commands (0-90A-50A) CBB PFC converter Waveforms of the buck stage intervals Waveforms of the boost converter intervals Maximum input capacitance designed at different D1 and D2 duty ratios Outer control loop for current reference generation The delayed reference signal used for the boost converter switch PWM The simultaneous dual switch control structure for CBB PFC converter Averaged model of the CBB converter Simulated and modeled low frequency output voltage Linearized circuits for obtaining the output responses relative to the source variations. (a) Linearized circuit for input current response to D 1 variations. (b) Linearized circuit for output voltage response to D 1 variations. (c) Linearized circuit for output voltage response to D 2 variations The reference and the actual input current at different values of mr The inductor current at different values of mr Simulation waveforms for the proposed CBB PFC converter at 5 A input current level Input and output current waveforms at different reference current values Current waveforms for the conventional mode selector control at 6 A reference current 125 xiii

14 5.16 Inductor current waveforms for different control structures at 500 W power level The system dynamics for a sudden change in the reference power from 340 W to 680 W The system dynamics for a sudden change in the load from 10 to 5 Ω The system dynamics for a sudden increase in the grid voltage from 170 V to 180 V Voltage and current stress over the active switching elements in the buck stage CBB PFC prototype converter Experimental waveforms of 315 W reference active power while only controlling the buck switch Experimental waveforms of 355 W reference active power using the simultaneous control Experimental waveforms of 1.6 kw reference active power using the simultaneous control at 4.2 Ω load (1- Grid voltage, 2- Grid current & 3- Output voltage, for 10 ms/div) Experimental waveforms at the starting conditions for the system of 460 W reference active power and 4.2 Ω load (1- Grid voltage, 2- Grid current & 3- Output voltage, for 40 ms/div) Experimental waveforms at a varying reference power of 4.2 Ω load (1- Grid voltage, 2- Grid current & 3- Output voltage) Experimental waveforms at a varying input voltage (1-Grid voltage & 2- Grid current) Three phase PFC CBB converter Partial shading example across a PV module composed of five PV elements The I-V characteristics of the five PV elements under partial shading conditions The P-V characteristics of the five PV elements system under partial shading conditions using a centralized MPP tracker xiv

15 6.4 DPP MPP tracker configurations Configuration of the proposed series string DPP topology Theory of operation of the PV elements proposed DICs The inductor current waveform of the DICs in DCM The inductor voltage waveform of the DICs in DCM The inductor current waveform of the DICs in the CCM The input capacitor current waveform of the DICs in the CCM The capacitor current waveform of the DICs in the DCM Potential concentrated shading scenario for the comparative study Comparison study results for the concentrated shading scenario Potential tapering shading scenario for the comparative study Comparison study results for the tapering shading scenario PCB circuit implementation Experimental results for the ladder topology Results for the proposed topology under the first scenario Results for the proposed topology under the second scenario Results for PV2,3 and DIC2,3 under the dynamic performance test Results for PV1 DC bus, load and the duty ratios under the dynamic performance test Overall system architecture xv

16 CHAPTER I INTRODUCTION In this chapter, the challenges of the electric vehicle (EV) charging stations are discussed while highlighting the growing use of distributed generators in the modern electrical grid system. The benefits of the adoption of photovoltaic (PV) sources along with battery storage devices are presented. Finally, the chapter ends with an introduction to the high level architecture of the proposed system along with a briefing of the content for the following chapters Conventional EV Charging Stations The prospective shortage of fossil fuels and the current environmental challenges of reducing the greenhouse gases motivate the extensive research on EV systems [1]. However, the research on EVs is highly impacted by the consumer willingness for switching from using conventional internal combustion engine vehicles to EVs as an alternate means of transport. This willingness is the main factor in predicting the future demand for EVs. In [2], the authors concluded that the charging time is one of the main challenges that the EV industry is facing. Thus, this dissertation focuses on providing novel solutions for reducing the EV charging time by providing fast charging rates. 1

17 Three levels of EV charging (shown in Fig. 1.1) are undergoing research and development in the US. The EV charging levels are classified according to their power charging rates [3]. Overnight charging takes place in level I, as the EVs are plugged to a convenient power outlet (120 V) for slow charging ( kw) over long hours. The main concern of level-i is the long charging time, which renders this charging level unsuitable for long driving cycles, when more than one charging operation is needed. Moreover, from the electrical grid operation point of view, the long charging hours at night overloads the distribution transformers as they are not allowed to rest in a grid system with high number of connected EVs [4]. Level-II charging requires 240 V outlet; thus, it is typically used as the primary charging means for private and public facilities. This charging level is capable of supplying power in the range of kw over a period of 3-6 hours to replenish depleted EV batteries. The time required is still the main drawback in this charging level. Additionally, voltage sags and high power losses in an electrical grid system with a high penetration of level II charging are some of the challenges that are facing its widespread. Control and coordination in level II would reduce the negative impacts of level-ii charging [5]; however, this requires an extensive communication system to be adopted. In general, both levels-i and II require single phase power sources with on-board vehicle chargers. On the contrary, three-phase power systems are used with off-board chargers for level III fast charging rates (50-75 kw). The use of fast charging stations significantly reduces the EV charging time to less than half an hour for a complete charging 2

18 cycle. Additionally, a widespread deployment of fast EV charging stations across the urban and the residential areas would eliminate the EV range anxiety concern [6-7]. However, the high power charging rates required over a short interval of time for level-iii impose a high demand on the electrical grid [8-9]. The current grid infrastructure is not capable of supporting the desired high charging rates of level-iii. Thus, achieving fast charging rates while solely relying on the electrical grid does not only require the improvement of the charging system, but also the improvement of the electrical grid capacity. Additionally, drawing large amounts of current from the electrical grid will increase the utility charges especially at the peak hours and consequently will increase the system cost. A) Level I Charging B) Level II Charging C) Level III Charging Figure 1.1. Three levels of chargers for EV charging stations. The establishment of a distributed generator (DG) behind the meter on the fast charging station site is a feasible solution to the aforementioned challenges. In such a 3

19 system, a power generation facility produces electrical supply that is intended for on-site use [10] The Evolution of Distributed Generators From the beginning and throughout the history, the electric supply industry evolved around basic principle of centralized generation. In this centralized scenario, the electrical power is supplied from large power plants through long transmission lines and massive distribution network to be delivered to the consumers as shown in Fig Figure 1.2. Conventional centralized electric grid structure. A few decades ago, a number of developments began to change the basics of operation of the electrical grid industry leading to the rise of DGs. The ambitious targets of the higher deployment rates of the DGs into the electrical pool is achievable due to the advanced technologies and the enhancements in the power electronics and the smart grid fields. Additionally, new regulations and policies are continuously issued favoring the distributed generation and the net metering concepts. However, the type of energy used in fueling the deployed DG sources on the demand side is a decisive factor in the economic viability of the DGs concept in today s electrical distribution market. 4

20 1.3. The Rise of Renewable Sources The renewable energy sources (RES) have a distinct advantage in their ability to be deployed in residential and urban areas due to their environmental friendly operation and minimal maintenance requirements. Consequently, one of the main key contributors to the recent growth of the DGs market is the rise of the RES technology. Renewable energy is considered to be the fastest growing sector in the power generation market as it is expected to steadily expand its share in the market in the next five years [12]. The historical and projected generation of renewable energy sources for different types of fuels is shown in Fig. 1.3, showing their steady growth and upside potential. Figure 1.3. Renewable electricity generation by fuel type, (Billion kilowatthours) [11]. Several factors are driving the steady rising use of RES as follows: The global concerns about climate change and the need to reduce greenhouse gas emissions. 5

21 The national independence of the fossil fuels exportations associated with higher penetration of renewable energy sources. The rising retail tariffs accompanied with the global rise of the oil prices as shown in Fig Figure 1.4. Historical dollars per gasoline gallon in U.S Photovoltaic Sources as an On-Site Source Solar energy is considered to be one of the most effective resources that attracted much attention due to its ubiquity and sustainability. The most common application for the use of solar energy is the adoption of PV panels. PV panels gained their widespread usage due to their unique capability of directly transferring solar energy into electrical energy without the need of mechanical auxiliary systems. Thus, PV panels are effectively utilized in different power generation levels starting from low-power domestic applications to mega power PV based power plants. The grid-connected PV installations are utilized with deeper penetrating levels compared to the standalone PV installations. This is due to the continuous reliance on the 6

22 electric grid as a stable source/load that can compensate for the PV power fluctuations. The share of grid-connected and off grid installations of the top PV installing countries is shown in Fig. 1.5 verifying the high favorability of grid-connected PV installations in recent years. In the proposed system, PV operates as grid-tied DG source. Solar energy is a preferable DG source in EV charging applications for two reasons: 1. The PV panels are more effective than other renewables (e.g. wind energy) in populated and residential areas due to their noise free operation and low maintenance requirements. 2. PV panels generate most of their energy during the highly priced grid tariff hours of the electrical grid. Thus, the EV charging stations can offset the high costing electricity with solar energy during the peak hours. Figure 1.5. The share of grid connected and off-grid installations [13]. 7

23 1.5. The Incorporation of The Battery Storage on The Load Side The PV power production is highly impacted by the ambient temperature and the sun insolation levels. Thus, the PV power suffers from discontinuity over a day of operation in addition to an intermittent nature that can occur over short time intervals (minutes to hours). Consequently, connecting the PV panels directly to the load without any subsidiary systems leads to a negative impact on the performance of the connected electrical loads. Storage devices can play a crucial role in stabilizing the output power of the solar energy. In this dissertation, energy storage devices such as batteries are suggested to be combined with PV sources to sustain the continuous power supply to the connected loads regardless of the power fluctuations in the PV sources [13]. Additionally, the integration of the hybrid PV-battery system into the grid allows for a higher degree of deregulation on the demand side, which is a key factor in achieving lower running costs at a higher performance Dissertation Objective The objective of this dissertation is to provide a renewable energy based fast charging solution for a transportation infrastructure with a high population of EVs. An optimal power flow management and an efficient configuration of the proposed system are desirable to supply the demanded high power charging rates. Thus, new topologies are presented in this dissertation as follows. A novel power flow management is proposed in order to run the system using the minimum running cost while extending the battery lifetime. Accordingly, a fast charging converter is presented and tested to allow for high EVs power charging rates with an improved degree of 8

24 reliability. A power factor correction (PFC) feature is enabled in the fast charging converters by introducing a new control structure. This feature leads to an improvement of the electrical grid power quality as well as a reduction in the size of the interconnecting components in the proposed system. Finally, a novel configuration applied on the PV series string is developed to increase the system efficiency and reduce its cost by the means of reducing the amount of the processed current in the power converters while extracting the maximum PV power. Electric Grid Solar Panels Battery Storage Electric Vehicles Figure 1.6. An overall image of the proposed hybrid system. An overall image of the proposed PV/Battery grid-connected EV charging station is shown in Fig The presented hybrid system is utilizing the DG technology by the adoption of the PV/battery sources on the demand side. These DG sources are connected to the electrical grid in a grid-tied system to provide fast charging power rates to the EVs. 9

25 1.7. Dissertation Organization The dissertation is organized as follows; Chapter II presents a summary of the main literature review used in this research. The proposed power flow management system for the PV/battery grid tied EV charging station is presented in Chapter III. The off-board fast DC/DC charger technology adopted in the proposed hybrid system is shown in Chapter IV. The novel PFC topology applied on the chosen DC/DC converter is presented in Chapter V. A novel differential power processing architecture is shown in Chapter VI to extract the maximum power from the PV sources. Finally, the integrated configuration of the designed subsystems draws the conclusion of the work in Chapter VII along with the research contributions and the suggested future research topics. 10

26 CHAPTER II LITERATURE REVIEW In this chapter, a summary of the studied literature is presented for the selected topics covered in this dissertation. However, detailed comparison analysis of the proposed work and the conventional methods are provided in the following chapters The Use of the Battery Storage with PV Systems One of the main challenges of the adoption of PV power sources is the lack of a stable and continuous electrical power production. The PV power sources suffer from an intermittent and a stochastic nature that is driven by the continuous variations in the solar insolation levels as well as the ambient temperature values. Additionally, the day-night cycles are highly impacting the ability of the PV sources to be used in standalone configurations. Thus, PV sources are marked as non-dispatchable units. Consequently, new solutions are needed to be adopted in PV systems to balance the electrical grid power flow, and provide steady power to the connected loads. One of the applicable solutions for the aforementioned challenge is the design of a hybrid RESs system using various RESs which can relatively offset a portion of the local fluctuations in every generation unit. However, this requires an appropriate selection of the 11

27 most suitable generation technologies as well as a proper sizing of the (RES) [14]. The combination of PV sources with wind energy is explored in [15]. However, such a system requires either the insertion of storage devices or a connection point to the electrical grid in order to continuously support the necessary loads. The authors in [16] presented the use of a PV source with fuel cells to meet the requirements of a residential load. In doing so, a reserve capacity had to be maintained at the PV source to supply the load changes as the fuel cells technology instills a slow dynamic response. This leads to a deviation between the PV maximum power point (MPP) and the system operating point. To accommodate those challenges, a hybrid system composed of PV/fuel-cells/ultra-capacitors is used in [17]. In this study, the ultracapacitors are selected due to their fast dynamics response, which leads to their ability of mitigating the rapid fluctuations of the PV power while continuously tracking the PV MPP. However, this configuration fails to meet the load demands during extended hours of low insolation level conditions (e.g. night hours or shady days). Storage devices can play a key role in the integrated RES. The literature contains different examples of RES combined with energy storage systems. Various energy storage technologies are studied in the literature to be connected with the wind generators in order to provide steady output power to the electrical loads. In [18], the authors presented a wind turbine combined with hydrogen cells and supercapacitors. In that study, the developed control system coordinates the power exchange between the sources. In such a system, the wind turbine can provide ancillary services to the electrical grid, a feature that grows more interest due to the deep penetration of RES in the modern electrical grid system. Battery 12

28 storage, ultra-capacitors, and hydrogen cells are some of the energy storage solutions analyzed for wind applications [19-21]. The recent growth of the PV power in the electrical generation market along with the future predicted PV installation plans drive the need for transforming the current PV panels from current controlled sources into PV systems [22]. The desired PV systems should be able to provide grid ancillary services, i.e voltage control, frequency regulation, low and voltage ride through [23-25]. The use of storage devices coupled with the PV sources can provide the necessary means to accommodate the aforementioned functions [26-28]. Additionally, the careful selection of the energy storage technology along with a careful design of its size allows for a higher degree of deregulation on the demand side, thus, achieving lower running costs [29]. The authors in [30] introduced the use of distributed batteries in a grid-tied PV power plant to improve the energy production. Achieving a constant power production from the PV power plant is the main defined objective of inserting energy storage system in the work shown in [31]. An energy management strategy is proposed in [32] to control a PV power plant by allowing it to generate constant power by hours. This is plausible due to the insertion of energy storage devices in the system. Constant power generation allows for the system participation in the electricity market pools. In [33], a storage battery is added to the grid-connected PV system to reduce the PV power fluctuations in a defined range within a particular period of time while maximizing the revenue. This is motivated by meeting the utilities regulations and restrictions on the PV power injected to the grid. The battery sizing is discussed in [34], where the objective is to maximize the cost associated with the power purchase from the electric grid. The authors in [35] performed 13

29 battery sizing analysis with the same objective and while accounting for the battery degradation cost in order to extend the system lifetime. In [36], eight different types of batteries were analyzed for their energy return factor and overall efficiency when used in renewable energy based systems. Therefore, from the literature, multiple lines of research point to the advantages of integrating battery storage devices with PV power in order to attain stable power supply at a minimal operating cost. In this dissertation, energy storage batteries are coupled with PV panels in a grid-tied system. The proposed hybrid system is designed to provide means of fast charging for EVs Power Flow Management of the PV/Battery Grid Tied System In order to design the proposed system configuration, the flow of the power between the four main elements in this system needs to be explored. The main elements are the connecting electrical grid, the PV sources, the battery storage and the EVs charging load. The decision on the need of a bi-directional power flow power electronic systems along with their sizing requirements can be decided based on power flow management. Consequently, Chapter 3 explains the proposed power flow management topology used in this dissertation. In this subsection, the research attempts to solve the power flow management problem are introduced and their applicability on the studied application is discussed. The combination of the battery storage with the PV offers an infinite number of solutions to the power flow problem during different time intervals, all of which are constrained by supplying the connected load with the demanded power. Thus, solving the 14

30 operation scheduling of the hybrid system is the main interest of research in several publications. Conventionally, the power flow in a grid-connected PV/battery system is predefined by heuristic rules that consider the load demand, the PV insolation levels and the utility off-peak hours [37]. However, a dynamic grid tariff complicates the solution of the proposed system further. In a dynamic grid tariff system, the operation of the PV/battery system using the simplified heuristic rules will provide running cost solutions that largely deviate from the minimal cost operation. Thus, the research in this area has taken on an accelerated path. In [38], a Lagrangian relaxation technique is applied to determine the optimal hourly battery charging or discharging current, where the objective is to maximize the contribution of the hybrid system to the grid. The proposed technique in [38] assumes there is no dispatch cost associated with the PV/Battery output power. This leads to the disaccounting of the battery degradation cost and its advisable operating conditions. Additionally, the formulation of the problem is limited to a thermally based electrical grid system. The formula cannot be generic as Lagrangian technique is only restricted to linear quadratic problems. The authors in [39], used a dynamic programming (DP) approach to optimize the power flow while considering the state of health (SOH) of the battery. This approach requires high memory allocation in the used processor as the system states are discretized into small steps over a long period of time. Additionally, the proposed presentation of the battery aging cost relies only on the SOH of the battery which is a function of the battery 15

31 depth of discharge (DOD) and it is only effective during the discharging process. The simplified presentation of the aging cost function ignores the temperature impact on the battery performance as well as the average state of charge (SOC) of the battery. Moreover, the applicability of the system in real time is highly dependent on the forecasting accuracy due to the lack of an error compensation stage. A predefined rule based model is presented in [40] where the battery energy storage is integrated into the renewable energy system in order to enable the PV source to act as a dispatchable unit on an hourly basis. The objective of the battery storage utilization in this paper leads to solutions that are not necessarily minimizing the running cost. Additionally, the system is sensitive to the solar power forecasts. From the ongoing research in the field of power flow management for PV/battery grid tied systems, few conclusions can be drawn. First, the problem formulation should account for the aging factor of the battery in order to extend the battery lifetime, and thus, increase the system reliability. The desired power flow management topology has to accommodate non-linear functions. This allows the generalization of the developed topology on different operating scenarios. An online error compensation stage has to be included in the topology to allow the system to operate effectively at mismatching conditions and forecasting deviations. Lastly, the online optimization stage should be designed to operate with low computational time, which makes it easily integrated into real-time controllers (e.g. DSPs, FPGAs, etc.). 16

32 2.3. The Overall System Architecture The conventional architecture of a PV/battery grid tied system [41] along with the power flow direction in the power electronic interfacing systems are shown in Fig However, the architecture of the PV/battery grid-tied system proposed in Chapter III in this dissertation is configured based on the power flow management system findings. PV String Battery Storage = = DC/DC Converter = = PPV PBat AC/DC Converter = PG PL = = Grid EVs Charging Figure 2.1. A conventional configuration for PV/battery grid tied systems Active Power Factor Correction As can be shown in Fig. 2.1, the grid should be capable of supplying power to the DC system, which is composed of the storage batteries and the EVs. Consequently, the 17

33 AC/DC rectifier is required to control the grid power factor that yields an efficient operation and a lower current stress. Power factor is defined as the ratio of real power to the apparent power in AC systems as shown in (2.1). In the proposed configuration, PF is the mains source power factor, P is the grid real power, I rms is the grid rms current, V rms is the grid rms voltage, and S is the grid apparent power. The apparent power is composed of both the real power and the reactive power (Q) as shown in (2.2). PF = P S = P V rms I rms (2.1) S = P 2 + Q 2 (2.2) PF = K e K d (2.3) K e = cos Θ (2.4) K d = I rms(1) I rms (2.5) The power factor can also be expressed as a product of two factors as shown in (2.3). The factors are the displacement factor (K e ) and the distortion factor (K d ). The displacement factor accounts for the displacement of the current waveform with respect to the voltage waveform, while the distortion factor accounts for the shape of the current. The displacement and the distortion factor equations are shown in (2.4) and (2.5), where I rms(1) is the rms value of the fundamental grid current, and Θ is the angle difference between the instantaneous grid voltage and current respectively. 18

34 Problem definition It is desirable to operate the system at the maximum possible power factor at all times unless ancillary services are required for the grid. High power factor yields higher system efficiency due to the circulation of less current for the same amount of real power. Additionally, the lower processing current allows the interfacing power electronic components to be designed for lower current stress, and thus, reduces the system cost However, the presence of inductive and capacitive components in the power electronic circuits leads to lower displacement factor. Moreover, the high-frequency switching of the used power electronic converters contributes towards a lower distortion factor. This is due to the fact that high-frequency components of the grid current will be present in the system. Uncontrolled diode rectifier The uncontrolled rectifier is composed of four diodes so that the sinusoidal voltage can be rectified in the DC side as shown in Fig The load requires a stable DC bus voltage, thus a bulky capacitor is often used in the DC side. The input current of such a rectifier circuit comprises of large discontinuous peak current pulses that result in a high input current harmonic distortion. This occurs as the rectifier conducts only for a short period of time when the AC mains voltage is higher than the capacitor voltage. The results of this system are shown in Fig. 2.3, where the low power factor and the high current stress are demonstrated for a 170 V peak AC voltage, 300 μf capacitor, and 100 Ω resistance. 19

35 I o I i V i V o C o R o Figure 2.2. Uncontrolled single-phase rectifier. High grid power factor and low distortion in the input current is plausible using the concept of PFC. PFC is based on increasing the power factor of the AC power by either the use of external components or by the appropriate control of the already in-use components. PFC is critical in the proposed configuration of the PV/battery grid tied system in order to increase the system efficiency, reduce the components sizing and decrease the power electronic converter cost. Thus, Chapter 5 in this dissertation discusses the novel PFC topology used to achieve unity power factor with reduced size converter and high efficiency. In the following subsections, the PFC types are defined and few of the most applied active PFC topologies are presented. 20

36 Figure 2.3. Simulation waveforms of an uncontrolled rectifier PFC types PFC can be classified into two types; passive PFC, and active PFC. An introduction to the main concept of both types followed by a summary of the advantages and drawbacks of each one of them is presented in this subsection. Passive PFC In a passive PFC system, only filtering passive elements are used in addition to the diode bridge rectifier shown in Fig. 2.2 to reduce the harmonics and correct the phase angle of the line current. The main notion of this PFC type is to design a filter that will pass only 21

37 the fundamental frequency signal while cutting off all the undesired frequencies. The advantages of the passive PFC systems can be summarized as follows: The simple structure as no feedback control is required. The system does not suffer from high electromagnetic interference (EMI) in comparison to the active PFC type. Low cost, due to the need for the construction of only passive filters without any additional semiconductor components. Low switching and conduction losses in the system due to the simple structure and the few components used in the system. While the disadvantages of passive PFC are: Large size due to the high requirements of the passive filters. Poor dynamics response associated with the time lag of the passive elements. Output voltage regulation is not achievable. Current phase shift repeatedly takes place while filtering the harmonics due to the nature of the used passive elements. The current shape is highly sensitive to the load changes. Active PFC Active PFC systems are realized by controlling a power electronic interfacing system to achieve pure power factor. This is commonly done by controlling the grid current so that its waveform will be in synchronization with the grid voltage. Filtering passive elements are still required in order to decrease the EMI associated with the high-frequency 22

38 switching of the semiconductor devices in the power electronic system. The advantages of active PFC systems are: Lower weight and smaller size compared to passive PFC systems, due to the lower capacitance and inductance requirements needed for the used filtering elements. Higher power factor can be achieved due to the full control over the grid current and the ability to compensate for any phase shifting. Less sensitive to the load variations. On the other hand, some of the main drawback of the adoption of active PFC systems are: More complicated control is needed. Higher cost due to the need for semiconductor and high-frequency switching devices Active PFC topologies In this dissertation, a method of active PFC is proposed, due to its ability to achieve higher power factor and lower harmonic values. Additionally, the power electronic interfacing system is already in use with the proposed configuration. Thus, in this subsection, few of the most commonly applied active PFC are presented. A. Fully controlled bi-directional rectifier This is the most commonly used rectifier in the industry as it exhibits high power factor and voltage regulation characteristics. This rectifier (Fig. 2.4) is the easier to design for three-phase systems. Additionally, it provides the ability to feed the power back to the mains voltage as it is a bi-directional rectifier. The main drawback of this inverter is the 23

39 high cost and the control complexity, especially if bi-directional power flow is not necessarily needed [42]. I o I i V i V o C o R o Figure 2.4. Fully controlled rectifier. B. Bridgeless boost rectifier The bridgeless boost rectifier [43] shown in Fig. 2.5 is a single stage rectifier, where the current flows only through two semiconductors in every path. This rectifier is also known as half controlled rectifier as only half of the semiconductor devices are controlled. The main concept of the rectifier is to control two switches alternatively at the positive and negative voltage cycles. Thus, this rectifier provides a simpler control approach to the fully controlled rectifier. The main drawback is that the rectifier diodes operate under high voltage and high forward current conditions, and thus, they suffer from severe reverserecovery problems [44]. Additionally, this topology is only suitable for voltage boosting applications. C. Single-switch active rectifiers Another family of active PFC rectifiers is the single switch rectifiers. The rectifiers in this category correct the AC mains power factor from the DC side after the rectifier 24

40 stage. The benefits of this topology, are the ease of control and implementation, the low cost, and the high power factor operation. I o I i V i V o C o R o Figure 2.5. Bridgeless boost rectifier. Three types of single switch active rectifiers are shown in Fig The boost based type is the most commonly used due to the continuity of the input current when compared to both the buck and the buck-boost types. However, the output voltage has to remain greater than the AC mains voltage at all times. For low voltage applications, the buck based type is more suitable, however, the discontinuity of the input current has to be filtered using bulky passive filters. The buck-boost based rectifier offers the advantage of an overlapping output voltage, however, the opposite polarity at the output renders it unsuitable for high power applications. The active PFC topology in this dissertation is proposed in Chapter 5. The proposed topology makes use of the cascaded buck-boost converter (CBB) to achieve high power factor for an overlapping voltage while simultaneously controlling both of the converter switches. 25

41 I o I i V i C o V o R o a) Boost based. I o I i V i C o V o R o b) Buck based. I o I i V i C o V o R o c) Buck-boost based. Figure 2.6. Single switch active PFC converters PV String Power Processing Architectures Increasing the power quality of the proposed system does not only require enhancing the grid power factor but it also requires extracting the maximum power from the PV sources while maximizing the system efficiency. Thus, the configuration and the control 26

42 of the PV panels to provide the maximum available energy is discussed in Chapter 6 and some of the used literature is discussed in this subsection. The research on the photovoltaic (PV) systems has taken on an accelerated pace and the PV modules prices are continuously falling due to the mass production and the technological improvements [45, ]. Yet, more research is still required to investigate new topologies capable of capturing more energy from the PV systems by using relatively low-cost interfacing systems. This should help in decreasing the price per watt of the PV system from 11.2 c/kwh in 2013 to 6 c/kwh in 2020, which is the goal set by the US department of Energy [143]. In order to maximize the energy captured from the PV sources, they are desired to operate at their MPPs [45, ]. Thus, various power electronic interfacing systems are studied in the literature [46, 148]. PV panels are often connected in series in the literature as well as in the proposed PV/battery grid tied system. The series connection is contributory to generating a relatively high DC bus voltage that is capable of supplying power to both; the electrical grid and the battery storage devices at a high system efficiency. Two different families of power electronic systems are generally used in connecting the PV source to the load. The centralized and the distributed integrated converter (DIC) technologies. The centralized technologies aim at connecting all the PV panels to a single power electronic converter. This system benefits from low price and simple control as discussed in the literature [46]. However, a series string of PV elements is highly sensitive to the mismatch in the output power of the series connected PV elements. These mismatch conditions appear due to partial shading, aging of the PV panels, silicon impurities, and 27

43 dust accumulation [47-48, 54, and 148]. The non-identical performance of the series connected PV elements leads to one of two possibilities; the shaded PV elements will impose their low current on the series PV string or the unshaded cells will impose their high current on the shaded cells, causing them to operate at negative polarity. In both cases, low productivity is expected with the use of centralized converters due to the inability of the system to capture the maximum energy from the connected PV elements. Thus, DICs for PV systems are being developed for maximum energy capture. Also known as submodule integrated converters (SMICs), the DICs are used to individually track the MPPs of the PV elements in order to capture more solar energy by allowing the PV elements to operate at different current and voltage levels. Different configurations of the DICs are studied in the literature and applied in the solar PV industry as shown in Fig The first shown configuration in Fig. 2.7.a is a string controlled one [ ]. In this configuration, every PV element is equipped with a parallel diode in order to prevent the imposition of negative polarity on the underperforming PV elements. Although this structure is the cheapest and the simplest to implement, but it suffers from high power losses due to the complete shutdown of the shaded PV modules. The micro-inverter technology is applied in the next configuration [ ], in which, every PV module is connected to the grid through its local inverter. This structure allows for individual and independent MPP tracking. However, an isolating transformer would be necessary due to the high voltage transformation ratio needed. This leads to an additional cost and a lower system efficiency. 28

44 PV 1 PV 1 PV 1 PV 1 DC AC DC DC DC DC PV 2 PV 2 PV 2 PV 2 DC AC DC DC DC DC PV 3 PV 3 PV 3 PV 3 DC AC DC DC DC DC DC AC DC AC DC AC a) b) c) d) Figure 2.7. Conventional configurations for DICs. a) String controlled. b) Microinverters. c) DC/DC optimizers. d) Cascaded DC/DC converters. The DC/DC optimizer shown in Fig. 2.7.c is introduced to boost up the PV module voltages without the need for any interfacing transformers, this leads to a high voltage transformation ratio on the DC side [ ]. Additionally, all the PV power is processed through dual stages, which increases the system power losses. Finally, the cascaded DC/DC converters are shown in Fig. 2.7.d where the output of the DC/DC converters are connected in series to avoid high voltage transformation ratio [149, ]. However, the power is still processed across two power electronic stages, and a more complicated control needs to be applied to coordinate the DC bus capacitors current flow. 29

45 Although the mismatch current between the series connected PV elements is a fraction of their total power, but the configurations shown in Fig. 2.7 process the total PV elements power through their interfacing power converters for individual MPP tracking. From the aforementioned, it can be concluded that a favorable solution for the mismatch losses is to connect the PV modules in a series string as shown in Fig. 2.7.A, while operating them at different current and voltage levels with a minimal power processing capability. The series connection is crucial to generate sufficient DC bus voltage to drive the grid inverter efficiently. The capability of the PV modules to operate at different MPPs will ensure that all the available solar power is captured. Finally, the minimal power processing contributes to a higher system efficiency due to the reduced losses. Differential power processing (DPP) topology is introduced in the literature to achieve these objectives. In this subsection, various DPP configurations are categorized and evaluated. DPP Configurations Current Balancing Converters Voltage Balancing Converters PV to main bus (nonisolated) PV PV to to Central main Inductor bus (isolated) PV to auxiliary bus PV to PV (ladder) Switched capacitor converters Virtual Parallel Conv. Figure 2.8. Classification of the DPP Configurations. The DPP configurations are classified into two main categories; the current balancing, and the voltage balancing configurations as shown in Fig

46 DPP Configurations A. Current Balancing Converters The current balancing converter configurations differ in the regeneration of the differential energy captured in the system as shown in Fig Independent local control can be implemented on the PV to main bus (PVMB-I and PVMB-NI) configurations shown in Figs. 2.9.a and 2.9.b as the mismatch power is regenerated to the DC bus [48]. However, all the DICs have to be either sized to the DC bus voltage, or an isolation transformer has to be inserted. This increases the weight and the cost of the system. L 4 M 4a M 4b M 4b PV 4 C i4 T 4 PV 4 C i4 M 4a L 3 M 3b M 1a M 1b PV 3 C i3 M 3a I main PV 3 C i3 T 3 I main L 2 Central Converter Central Converter M 2b M 2a M 2b PV 2 C i2 M 2a PV 2 C i2 T 2 L 1 M 1b PV 1 C i1 M 1a PV 1 C i1 M 1a T 1 M 1b a) b) Figure 2.9. DPP Current balancing converter configurations. a) PV to main bus (nonisolated). b) PV to the main bus (isolated). c) PV to the central inductor. d) PV to PV (ladder). e) PV to the auxiliary bus. f) The non-isolated voltage fed converter. 31

47 D 4a M 4b D 4b PV 4 C i4 PV 1 C i1 M 1a M 3a D 3a M 3b D 3b L 1 PV 3 C i3 M 2a C i2 PV 2 M 1b I main M 2a D 2a M 2b D 2b I main Central Converter L 2 Central Converter PV 2 C i2 M 2b PV 3 C i3 M 3a M 1a D 1a D 1b L 3 PV 1 C i1 C i4 PV 4 M 3b L c) d) L 3 M 4a M 4b PV 4 C i4 T 4 C 3 M 3 PV 3 D 3 M 1a M 1b PV 3 C i3 T 3 I main L 2 I main M 2a M 2b Central Converter C 2 M 2 D 2 PV 2 Central Converter PV 2 C i2 T 2 PV 1 C i1 M 1a T 1 M 1b C B C 1 PV 1 e) f) Figure 2.9. DPP Current balancing converter configurations. a) PV to main bus (nonisolated). b) PV to the main bus (isolated). c) PV to the central inductor. d) PV to PV (ladder). e) PV to the auxiliary bus. f) The non-isolated voltage fed converter. (Cont'd.) The PV to central inductor (PVCI) configuration (Fig. 2.9.C) is solving some of those problems [49], however, a more complicated control algorithm needs to be applied. Additionally, the inductor current has to be sized for high values especially at high shading factors. Moreover, the mismatch losses are considered to impact only the MPP currents with no effect on the voltage. 32

48 To mitigate those challenges, the PV to PV (ladder) configuration is shown in Fig. 2.9.D [50]. In this configuration, the PV mismatch power is circulated between the PV modules. However, there is a decoupling between the neighboring PV modules. Thus the current processed in every MIC is always impacted by the shading factor of the neighboring modules, which leads to higher current stress relative to the PV to main bus configuration. A PV to an auxiliary (virtual) bus (PVAB) configuration is shown in Fig. 2.9.E [51].This configuration reduces the amount of current processed in every MIC compared to Fig. 2.9.D. However, the insertion of an electrolytic capacitor in the line creates a single point of failure in the system which decreases the reliability. Additionally, the use of isolated DICs is necessary and a coordinated control needs to be applied. Lastly, the non-isolated voltage fed (NIVF) configuration is shown in Fig. 2.9.F [52]. The main conceptual idea of this configuration is that the mismatch power between the panels will be fed as an extra voltage to the DC bus. One of the main shortcomings in this configuration is the high voltage fluctuations on the DC bus which can be stabilized using a passive filter or a high-frequency DC/DC converter. The mean inductor current values of the current balancing converters are shown in Table 1, where D is the designated converter duty ratio, j is the intended PV module, and SF is shading factor of the presented DPP configurations. 33

49 Table 2.1. The mean inductor current values for current balancing converters in DPP architectures. PVMB (NI) PVMB (I) PVCI I pvj+1 I pvj I pvj+1 I pvj SF. I pvn ladder configuration PVAB NIVF I pvj+1 I pvi + D j 1 I Lj 1 + (1 D i+1 )I Li+1 I pvj+1 I pvj I string I pvj B. Voltage Balancing Configurations The voltage balancing converters achieve DPP by balancing the voltages of the neighboring PV modules. Two different voltage balancing DICs are shown in Fig The PV balancers (PVB) configuration is shown in Fig a and introduced in [53]. The concept of the PV balancers configuration is based on the slight variation of the PV MPP voltage under mismatch conditions compared to the current variations. Thus, (2.6) can be written where V DC is the total DC bus voltage, V Oi is the converters output voltage, and n is the number of PV modules in the string. However, the DC bus voltage needs to be controlled carefully in order to enhance the system efficiency. The local MPP may not be reached for all the modules, but they will always operate close to it. n V Dc = (V PVi + V Oi ) (2.6) i=1 The switched capacitor converter (SSC) (Fig b) is introduced in [54]. The configuration of this topology is comparable to the PV ladder configuration shown in Fig. 2.9.d, as the intermediate inductor is replaced with a ceramic capacitor to decrease the size and the cost of the system. The voltage is regulated to enforce a voltage ratio of 1:1 across 34

50 all the PV modules to force them to operate near their designated MPPs, thus (2.7) is applied. M 3a M 2b PV 3 C i3 C i2a T 2 C o2 M 2a PV 2 I main Central Converter PV 2 C i2 M 3b M 2a C b2 I main Central Converter M 1b M 4b C b1 C i1a T 1 C o1 M 1a M 1a PV 1 C i1 PV 1 M 1b A) Figure DPP voltage balancing converter configurations. n V Dc = V PVi i=1 B) (2.7) R eff = 1 f sw C X (2.8) 1 f o = (2.9) 2π L x C x One of the main drawbacks of this topology is that it is mostly effective with fixed conversion ratio, thus the converter is less reliable for frequent weather fluctuations. Additionally, the high switching frequency is desirable as shown in (2.8). Another limitation of this method is the existence of high current spikes that are associated with the hard switching of the capacitor converter. In order to mitigate some of those effects, a 35

51 resonant ladder converter is proposed in [54], where the intermediate capacitor is replaced with an impedance Z x, and the circuit is switched at resonant frequency as in (2.9) DPP Control Approaches and Components Sizing The applicable control approach, the required amount of active and passive components as well as the converters sizing are some of the decisive elements in the comparison between different DPP configurations. A. DPP Control Approaches Local control can be applicable to PVMB, PVSS, and ladder configurations. However, it is important to note that current passing in every converter in the ladder configuration is influenced by the mismatch in the other converters. Thus, the converters control is local but dependent on the neighboring control signals. Centralized control is necessary to be used with the PVCI and the PVAB configurations in order to balance the amount of the centralized inductor current and the centralized capacitor voltage respectively. The need to balance the PV modules voltage in the voltage balancing converters arises the necessity of using a centralized control signal to set the common PV module voltage. This is commonly done by the central converter which tracks the string MPP. However, this control algorithm varies with the NIVF topology as the local MPP is tracked for every PV module locally. 36

52 B. DPP Components amount and Sizing Table 2.2. Minimum required components and voltage stress for the DPP configurations. Configurations PVMB-NI PVMB-I PVCI Ladder Min. No. of Required Converters (N-1) + Central (2N-2 switches & N-1 inductors) (N-1) + Central (2N-2 switches & N-1 transformers) (N) + Central (4N-2 switches & 1 inductor) (N-1) + Central (2N-2 switches & N-1 inductors) Switch voltage ratings V DC V DC N 1 N 2 V pvi V pvi N 2 N 1 V DC N j V pvi V pvi i=1 i=1 V pvj + V pvj+1 Configurations PVAB NIVF PVB SCC No. of Required Converters (N) + Central (2N switches & N inductors) (N-1) + Central (2N-2 switches & N-1 inductors) (N) + Central (2N switches & N transformers) (N) + Central (2N switches & N-1 capacitors) Switch voltage ratings V AB N 1 N 2 V pvi V pvi N 2 N 1 V AB V pvj 1 D j V Oj (1 N 1 N 2 ) + V pvi j (V pvi + V Oi ) i=1 (V pvj + V Oj ) N 1 N 2 V pvj where V DC is the DC bus voltage, N is the number of PV modules in the string, j is the intended PV module, and V AB is the auxiliary bus voltage, of the presented DPP configurations. It is concluded from this subsection, that the desired DPP should consider low current processing and low voltage stress on the DICs while tracking the individual MPP of the connected PV elements. 37

53 CHAPTER III POWER FLOW MANAGEMENT 3.1. Introduction High required charging rates lead to high power demands, which may not be supported by the grid. Thus, the PV source and the storage battery are coupled together in a grid tied system to provide the EVs with the needed charging power rates. In order to design the system configuration, it is necessary to evaluate the amount of the processed power and the direction of power flow in each of the power electronic system used in the system. Thus, in this Chapter, An optimal power flow technique of a PV-battery powered fast EV charging station is presented to continuously minimize the system operating cost. The objective is to provide a power flow solution to support the growing need of fast EVs charging rates using a grid-tied PV/battery system. An optimization problem is formulated along with the required constraints and the operating cost function is chosen as a combination of electricity grid prices and the battery degradation cost. In the first stage of the proposed optimization procedure, an offline particle swarm optimization (PSO) is performed as a prediction layer. In the second stage, dynamic programming (DP) is performed as an online reactive management layer. 38

54 The forecasted system data is utilized in both stages to find the optimal power management solution. In the reactive management layer, the outputs of the PSO are used to limit the available state trajectories used in the dynamic programming (DP) and, accordingly, improve the system computation time and efficiency. Online error compensation is incorporated into the DP and fed back to the prediction layer for necessary prediction adjustments. Simulation and a 1 kw prototype experimental results are successfully implemented to validate the system effectiveness and to demonstrate the benefits of using a hybrid grid tied system of PV/battery for fast EV charging stations System Presentation The initial configuration of the PV/battery hybrid system explored in this chapter is shown in Fig The PV string, the battery storage, the EV load, and any other auxiliary loads are connected to the DC link through their individual DC/DC converters. The electric grid is connected to the DC link through a bi-directional AC/DC converter as shown. The battery storage DC/DC converter is a bi-directional power electronic interfacing converter to allow smooth operation during the battery charging and discharging modes. However, the uniqueness of this study is the reliance of the proposed configuration on the power flow management results. Thus, the shown configuration will be developed at the end of this chapter to reflect the findings of the optimal power flow operation through one day of operation. The battery power (P b ) is assumed to be positive during discharging and negative while it is being charged. The load power (P L ) is the summation of the EVs load and the auxiliary station loads. In this dissertation, the load power (P L ) is always positive as the 39

55 EVs do not supply power back to the grid nor to the battery storage. The grid power (P G ) is positive when the grid is supplying the station loads, while it is negative when the grid is fed from the on-site sources. The PV power is always controlled to track the maximum power point and the load power is always desired to be supplied. PV String Battery Storage Forecasting Data Upper Level Heuristic Optimization (PSO) Grid AC/DC Rectifier = = = PBat DC/DC Converter = = Lower Level Dynamic Programming (DP) Centralized Controller PEV = = DC/DC Converter = = System Measurements PPV, PL, SOC & GT Other DC Loads EVs Figure 3.1. The overall configuration of the hybrid system. The first stage in the system operation is the collection of the forecasting data. This data comprises of the weather conditions which directly impacts the available power from the PV, the historical data which is used to predict the EV loading, and statistical or simulation models that are utilized for accurate forecasting of the grid tariff. Although, the determination of the forecasted grid tariff is not discussed in details in the scope of this dissertation, but few topologies found in the literature can be applicable. In [55], the authors proposed a combination of fuzzy interference system and least squares estimation to improve the short-term forecasting performance. Serving the same purpose, an adaptive 40

56 wavelet neural network is proposed in [56]. While the authors in [57] accounted for the aggregate customer reactions to electricity prices to develop a hybrid forecasting topology in a dynamic framework. A block diagram of the required forecasting data is shown in Fig In the studied system, a day-ahead scheduling is performed to optimize the PV/battery commitment and dispatch. Thus, the forecasting data are collected for 24 hours ahead. Forecasting Data 24 Hours Weather conditions PV power Historical data EVs load power Statistical or simulation models Electrical grid tarrif Figure 3.2. Forecasting Block Diagram Clearly, in order to implement the aforementioned grid tariff forecasting methods, the market type of the power industry governing the proposed system should be defined. The auction market is chosen in this study over the bilateral market to provide a higher degree of competition between the generators in decreasing the cost. In this market, the generators submit their bids to a centralized agent that determines the final price and the winning generator. This information is used as the updated grid tariff for the proposed system. The proposed system can work with any kind of operator, whether an independent system operator (ISO) or a regional transmission organization (RTO). The grid tariff is updated once an hour in the case study for this chapter which can be adjusted according to the frequency of the interaction between the system and the ISO or RTO. 41

57 The PSO optimization is considered to be a predictive upper-level optimization stage where the optimization is taking place based on a pre-known data from the forecasts. In the PSO, the battery state of charge (SOC) scheduling is assigned for every hour during a 24-hour horizon to achieve the minimum running cost for the system. Consequently, the PSO can be performed on an hourly basis if the forecasting data deviates from the online measured data from the PV source, the load, and the grid. The optimal SOC assignment provided from the upper-level optimization is used as an input to the dynamic programming online optimization level. Thus, the dynamic programming is computed only within the SOC limits specified at the upper level rather than all possible SOC levels. The DP is used as an online optimization tool where it is computed for every hour and then updated instantaneously based on the system real measurements. Thus, the dynamic programming is capable of applying error compensation based on the system measurements received and their deviation from the forecasting data used in the upper optimization level. The required system measurements are the PV output power (P PV ), the load current power (P L ), the measured battery SOC, and the updated grid tariff (GT). The hybrid system power balancing equations are represented as follows: P b (t) = P L (t) P pv (t) P G (t) (3.1) SOC(t) = SOC(t t) P b(t) t Q (3.2) where P G (t) is the grid supplied power at time t, Q is the battery full capacity at the time of power exchange, and t is the time interval. 42

58 Accordingly, P b (t) is considered to be positive while supplying power to the loads and negative while being charged from the PV source or the grid. The system operation is constrained by the following limits. The constraints imposed by Eqns. 3.3 and 3.4 are set to decrease the battery aging, while Eqn. 3.5 is set to limit the permitted power from the grid according to the transmission line and the distribution transformer ratings. SOC min SOC(t) SOC max (3.3) P bmin P b (t) P bmax (3.4) P Gmin P G (t) P Gmax (3.5) 3.3. Problem Formulation The main purpose of the power flow optimization problem is to minimize the system running cost while continuously supplying the desired loads. In order to find the optimal power flow for the system, a proper optimization problem needs to be formulated. The total cost of the system at any time (t) is expressed in Eqn. 3.6, where C T (t)is the total system cost, C G (t) is the grid operating cost, C BD (t) is the battery degradation cost. Thus the system objective function for one day of operation is shown in Eqn C T (t) = C G (t) + C BD (t) (3.6) t=t Min(C T ) = Min [ C G (t) + C BD (t)] (3.7) t=0 43

59 A. Gird running cost The grid cost C G (t) expression is shown in (3.8) where GT(t) is the grid tariff ($/kwh), P G (t) is the grid power (kw), and t is the time interval (hrs). The electricity grid prices or the grid tariff is dynamically changing due to different factors related to the amount of power demanded by the local loads as well as fuel prices, available generation and equipment outages. Thus, a day-ahead price forecasting of the electricity pricing is necessary in this study to be able to perform the required optimization [58]. C G (t) = GT(t)P G (t) t (3.8) B. Battery Degradation cost The impact of the battery health and degradation on the system cost is analyzed and taken into account in the formulated optimization problem. Accounting for the battery aging is crucial as the cost of lithium-ion batteries has a significant impact on the overall system cost. However, the battery degradation cost function is not simple because it is affected by various independent factors [59]. Three main factors impacting the health and the lifetime of the analyzed lithium-ion batteries are considered in this dissertation. The modeled battery degradation cost includes the impacts of the battery temperature, the average SOC, and the depth of discharge (DOD) on the lithium-ion battery capacity fading. B.1. Temperature impact The ratings of the charging and discharging current impact the battery lifetime by changing the battery operating temperature [60]. The battery operating temperature is directly affected by the average power (P avg ) drawn to or from the battery as shown in 44

60 (3.9). In this equation, a simple thermal model for the lithium-ion battery pack is represented, where T is the battery operating temperature, T amb is the ambient temperature of the battery pack, R Th is the battery pack thermal resistance, and P avg is the average charging or discharging battery power. The absolute of the average power is considered in this equation in order to account for temperature variations in both the charging and the discharging scenarios. T = T amb +R th P avg (3.9) The battery temperature impact on the battery lifetime is driven from Arrhenius equation which relates the battery lifetime (L(T)) at a certain temperature to the reaction rate. The rise in the temperature impacts both the battery power and capacity which leads to power fade and capacity fade over the battery lifetime. The power fade is discounted as its effect on the battery degradation cost is negligible relative to the capacity fade. Thus the battery lifetime is directly related to the battery capacity as shown in (3.10), where Q is the battery capacity at the time of power exchange, a and b are curve fitting parameters. The computed battery lifetime is then used to update the battery capacity for the next charging cycle. L(T) = aqe bq T (3.10) tf dt C temp = C bat ti Yhr L(T) (3.11) The battery degradation cost per kwh due to the temperature factor is shown in (3.11) where Yhr is a constant representing the number of hours per year, and C bat is the battery initial cost. The battery lifetime is simulated at different temperatures, and the cost 45

61 associated with that are shown in Figs. 3.3 and 3.4 respectively. The lifetime of the battery is said to be reached when the battery capacity decreases by 30% of its initial rating. Figure 3.3. Battery lifetime for different operating temperatures. Figure 3.4. C BD due to temperature impact B.2. Average SOC impact Modeling the impact of the SOC on the battery degradation cost is done using a curve fitting formula [58] to comply with the aging experimental data provided in [59-60]. Thus, Eqn is driven such that Q fade is the capacity fade at the end of the battery lifetime, and parameters m, d&n are curve fitting constants. A relationship between the battery degradation cost and the average SOC is shown in Fig C soc = C bat m SOC avg d Q fade n Yhr (3.12) Figure 3.5. C SOC at different SOC averages. 46

62 B.3. DOD impact A relationship between the Li-ion battery lifetime and the DOD is presented in [61-62]. This data is used in Eqn yielding to Fig. 3.6, which shows a relationship between the battery DOD and its associated cost per kwh. C DOD = C bat 2 N DOD Q µ 2 (3.13) where N is the number of the battery lifecycles at a particular DOD, and µ is the efficiency of charging and discharging the battery. In order to include the DOD battery degradation cost in the optimization problem, the cost function needs to be linear, and thus, a polynomial fitting curve is used with the calculated data as shown in Fig. 6. The equation of the fitting polynomial is shown in (3.14). C DOD = DOD DOD DOD DOD (3.14) To include the impact of the three factors in the battery degradation cost, Eqn is presented, and the function to be optimized can be formulated as in (3.16) after discretization. The physical constraints and designed limits of the system are shown in Eqns Figure 3.6. C DOD at different DOD values. 47

63 C bd = max {C temp, C DOD, C SOCavg } (3.15) N i C Ti,run = [C G (k) + P b (k) tc bd (k)] k=1 (3.16) The proposed power flow formulation contributes to the battery lifetime and increases the robustness of the system by accounting for the battery degradation in the optimization process. Moreover, the system is more reliable due to the forecasting method proposed which predicts the load demands, the weather conditions, and the grid tariff for a day ahead to schedule the battery SOC variation accordingly Power Flow Optimization The objective of defining the optimization problem is to minimize the daily running cost of the system with optimal battery power scheduling. The method used to realize the optimization problem shall be chosen according to the nature of the problem, the number of variables and uncertainties, the required computation time, the desired accuracy, and the need for error compensation (reactive management). Some of the most common optimization methods used for power flow management are shown in Fig One of the simplest methods used for unit commitment scheduling is priority method or rule-based method. This method creates a priority list based on some pre-defined rules and then executes the list while taking the scheduling decision. Although, this method provides a simple means of battery scheduling while allocating low memory, but the solution of this method is not optimal. This feature degrades the overall efficiency of the system which leads to a higher running cost. 48

64 Power Flow Optimization Methods Quantitative Methods Heuristic Methods Linear Programming (LP) Quadratic Programming (QP) Dynamic Programming (DP) Genetics Algorithm (GA) Particle Swarm Optimization (PSO) Figure 3.7. Power flow optimization methods block diagram. Linear programming has been used in the literature in unit commitment scheduling problems [38]. Linear programming deals only with linearly formulated problems which are not generally the case with the short-term scheduling problems. Thus, mixed integer linear programming (MILP) is introduced and used with nonlinear problems formulated in linear form, which creates discrete value variables [63-65]. The main disadvantage of this method is the need for problem linearization, which may cause the loss of some problem characteristics. Additionally, this method requires the use of a specific mathematical solver. LP and MILP are also not suitable candidates for online error compensation. Quadratic programming is sometimes referred to as Lagrangian relaxation method. It has been successfully implemented on unit commitment problems [38]. The main advantage of Lagrangian relaxation is its quantitative measure of the solution [63]. However, this method is mostly suitable to thermal units commitment due to its quadratic nature. Additionally, some simplifications may need to be applied to the objective function to make it convex or concave, which may affect the solution feasibility of the optimization problem. 49

65 DP is a graph-based technique that takes the shortest path between two points. This method can be applied to any nature of functions with the ability for reactive management. The main drawback of dynamic programming is the need to discretize the system states into steps. This requires a high required memory and may affect the computation time for long studied periods. Heuristic methods are mostly used with nonlinear objective functions or constraints when quantifying the optimal solution could be tedious. The main disadvantage of these methods is the long required computation time that results from the need to run the program for numerous iterations until the optimal solution is achieved. So, heuristic methods are not suitable for online optimization and reactive management. Genetic algorithms (GA) is one of the most promising iterative optimization methods in which the algorithm mimics the process of natural selection to reach the optimal solution. The algorithm starts by setting a random number of data points (population) and then runs a certain number of iterations (generations) to optimize the objective function (fitness function). GA is used in [67] to realize the economic operation of a standalone micro-grid system. Particle swarm optimization (PSO) is another widely used heuristic optimization method in power systems unit commitment problems. In [68], PSO was combined with Lagrange relaxation to solve the unit commitment problem where PSO is used for the optimal setting of Lagrange multipliers. PSO is used to solve the power flow management problem in [69] and the authors concluded that PSO is more efficient in such an application compared to GA. 50

66 Consequently, a dual layer optimization strategy is proposed in this study to solve the power flow problem. The first layer is an offline layer that utilizes a day ahead forecasting approach to assigning the battery SOC scheduling throughout the day. PSO optimization is chosen for this layer due to its efficiency and high accuracy. Although PSO suffers from high computation time, but that problem can be safely overlooked as the optimization is performed offline. Another power flow management layer used in this study for online operation and error compensation is the DP. DP is the chosen method for the online optimization due to both its dynamic ability and the non-linear structure of the formulated problem in (3.16). The combination between the PSO and the DP results in reducing the drawbacks associated with the DP online optimization. That is done as DP operates for relatively short time intervals within certain SOC limits that are assigned from the offline optimization (PSO). The reduction in the system running cost is achieved through the means of peak shaving using forecasted data alongside with the healthy operation of the battery pack in the proposed system in order to extend its lifetime. In the following subsections, the use of the offline PSO and the online DP stages are successively explained. A. Offline Predictive Optimization Stage (PSO) An offline optimization technique is desired to be used in the studied system to achieve an optimal battery scheduling based on the forecasting data. As shown in (3.16), the objective function is non-linear and non-quadratic; thus, linear programming and quadratic based techniques (e.g., Lagrangian relaxation, gradient method) are not suitable for the optimization problem of interest in this study. Here, PSO is used as a well proven heuristic optimization tool to find the optimal scheduling. 51

67 The PSO is applied to the optimization problem to find the optimal battery SOC values throughout the evaluated time period {SOC t } t=1,2,,k. The time period in the algorithm is chosen to be 24 hours, with an interval of 1 hour. The population for the PSO algorithm consists of N p vectors of particles, i.e., q = 1,2,, N p, as each vector defines a sequence of the battery SOC during the designated time period, while every particle represents the battery SOC value for one hour time interval. The objective function is shown in (3.14), the problem constraints are shown in (1-5), the battery parameters (capacity, capital cost, thermal model, and fitting variables), the PV predicted power and the load forecasted demand are all used as inputs to the PSO. Based on these inputs, the implemented PSO searches the optimal SOC values for the 24 hours, i.e., SOC 1, SOC 2,, SOC K, such that K = 24. PSO C T SOC t Cost Function P b, P G, T, L(T), SOC avg & DOD System Dynamics Figure 3.8. PSO block diagram to optimize the system running cost. The PSO is initialized with a population of random solutions for the SOC assignments for every one hour time interval of a day. The SOC assignments (SOC t ) are used in the system dynamics to calculate the system variables at every interval. The system variables required for the cost analysis are the following; the battery power (P b ), the grid 52

68 power (P G ), the battery temperature (T), the battery lifetime (L(T)) at the instantaneous power, the average SOC (SOC avg ), and the DOD. The system variables are used in the cost functions shown in (3.8, ) to generate the cost associated with the set of SOC values, {SOC t } t=1,2,,k. The generated cost (C T ) is then fed back into the PSO algorithm. This operation continues for some iterations and the position of the particles are updated at each iteration based on the local and global optimal solutions. The set of the assigned SOCs that gives the minimum global cost is considered to be the optimal solution. The optimization process is shown in Fig The optimal vector of SOC assignments at every interval of time are used as SOC limits for the next layer of optimization as shown in the next subsection. B. Online Optimization Stage (DP) The purpose of the DP is to manage the system power flow over short time intervals with consideration to the SOC limits specified by the PSO and to compensate for the optimization errors when the system measurements deviate from the forecasted data. The use of the DP in this stage reduces its previously mentioned weakness of high memory allocation requirements as it only operates on short time intervals within state trajectories limited by the optimal SOC vector provided from the prediction layer. Thus, a SOC constrained structure is used in this layer for the DP stage. The DP operation over an operating interval is limited within the initial and the final SOC assignments. A freedom degree is utilized for the transition states between the initial and the final SOC. This allowable degree for the transition states is limited by the battery system charging and discharging power limits. An example of the SOC constrained structure is shown in Fig It is illustrated by the example that the possible trajectories 53

69 are significantly limited due to the predictive optimization used in the PSO. In this example, the optimal SOC assignments are assumed to be 0.6 at both, the initial and the final states. Thus, this feature allows for less computational time and smaller allocated memory. to t1 t2 T=t3 SOC max SOC max SOC max SOC max SOC SOC limits SOC SOC min SOC min SOC min SOC min T T T Figure 3.9. Batteries SOC space example for DP. The error compensation procedure is shown in Fig It is shown that there are six possible deviations of the measured data from the forecasted ones. Those deviations affect the decision taken in the DP layer by shifting the SOC limits up and down based on the type of error found. For example, if the updated GT is lower than the forecasted one, the SOC limits can be increased to allow higher storage in the batteries. The shifting value 54

70 is proportional to the error value, however, if the error exceeds a certain limit, a different procedure is followed as shown in Fig Lower P PV Higher GT Shift SOC Limits down Higher P PV Lower GT Shift SOC Limits up Higher P L Lower P L Figure Error compensation procedure in the DP stage. Forecasting Data Ppvf(t), PLf(t), GTf(t) Initialize the SOC assignments of all the intervals (SOCt) PSO Errors computation (Errn) DP Measured Data Ppv(t), PL(t), GT(t), SOCi Prediction Layer SOCt System Dynamics Cost Function Pb, PG, T, L(T), SOCavg, DOD Ct Computation of SOCt Measured Data Yes (Err) > Lower limit Yes (Err) > upper limit No Compute shortest Path SOC * = {SOC f, SOC f-1,.., SOC i } Apply the SOC scheduling to the PV/battery system i=i+1 SOCt No Update SOC limits SOC limits NO Is i=n Yes SOC limits from PSO Online Reactive Management Layer Figure Flowchart of the proposed power flow management structure. In the error compensation stage, the SOC limits are dynamically updated based on the error between the measured and the forecasted data. This is done in every time interval. If the error exceeds a certain limit, the program feedback that information to the PSO in the prediction layer in order to re-initialize new optimal SOC settings. A flow chart of the 55

71 proposed control structure and the coordination between the two layers is shown in Fig Validation Results The simulation parameters of the case study for the proposed hybrid PV/battery system are shown in Table 3.1. The initial cost of the battery is determined based on the available data of the current EVs Li-ion battery cost as shown in [70-71]. Moreover, the goal of the US Department of Energy to cut the prices down to $125/kWh by 2022 [72] is accounted while setting the initial cost in the simulation parameters as shown in Table 1. Table 3.1. Simulation parameters. T PSO PSO Studied Period 24 hrs Δt PSO interval period 1 hrs T DP DP Studied Period 1 hrs Δt DP interval period 10 mins SOC min /SOC max Minimum/Maximum SOC 0.1/0.95 Q Battery capacity 100 kwh P bmin /P bmax Minimum/Maximum battery power 75/75 kw P Gmin /P Gmax Minimum/Maximum grid power 100/150 kw SOC initial Initial SOC 0.5 R th Battery pack thermal resistance 0.2 mω C Bat Battery Cost per kwh $ 400 A. Case Study I The proposed power flow management topology has been tested by applying it to a case study for a fast electric vehicle charging station. The forecasted load profile and the PV output power of the charging station are shown in Fig for one full day of operation. A dynamic GT is chosen for testing the system as shown in Fig The PSO has been 56

72 carried out for the full day operation and the optimum SOC scheduling is shown in Fig The optimal power flow from the battery and the grid are shown in Fig The convergence of the system global cost with the number of iterations is shown in Fig to demonstrate the optimum operating cost that the system is providing. Power (kw) Time (hrs) Figure PV power and load power forecasted for one day of operation. SOC & Cost ($/kwh) PV power Battery SOC Load Power Grid GT Time (hrs) Figure Battery SOC scheduling and GT for one day of operation. The next step of the test is to apply the DP in every time interval of one hour using time steps of 10 minutes. For time interval of [5 pm 6 pm], DP results are shown to verify the system effectiveness. Figs and 3.17 show the detailed PV power and load power variations through the selected time range. The associated battery power flow for the optimal operation on the short interval is shown in Fig The SOC values are updated 57

73 accordingly as shown in Fig As shown, the DP adds a further degree of optimization and error compensation that is not achievable through offline predictive optimization Battery Power Grid Power Power (kw) Time (hrs) Figure Optimized battery power and grid power for one day of operation. Figure The convergence of the global cost in the PSO problem. It is clear from the shown results that the peak load shaving is successfully done at the high grid tariff periods (e.g. at 6-8 am in Figs ). This is the main reason that helps in increasing the system savings in one day of operation. 58

74 Power (kw) Figure 3.16 PV power measured over one hour of operation. Power (kw) pm 5:20pm 5:40pm 6pm :20pm 5:40pm 6pm Figure Battery power optimized over one hour of operation. Power (kw) pm 5:20pm 5:40pm 6pm Figure Load power measured over one hour of operation. SOC pm 5:20pm 5:40pm 6pm Figure Battery SOC scheduling over one hour of operation. B. Case Study II The system is then evaluated at the same P PV, same battery pack, while the load power is reduced as shown in Fig a. The resultant power flow of the system for one day of operation is shown in Fig b. It can be observed from Fig c that the global cost is negative indicating a revenue for the charging station because of a net power flow into the grid. Finally, if the load demand is higher than the grid capability, the available PV power and the storage energy for the desired duration, then a load shedding procedure shall be followed by limiting the charging rate of the EVs. However, the need to apply the load shedding indicates that either the system forecasts largely deviated from the actual 59

75 conditions or that the system is not designed to sustain the operation in all conditions. If the forecasts deviate, then the online DP will report this information back to the PSO (as shown in Fig. 3.11) so that the PSO can assign new SOC variables and decide on the maximum power that the system can provide. If the system is not initially designed to sustain the maximum loading conditions, then the PSO will apply the load shedding procedure prior to running the system. The DP performs within the assign SOC limits commanded by the PSO load shedding procedure. However, the amount of load shedding is not part of the optimization problem as the system is always designed to either satisfy the load demand or provide the maximum available energy from the system during the daily operation. a) PV power and load power forecasted for one day of operation. Figure The power flow results for Low load conditions scenario. 60

76 b) Optimized battery power and grid power for one day of operation. c) The convergence of the global cost in the PSO problem. Figure The power flow results for Low load conditions scenario. (Cont'd.) Although adding a battery degradation cost shows the slightly higher daily running cost for the system, the insertion of this term extends the lifetime of the battery and thus decreases the battery replacement cost in the long term. The proposed topology leads to 20-40% extension in the battery lifetime with respect to the conventional method of optimizing the running cost based only on the grid tariff. This lifetime extension helps in achieving the goal set by the US Department of Energy to increase the lifespan of EV batteries to 15 years. Table 3.2 presents the extension in the battery lifetime for two case 61

77 studies in relative to the conventional method which does not account for the battery degradation cost. Table 3.2. Batteries lifetime comparison. Case Study 1 Case Study 2 Proposed Method 13.8 years 13.9 years Conventional Method years 10.7 years C. Experimental Validation A downsized 1 kw laboratory prototype of the proposed system is developed to validate the theoretical and simulation results. The main aim of the experimental test is to prove the system dynamic ability and fast response under varying operating conditions. The developed testbed comprises of three power electronic converters connected to the system power sources. The sources in this system represent the grid, the battery, and the PV array. The load is emulated using a controlled variable power electronic load as shown in Fig In order to apply the DP in the DSP configuration, the initial code in Matlab format is translated into a lower level language understandable by the DSP. The DP algorithm requires the computation of Eqn. 16, which is composed of factorial multiplications and additions operations. This equation has to be computed at every state in the DP graph, then the different paths are compared and the shortest path is considered for implementation by applying Bellman Equation. However, The SOC limits specified in the offline predictive layer is critical in simplifying the DP problem for the DSP coding as it reduces the number of trajectories that can be used for the optimal solution. This feature makes it practical to apply the DP as an online tool that can run at every specified time interval. In the case study results presented in Figs , the time interval is chosen to be one hour. Thus, 62

78 in this example, the DP need to run only once in every hour or whenever a significant change in the site conditions is reported from the local sensors. The DP optimization requires 31 factorial multiplications, 7 additions which require 0.25 μs for every state in the DP graph. Then, the shortest path is chosen based on the lowest cost. The optimization runs in a lower priority interrupt procedure and a 150 MHz floating point DSP is used in the implementation. The DSPs are used to apply the SOC scheduling assigned in the prediction layer as well as applying short interval optimization and error compensation. Figure Experimental setup for the proposed PV/Battery system. The starting conditions of the three power electronic interfacing systems of the Grid, battery, and the PV are shown in Fig to demonstrate the smooth transition of the controlled converters during start up conditions. The power flow management test is carried out to emulate the system simulation results. It should be noted that the system variables are changing rapidly compared to the case study shown in Figs The 63

79 rapid changes are due to the limited time of 140 s used in the experiment compared to the 24 hrs used in the case study. However, the rapid variations test the system response and the fast tracking of the different operating conditions. The GT of the presented scenario used in the proposed system is shown in Fig It can be shown from the presented figures that the GT is changing rapidly which would lead to different power commands from the available sources. However, as explained in the previous Sections, the equal power sharing is not the objective of this dissertation, rather an optimization management of the power flow is applied to minimize the operating cost. Thus the experimental setup is tested for a time horizon of 140 s under a certain scenario comprised of three variables. The variables are the load power, the PV power and the grid tariff. The simulated load power for the presented scenario as well as the experimental load power is shown in Fig It is observed that the load power starts at 0 kw, then increases gradually to reach its peak at s, then varies until the end of the time interval. This scenario is chosen to imitate the presented load power scenario shown in the case study in Fig during the first 15 hrs. The presented results demonstrate that the experimental setup successfully tracks the simulated scenario at different power levels. The data shown in Figs provides the optimized simulated data of the presented scenario using PSO along with the associated optimized experimental results. The load power, the PV power, the initial battery SOC (0.8 in this scenario), and the GT are used as inputs in the optimization problem to create the dotted lines in Figs that represent the optimal power flow conditions of both the grid and the battery 64

80 sources. The optimal power flow scheduling is then applied on the experimental setup and the results are compared to the ideal simulated scenario as shown in the solid lines in the Figs. It can be concluded from the presented data that the power converters along with the control structure applied are capable of tracking the optimal power flow conditions through the applied time interval. Grid Power Grid, Battery & PV Power Grid & Battery Power Figure Experimental waveforms at the starting conditions for the PV/battery grid tied system. Figure Dynamic grid tariff used for the presented scenario during the experimental implementation. 65

81 Figure The optimized simulated and experimental load power scenario results. Figure The optimized simulated and experimental grid power scenario results. The simulated PV power in Fig represents the maximum power that can be tracked from the PV array during the time interval. It is clear that the PV converter is successfully tracking the maximum power point under rapid variations in the insolation level. Lastly, the three converter currents along with the DC bus voltage are shown in Fig. 66

82 3.28 for the aforementioned scenario to demonstrate the stability of the system and the constant DC bus voltage at varying operating conditions. Figure The optimized simulated and experimental battery power scenario results. Figure The optimized simulated and experimental PV power scenario results. 67

83 Figure Experimental results for 20s/div (1- Grid converter current, 2- Battery converter current, 3- PV converter current & 4- DC bus voltage) Net Metering and System Configuration The presented system in Fig. 3.1 is configured assuming a unified metering. A unified metering is the metering system that allows PV owners to receive credit at the full retail rate for energy exported to the grid. However, unified net metering can create a serious cost imbalance. While PV owners with solar panels usually see significant reductions in their electric bills, they still rely on the grid for electricity at night and on cloudy days. The utility collects less revenue, even though the infrastructure costs remain the same. Lost revenues from DER customers are being recovered from non-der customers in order to encourage distributed generation implementation. This type of lost revenue recovery drives up the prices of those non-participating customers and creates the environment for ongoing loss of additional customers as the system cost is transferred to a smaller base of customers. 68

84 Thus, alternative billing policies are predicted to take place in the future. In October 2015, the Hawaii Public Utilities Commission (PUC) issued a ruling to end the unified metering system for new PV owners and replaced it with a new dual metering system. The dual metering system compensates the customers for generating electricity and feeding it to the utility at a lower retail rate. In such a scenario, exporting energy to the grid will have less economic benefits from the PV owner point of view. Consequently, the system architecture needs to address this point for achieving a lower cost and higher efficient interfacing systems. The dual metering system is evaluated using the proposed power flow management and the results are shown in Fig It can be concluded from the presented Fig. that the grid would be supplied from the PV/battery system only at times when there is an excess of solar energy and the batteries are fully charged. Figure Optimized battery power and grid power for one day of operation using the dual metering system. The conventional configuration of the PV/battery grid tied system shown in Fig. 3.1 is composed of a bidirectional PWM inverter that is sized for the full power imported 69

85 from and exported to the grid. However, if the new metering systems are imposed, then a full sized bi-directional PWM inverter would be an evitable part of the system. Additionally, the conventional configuration showed in Fig. 3.1 creates more than a single failure point in the system that can be avoided; e.g. the PWM inverter and the DC link capacitors. Furthermore, the need for electrolytic capacitors at the DV link to stabilize the voltage shortens the system lifetime and increases its cost. A new proposed reliable configuration of the grid tied PV/battery electric vehicle charging station is shown in Fig to alter the aforementioned challenges. AC/DC PWM Inverter PV String Unidirectional DC-DC Converter Grid L Filter AC/DC Rectifier Bidirectional DC-DC Converter Battery Storage Electric Vehicle Unidirectional DC-DC Converter Figure A novel reliable configuration for the hybrid system. In the presented configuration, a typical uncontrolled rectifier is used to interface between the grid and the storage batteries. This rectifier is sized for the maximum power that can be imported from the grid. A downsized PWM inverter is only needed for the interface between the PV strings and the grid. The PV string, the storage batteries, and the 70

86 electric vehicles exchange power through the shown DC/DC converters as will be discussed in the next chapters Conclusion A proposed power flow management technique for PV-battery powered EV fast charging stations is presented in this chapter. The broad objective of the proposed technique is to operate a PV/battery system, which is serving as a fast electric vehicle charging station, in a cost-effective operational mode. This is achieved by continuously minimizing the system running cost while considering both the dynamic grid tariffs and the battery degradation cost. Accordingly, a battery degradation cost model is presented which accounts for the operating temperature, average SOC, and the cycle DOD. PSO is used as an offline predictive optimization tool to set the battery SOC limits according to the PV, load forecast, and the dynamic grid prices. An online DP approach is then utilized to manage the system power flow on a lower level and on short time intervals. The inclusion of the DP into the system helps in improving the system computation time and efficiency. Additionally, the DP is used for error compensation at times when the forecasted data differs from the measured data. Simulation and experimental results were presented to prove the system effectiveness under dynamic and various conditions. The dual metering systems are gaining more share in the electrical power system industry. Thus, the developed power flow management topology is applied considering this new metering system to conclude the following. The amount of power flowing from the 71

87 battery storage to the grid is a relatively a small fraction of the same amount in the unified metering system. This is due to the fact that the ratio of the sold electricity revenue to the battery degradation cost is decreasing in this metering system. Consequently, the use of a bi-directional fully controlled rectifier between the grid and the battery storage adds a level of complexity and a high cost that can be avoided. Therefore, a new PV/battery grid tied configuration is proposed in this chapter to reduce the system cost and simplify its control. However, the newly presented configuration is faced with challenges in regards to the DC/DC converter selection, the PFC capability, and the PV string configuration. These challenges are discussed successively in the upcoming chapters. 72

88 CHAPTER IV FAST DC CHARGERS CONFIGURATION 4.1. Introduction Todays 240 V fast charging stations (level-ii) require 2 6 hours of charging time to replenish depleted EV batteries. The time required for recharging the EV batteries is not acceptable for many EV users. The fast charging is necessary, but the electrical infrastructure of the local grid would not be able to support the high power fast charging stations. Thus, a proposed hybrid PV/battery grid-tied system is introduced in this dissertation. The proposed system is designed to comply with the power flow management results presented in Chapter 3 by realizing the configuration shown in Fig The central interfacing system of this configuration is the design of the bi-directional DC/DC converter used in the system to interface the interconnected sources and loads. Thus, a battery charging system (BCS) DC/DC converter that is used to assist the fast charging requirements of EVs is presented in this chapter. The BCS presented in this chapter is designed to be rechargeable from the available power substations (e.g. 3 phase 480 V) with 80 kw charging rate. The appropriate modular power interface is designed and implemented between the BCS, batteries of the EVs and the power substations. Experimental validation of high power charging rates is presented in this chapter to demonstrate the system performance and effectiveness under rapid charging requirements. 73

89 4.2. System Configuration The BCS charging modules consist of the following power electronic components; An AC/DC rectifier, for converting the AC input grid voltage into a constant DC voltage. Relays for controlling the modes of operation. A high power bi-directional DC/DC converter, for controlling the power flow. An interfacing board for the implementation of the control and the communication algorithms. The proposed power electronics configuration for the individual charger modules is shown in Fig Essentially, this Fig. is similar to the configuration shown in Fig. 3.30, with the exception of the PV source being excluded from the shown charger module as it does not affect the design at this stage. The system has various modes of operation. When the electrical grid is charging the storage, the charger modules are switched into the charging mode and the power flows from the electrical grid into the storage batteries. The grid can be charging the EVs simultaneously. The DC/DC converters in this mode control the charging current into the storage batteries and the EVs. During the discharging mode, the battery storage provides power to charge EVs. The BCS system controls the charging rate into the EVs through the interfacing DC/DC converters as shown in Fig

90 Charging Station Individual Charger Module Grid 480V 3 Phase L Filter AC/DC Rectifier Bidirectional DC-DC Converter 80 kw Charging Module 400 kwhr Battery Storage V Electric Vehicle Unidirectional DC-DC Converter V Figure 4.1. Individual Charger Modules Modular Power Interface Since the onboard charger does not provide fast charging capability, DC charging is required to ensure fast charging for extending the EV drive range. The DC-DC converter interfaces the energy storage system with the grid rectifier and is primarily used to control the charging and the discharging rates of the battery storage. It can also be used to reduce or eliminate the grid harmonics resulting in a higher power factor for a more efficient charging configuration (as shown in Chapter 5). The DC-DC converter has to be bidirectional to enable the battery storage charging from the grid and discharging through the EVs. The single stage and the dual stage DC-DC converter topologies are analyzed and compared in this research to be used in an EV charging station infrastructure. 75

91 Bi-Directional Converters Single Stage Dual Stage Buck-Boost Cuk Sepic-Luo Combined Half Bridge Cascaded Buck-Boost Figure 4.2. Various bi-directional converters considered for the comparison study and their classifications. A comparison among various bi-directional converter alternatives for the BCS application is explored in this dissertation [73-74]. The different converter options considered for the comparison can be classified into two main categories as shown in Fig A. Single stage bi-directional converters. Single stage bi-directional converters process the total power through a single stage of active elements. The main advantage of the single stage converters is the reduced number of active elements required for the power flow compared to the dual stage converters. Three bi-directional converters studied under this classification are shown in Fig The Buck-Boost (BB) bi-directional converter can be implemented easily with only one inductor required for the power transfer. On the other hand, capacitors should be used on both sides of the converter with relatively high ripple current, the high inductor current is expected to pass through the inductor, and the output voltage is negatively polarized. 76

92 - Unlike the BB topology, the Cuk bi-directional converter reduces the need for input and output voltage balancing capacitors as reduced input and output current ripple is expected. Compared to buck-boost topology, more inductors are required and the capacitor rating for transferring power is relatively high. As in the case of the buck-boost topology, the output voltage polarity is inverted. D1 D2 EV Grid + - C1 S1 L S2 C2 + - Battery Storage A) Buck-Boost L1 L2 Cm Grid EV S1 D1 S2 D2 Battery B) Cuk L1 +C D2 EV Grid S1 D1 L2 S2 Battery Storage C) Sepic-Luo Figure 4.3. Single stage bi-directional DC/DC converters. 77

93 The need for one of the voltage balancing capacitors can be also eliminated in the Sepic-Luo configuration. A decrement in the transfer capacitor rating is achieved in this converter compared to the Cuk converter. Moreover, the output voltage has the same polarity as the input supply so that they can share the same ground connection. As can be observed from Fig. 4.3.c), more passive elements with higher inductances are required to maintain the ripple limits of the input and output currents. B. Dual stage bi-directional converters. The power is processed through two different stages of conversion in the dual stage bi-directional converters. The two-stage methodology allows a wider range of output voltage and current in addition to the lower voltage stress applied to the active components. In this subsection, a comparison between two dual stage bi-directional converters is presented to analyze the benefits and the drawbacks of the different topologies for EV applications. The comparison is based on the system efficiency, the components sizing and their ratings. The first converter is the Cascaded Buck-Boost (CBB) converter proposed in [75] and shown in Fig This converter has been adopted for different applications in the EVs and the RES industry. The Combined half bridge (CHB) topology proposed in [76] as shown in Fig. 4.5 is another dual stage converter type considered for comparison in this study. Both of the converters require only one switch to be operating at a particular frequency to perform either as a buck or a boost converter, while the other switch is kept on or off for the whole current flow period [75]. The authors in [77] suggested controlling both of the switches with different duty ratios to maintain a particular intermediate voltage 78

94 for CHB. This will result in a higher intermediate voltage across the central capacitor C M. The Central capacitor can be used as a point of common coupling for a multi-input, multioutput DC/DC converter system. EV Grid S1 D1 S2 D2 + L - + Battery C1 C2 - Storage S3 D3 S4 D4 Figure 4.4. CBB type bi-directional converter. Table 4.1 provides the required inductance for different modes of operation for both of the converters. Table 4.2 provides the required capacitance values for both of the converters. V G is the grid voltage, V E is the electric vehicle voltage, and V B is the battery storage voltage. The two converters have the same expression for minimum required capacitance. The capacitor voltage ratings are calculated considering certain allowed voltage ripple of 10 % across the capacitor. 79

95 S1 D1 S2 D2 Grid EV L1 C1 + - CM + - S3 D3 S4 D4 C1 + - L2 Battery Storage Figure 4.5. CHB type bi-directional converter. Table 4.1. Inductor current ratings for dual stage converters. CBB Inductance CHB L L1 L2 V G to V B Buck V G to V B Boost V B to V E Buck V B to V E Boost V 2 2 (1 D 1 ) f i L I L P V 2 2 (1 D 3 ) V 1 2 D 4 f i L I L P V 1 2 (1 D 3 ) f i L I L P V 1 2 (1 D 1 ) V 1 2 (1 D 2 ) 2 D 2 f i L I L P f i L I L P f i L I L P 80

96 Table 4.2. The capacitor voltage ratings for the dual stage converters. V G to V B Buck V G to V B Boost V B to V E Buck V B to V E Boost (1 D 3 ) P(1 D 2 ) C1 8Lf 2 v 1 V 1 fv G 2 v 1 V 1 (1 D 1 ) P(1 D 4 ) C1 8Lf 2 v 2 V 2 fv V 2 v 2 V 2 Table 4.3. Efficiency comparison of the bi-directional converters. From Grid to Battery Storage From Battery Storage to Electric Vehicle Pout (kw) Pin (kw) η % Pout (kw) Pin (kw) η% CBB CHB BB It can be concluded from the above comparisons and tables that the cascaded topologies have higher efficiencies than the conventional ones. Fewer components are required for the CBB converter compared to the CHB converter. Based on those findings, CBB converter is selected to be used in the BCS application. During the charging mode of the BCS batteries from the three phase grid input, the DC-DC converter operates in a buck mode. BCS battery storage operates between 320 V to 480 V and the rectified three phase grid voltage is around 650 V. During charging of the EVs from the BCS the DC-DC converter can run either in a buck or boost mode depending on the voltage level of the EVs and the BCS batteries. 81

97 4.4. Design Considerations Using an Interleaving Converter The use of an interleaved converter is preferred over the conventional one for achieving lower current stress on the various active and passive components [78]. Interleaving technique uses multiple channels phase-shifted from one another by 1 T where N N is the number of parallel channels and T is the switching time period. The inductors and the capacitors are sized in the converter according to the limitations imposed on the output current and voltage ripple. Eqns describes the enhancement in the output current ripple using the interleaving converter with three channels. Table 4.4. Equations governing the current ripple in the presented CBB converter. Buck operation with interleaving Boost operation with interleaving I 0 = 3I Li (4.1) I 0 = 3I Li (1 D) (4.2) I O = 1 3 I L i (4.3) I O = 1 3 I L i (1 D) (4.4) I O I O = 1 9 I Li I Li (4.5) I O I O = 1 9 I Li I Li (4.6) where I O and I L are the output load current and the inductor current receptively. I O and I L are the output and the load current ripples, while D is the controlled duty ratio. The inductor current and the capacitor voltage ripple requirements are updated based on the improvements provided by the interleaving technique as shown in ( ). The improvement helps in designing the converter with lower inductor and capacitor values. Based on the new requirements, the passive components are sized using the following equations ( ). 82

98 Table 4.5. Sizing of the passive elements in the presented interleaving CBB converter. Buck Mode Operation L = V 0 2 (1 D) C o = f i L I L P (1 D) 8Lf i 2 v o V o P (4.7) L = V I 2 D (4.9) C o = Boost Mode Operation f i L I L PD P (4.8) 3f i v o V 0 V O 2 (4.10) where V o represents the output voltage (either BCS or EV battery voltage), f is the switching frequency, f i is the interleaving frequency, P is the output power, and C o is the output capacitance which can be C 1 or C 2 depending on the direction of the power flow. The number of interleaving stages is a tradeoff between the lower ripple that can be achieved and the control complexity which increases the cost of the circuit. A more detailed analysis of the choice of this number can be found in [79]. Based on the provided analysis and the commercial products availability, three stages of interleaving converters are chosen for the used CBB converter. Fig. 4.6 shows the current flowing through interleaved inductors and the total output current for the BCS charging operation. The ripple on the total output current is reduced significantly as can be observed from the Fig. The proposed configuration of the interleaved CBB converter is shown in Fig

99 Current (A) Current (A) Interleaving Inductor Currents Output Current Time (s) Figure 4.6. The simulated interleaving inductor currents and the output current. IL1 IL2 IL3 VG or Vv Grid EV + - S1a D1a C1 S1b D1b S1c D1c L1 L2 L3 S3a IL1 IL2 IL3 D3a S3b D3b S3c D3c C2 + - Battery Storage VB S2a D2a S2b D2b S2c D2c S4a D4a S4b D4b S4c D4c Figure 4.7. The Interleaving CBB converter used for the BCS system Thermal Management of The Charging System High power ratings are suggested in this study to charge the BCS. The high charging rates draw high current values from the battery storage system while discharging through the EV batteries. Thus, a thermal battery energy management system needs to be designed to handle the extreme stress conditions. In this subsection, an electrical and a thermal model of the Li-ion battery are introduced. The resulting models have been coupled accordingly in order to arrive at a compatible thermal energy management system. 84

100 A) Li-ion battery models Li-ion battery is widely used in EV applications due to its longer life-cycle, higher energy and power density compared to those of Ni-MH and lead-acid batteries [79]. Thus Li-ion batteries are typically the candidate of choice for BCS applications. A.1. Li-ion battery electrical model A circuit based battery model is essential in order to build a complete integrated simulation circuit. The battery cells are modeled using a Thevenin circuit model [80], as shown in Fig. 4.8, where V t is the terminal voltage, V oc is the battery open circuit battery voltage, R o is the ohmic resistance, R d is the diffusion resistance, C d is the diffusion capacitance. Cd Voc Rd Ro Vt Figure 4.8. Equivalent circuit model of Li-ion battery. Although this model is experimentally verified for its accuracy, it ignores the effects of high current ratings which lead to high thermal stress on the battery. Thus, a thermal battery model is introduced to be coupled with the circuit model in order to account for the high-temperature stress that typically occurs at high charging and discharging rates. A.2. Li-ion battery thermal model A number of electrochemical reactions take place during charging and discharging of the battery pack. These reactions result in heat accumulation inside the battery cells which may cause a thermal runaway problem if thermal energy is not efficiently managed [81]. 85

101 An accurate battery thermal model is an essential tool for the design of a thermal management system. The energy balance for every control volume can be given by Eqn [82]. The heat generation term can be estimated as shown in [79]. These Eqns. allow the ability to estimate every temperature at every point in the cell. (ρc p T) = (k T) + q (4.11) t The mathematical and numerical thermal models are all based on the energy balance, heat generation, and boundary condition equations. Thermal models are developed in the literature to analyze the battery thermal behavior, with different accuracy levels and degrees of complexity. A simplified one-dimensional thermal model with lumped parameters is verified in [81] to simulate the temperature behavior of Li-ion batteries during the discharge cycle. The results showed that, at high discharging rates, scaled up Li-ion cells require an efficient thermal management system to avoid risking thermal runaway. A complex one-dimensional thermal model is used to explore pulse power limitations and thermal behavior in a Li-ion battery pack for EV applications [83], this paper demonstrated the ability to increase the battery charging rate by limiting its charge via a φ s φ e potential margin. Ohmic heating is found to be the dominating term under pulse power operation similar to that applied on the EVs battery packs during charging and discharging conditions. Thus, equivalent circuit models validated over a wide range of temperatures and state-of-charge (SOC) levels can be sufficiently accurate for EV applications. More multi-dimensional models are developed in the literature for more accurate thermal behavior estimation of the Li-ion battery pack. 86

102 In this dissertation, the lumped capacitance model [84] is coupled with the electrical model shown in Fig. 4.8 to account for the thermal stress at different discharging rates. The model equations are summarized as follows: Q B = T B T air T o (4.12) h = R o = 1 ha + 1 ka m air ρa a ( ) 5 b, for T b > T ref (4.13) (4.14) { 4, for T b T ref } T air = T amb Q B m air C p,air (4.15) T B = Q G Q B m B C p,b 0 t dt (4.16) where Q B is the heat dissipated from the battery, T B is the battery temperature, T air is the surrounding air temperature, h is the heat transfer film coefficient, k is the heat conductivity coefficient, T ref is the reference set temperature, m air is the air flow rate, ρ is the air density, A is the battery pack temperature, T amb is the ambient temperature, C p,air is the air heat capacity, Q G is the heat generated from the battery, m B is the battery mass, and C p,b is the battery heat capacity. The battery heat is mainly generated from the ohmic resistance in the battery model. The mathematical models are combined with the PNGV model in Matlab/Simulink to analyze the battery thermal performance under various discharging rates in the BCS. 87

103 In [84] it was found that the best-operating temperature for Li-ion batteries ranges between C with a uniform temperature distribution. Accordingly, the reference temperature T ref is set at 60 C o. The model parameters are those of a 400 kwhr pack of high power Li-ion battery type Figure 4.9. Li-ion battery operating temperature at different discharging rates. The battery thermal performance is shown in Fig. 4.9 under three different discharging rates. The temperature distribution between the battery pack cells is not shown in the simulation results as the battery pack is modeled as a lumped system. The simulation results clearly indicate that the air cooling system is not sufficient to reduce the heat of the battery pack at high charging and discharging rates. Although the temperature rise rate in the battery pack decreases with forced air cooling (at 60 C o ), a fully compatible air cooling system can only be efficient at relatively low discharging rates. Additionally, air cooling causes a non-uniform thermal distribution among the battery cells, which becomes even more evident during abusive conditions. Furthermore, the power density of Li-ion batteries is significantly limited at very low ambient 88

104 temperatures, while the air ability is very limited in terms of heating up the battery to the desired operating temperatures. B) Li-ion battery thermal energy management Designing a successful thermal energy management system is critical to the efficient and safe usage of Li-ion batteries in EVs and BCS applications. In addition to the desired temperature requirements, the thermal management system must also be compact, lightweight, small in size, and reliable. B.1. Thermal management using air and liquid The air cooling system inability to reduce the battery thermal stress to an acceptable range at high power demands limits its usage in EV applications regardless of its simplicity and compactness. Liquid thermal management systems can be designed using a number of methods [85]. Also, despite the additional complexity associated with the use of liquid as the heat transfer medium, results show that this is a more effective system compared to air cooling/heating the system. The main drawbacks of liquid thermal management systems are their bulkiness, complexity, and high cost. B.2. Thermal management using PCMs An effective battery thermal management system should be capable of maintaining the battery operating temperature within the desirable range without adding complexity and bulkiness to the system. A thermal management system is introduced in [86] using phase change material (PCM). 89

105 The PCM is integrated within the battery pack between the individual cells. Essentially, as the battery is discharged at high rates, its operating temperature increases causing the PCM to melt. The high latent heat of the PCM is capable of removing large quantities of generated heat. Moreover, as the battery temperature drops significantly, at cold surrounding temperatures, the latent heat stored in the PCM will be transferred to the module causing the pack temperature to rise. The effectiveness of the use of PCM for high power applications is shown in [87-88] under both normal and abusive conditions. A comparison between the PCM and forced air cooling under high current stress is conducted in [89], proving the superiority of PCM and its ability to maintain the Li-ion battery pack temperature below 55 C o at 6.67 C (10 A/cell). The availability of promising thermal management systems, such as PCMs, make high power charging systems increasingly more desirable. In this dissertation, 80 kw discharging rates are required to charge the EVs from a 400 kwhr BCS. This high power demand can be achieved using the advanced thermal management systems discussed and referred to in the literature Experimental Implementation An 80 kw CBB converter prototype is developed experimentally to verify the operational modes of the BCS as shown in Fig The control algorithms have been implemented using TI2812 digital signal processor. The ADC sampling and PWM switching rates are kept at 10 khz. 90

106 The performance of the rectifier is evaluated at different charging conditions. The experimental results show that the rectifier operates at % efficiency for 80 kw charging operation. Interleaving Bi-Directional DC/DC Converter Interfacing Board Rectifier Filtering Inductors Interleaving Inductors Figure BCS experimental setup. The operation of the DC-DC converter at the switching instants is observed in Figs , showing the DC-DC converter input voltage, output voltage, and the charging current, when the input DC bus voltage is 630 V and the command current is 174 A. Fig shows the efficiency curve with respect to the charging current of the AC- DC converter. The experimental results show that DC-DC converter designed for BCS is very efficient around the desired charging rates. 91

107 Grid Voltage 300 V (RMS) Grid Current 45.5 A (RMS) Input Power 9 kw Figure Input line voltage, current and power from the grid. Inductor Voltage 295 V (RMS) Output Voltage 340 V (RMS) IGBT Voltage 335 V (RMS) Inductor Current 20.9 A (RMS) Figure The operation of the DC-DC converter at switching instants. The BCS is tested under transient conditions to ensure a smooth and effective transient operation. Figs and 4.16 present the DC-DC converter input and output voltages, and the charging current under variable charging commands. In Fig. 4.15, the DC output current starts from zero and reaches to 50 A within 20.1 sec. and then maintains its value for 30 sec. before it is commanded for 90 A. The charging current successfully tracks the commanded rate with very smooth transition. In Fig. 4.16, the current starts from zero 92

108 and reaches to 90 A within sec. before being commanded to decay to 50 A. The charging current gradually decreases to 50 A following the commanded charging rate. Output Voltage 410 V (RMS) Input DC Voltage 630 V (RMS) Output Voltage 174 A (RMS) Figure DC-DC converter input voltage, output voltage and charging current. 100 Efficiency curve 90 Efficiency (%) I charging (A) Figure AC-DC converter efficiency curves with respect to the charging current. 93

109 Output Voltage 357 V (RMS) Input DC Voltage 655 V (RMS) Charging Current 69.4 A (RMS) Figure DC-DC converter input and output voltages and charging current for variable charging commands (0-50A-90A). Output Voltage 360 V (RMS) Input DC Voltage 622 V (RMS) Charging Current 71.3 A (RMS) Figure DC-DC converter input and output voltages and charging current for variable charging commands (0-90A-50A) Conclusion The proposed BCS is designed, developed and implemented for charging EVs. The developed system provides fast EV charging rates while being capable of maintaining a uniform demand distribution on the electrical grid. A comparison between the various high 94

110 power available bi-directional converters is presented in this chapter and the interleaved CBB converter is selected for the EVs charging application. The interleaving feature proved its effectiveness in reducing the current stress on the passive and active components while decreasing the voltage and current ripples at the output. The Li-ion battery electrical and thermal models are presented and the battery thermal stress is analyzed. It is concluded that the use of the available advanced thermal management systems such as PCMs is recommended in the proposed BCS. The experimental BCS is developed with 80 kw CBB converter and tested under various operating conditions. The test results validated the effectiveness of the BCS for EV charging infrastructure. In Chapter 5, the same CBB converter is analyzed to perform PFC for the grid AC mains voltage. It is desirable to operate the system with the same existing components while operating at a unity power factor and low current harmonics. 95

111 CHAPTER V POWER FACTOR CORRECTION USING CBB CONVERTER This chapter presents a new dual switch control structure for the AC/DC CBB converter used as the interfacing unit in the PV/battery grid tied system. The main purpose of the applied control is to utilize the CBB converter presented in Chapter 4 as a power factor correction (PFC) converter. Thus, a novel topology is shown in this chapter for achieving this goal. The AC/DC converter is designed and tested on a single phase system with the ability to extend the same topology concept to three phase systems. The proposed converter operates at a discontinuous capacitor voltage mode providing an inherent high power factor and a zero voltage turn-off switching. Additionally, the proposed control structure enables for a non-distorted sinusoidal current for a wide range of output voltage levels. Unlike the conventional methods, a mode detector is not required and consequently, there is no hard transition between the buck and the boost modes. Although both converter switches are controlled, only one feedback control loop is required to obtain the desired power flow at a unity power factor. The principle of operation, theoretical analysis, simulation, and experimental results of a 1.6 kw prototype grid-connected converter are presented. The results confirmed the validity of the proposed system under various operating conditions. 96

112 5.1. Introduction Power electronic connected loads need to comply with specification restricted by harmonic regulations and IEEE standards, such as IEC and IEEE 519 [90], [91], in order to maintain the power quality of the grid. Thus, along with the widespread applications of power electronic connected loads, the research on active power factor correction (PFC) techniques has taken on an accelerated path. Basic single stage up/down converter topologies such as buck-boost, Sepic, and Cuk, with or without an isolation transformer, are widely used in PFC applications [92-96]. Although these converters provide simple configurations for wide range of input/output voltage conversion ratio, their active and passive elements suffer from high stresses [97]. Further, the output voltage polarity inversion of the buck-boost and cuk converters renders them unsuitable for high voltage applications. In an attempt to mitigate the high stress on converter components, research has focused on dual switch non-inverting buck-boost converters. The cascaded buck-boost converter (CBB) shown in Fig. 5.1 was proved to be one of the most promising noninverting converters for high power applications [98-102]. The conventional CBB AC/DC converter control structure uses two complimentary modes of operation; Buck and Boost [103], [104]. The buck mode occurs by switching the buck switch (S 1 ) while keeping the boost switch (S 2 ) off when the sinusoidal input voltage (V i ) is higher than the output voltage (V o ). The boost mode takes place when V i is lower than V o and it is implemented by keeping S 1 on while controlling S 2. The main challenge facing such a structure is the need for a mode detector which requires the use of fast and precise voltage sensors for the input and output voltages. The sensor delay, coupled with the unaccounted voltage drops in the 97

113 converter components, lead to a discontinuity in the input current during the transition between the modes. Additionally, hard-switching between the two modes leads to high and unstable output voltage transients [105]. I ir L i I s1 L 1 I L L 2 I D2 I O I i I ci S 1 I D1 V L I s2 D 2 V i V r V ci C i D 1 V t S 2 V O C O R O Figure 5.1. CBB PFC Converter. Researchers have investigated these challenges by inserting an additional mode between the buck and the boost modes [106], [107]. A combination of buck and boost modes is introduced in [108], where the authors inserted two extra combinational modes; namely, pre and post buck-boost mode. Although this complicates the control structure, it yields higher efficiency. A pseudo-continuous conduction mode is proposed in [109] to achieve unity PFC by allowing the inductor current to freewheel during the buck-boost mode. The main drawbacks of such a topology are the lower system efficiency, due to the absence of a direct energy transfer path, and the sensitivity of the output voltage to the duty ratio variations. In [110], the converter is controlled to switch between an initial phase and either the buck or the boost modes in every switching cycle. Although this structure may decrease switching losses, the absence of a freewheeling path and the inability to switch more than one active element every cycle requires higher switching frequency operation. A digitally controlled stepwise technique is applied in [111] to prevent the instability 98

114 caused by the mode transitions. However, this limits the converter capability of accurately tracking a reference signal during the transition mode due to the constraints introduced to the duty ratio compensator. In this chapter, simultaneous dual switch control for PFC operation of the CBB converter is proposed. The proposed control structure eliminates the transition between the different modes while using only one feedback control loop. Thus, there is no need for a mode detector or a precise output voltage sensor. The CBB converter shown in Fig. 5.1 operates in discontinuous conduction mode (DCM) with the proposed controller. Unlike continuous conduction mode (CCM), DCM operation provides inherent PFC features which significantly reduces the high switching frequency requirement [93], [102], [ ]. Discontinuous inductor current mode (DICM) is a widely used DCM control technique applied to various PFC converters [107], [ ]. However, DICM causes high current stress on the converter switches, and it faces a challenging design for the input capacitor required to balance the power and provide a continuous input current without imposing any inrush currents into the system. A dual alternative to DICM is applied in this chapter by operating the converter in a discontinuous capacitor voltage mode (DCVM) [124]. DCVM is achieved by placing a small capacitor (C i in Fig. 1) at the converter input and forcing it to discharge to zero voltage every switching cycle in order to obtain a unity power factor and a continuous input current. The proposed simultaneous control structure allows for an extended DCVM range of operation leading to the enhancement of the converter inherent PFC features. Moreover, the switching frequency is noticeably decreased while maintaining a high power factor and a low output voltage ripple. Thus, 99

115 while both series converters switch simultaneously, the significant reduction achieved in the switching frequency is projected to increase the system efficiency. Further, the converter possesses a zero turn-off switching voltage and a zero turn-on diode voltage in the buck stage DCVM Principle of Operation The applicability of DCVM on single stage converters, such as buck and Cuk converters, for PFC purposes, has been studied in the literature [ ]. The use of DVCM was also reported on the Sheppard-Taylor converter for the same purposes [ ]. To the best of the authors knowledge, DCVM operation for a dual stage converter has not appeared in the literature. CBB converter operation in DCVM is analyzed in this section based on a simultaneous dual switch control. The converter shown in Fig. 1 consists of two series converters, buck, and boost. The buck converter is designed to work in DCVM while the boost converter is designed to work in CCM, as the inductor current is continuous. As explained in [135] there are three states for any DCVM converter, while there are only two complimentary states for CCM converters. In CCM mode, the converter state can be denoted according to the switch position, 1 means that the switch is on, and 0 means that the switch is off. In DCVM mode, the position of the switch and the diode are individually denoted by 1 and 0 (1 =on, 0 =off). Thus, the two-stage converter states in the CBB can be expressed as X 1 - X 2 - Y. Where X 1 represents the state of S 1, X 2 represents the state of D 1, and Y represents the state of the boost converter. 100

116 The converter is analyzed assuming that the input current (I i ) is constant over one switching cycle, the capacitor (C i ) has a low enough capacitance to operate in discontinuous mode, the total inductance (L = L 1 + L 2 ) is big enough to ensure that I L is continuous. The characteristic waveforms of CBB converter over one switching cycle are presented in Fig. 5.2 and 5.3 for the buck and the boost portions respectively. The converter is analyzed assuming that the input current (I i ) is constant over one switching cycle, the capacitor (C i ) has a low enough capacitance to operate in discontinuous mode, the total inductance (L = L 1 + L 2 ) is big enough to ensure that I L is continuous. The characteristic waveforms of CBB converter over one switching cycle are presented in Fig. 2 and 3 for the buck and the boost portions respectively. A. Buck Stage Analysis Vci T 1-0-Y 1-1-Y 0-1-Y Ici T 1-0-Y 1-1-Y 0-1-Y Vcp IL - Iir Y=1 Y=0 De D1 1-D1 t De D1 1-D1 -Iir t a) Input capacitor voltage. b) Input capacitor current. IL T VL T Y=1 Y=0 Y=1 Y=0 De D1 1-D1 t De D1 1-D1 Vo t c) Converter inductor current. d) Converter inductor voltage. Figure 5.2. Waveforms of the buck stage intervals. 101

117 Vs1 T VD1 T Vcp Vcp De D1 1-D1 t De D1 1-D1 t e) Buck switch voltage. f) Buck diode voltage. IS1 T Y=1 Y=0 ID1 T Y=1 Y=0 IL IL - Iir IL De D1 Iir 1-D1 t De D1 1-D1 t g) Buck switch current. h) Buck diode current. Figure 5.2. Waveforms of the buck stage intervals. (Cont'd.) For the interval (0 < t D e T): The converter switching state is 1 0 Y, V C i is discharged from the peak voltage (V cp ) to zero as shown in Fig. 5.2.a. As the value of Y changes, I L changes, and thus I C i slope varies as shown in Fig. 5.2.b. The current and the voltage waveforms of L are observed in Fig. 5.2.c and 5.2.d. S 1 and D 1 voltages are shown respectively in Fig. 5.2.e and 5.2.f. Notice that I D1 (Fig. 5.2.g) is zero as the diode is switched off, while the I s1 follows I L as shown in Fig. 2.h. V C i For the interval (D e T < t D 1 T): The converter switching state is 1 1 Y. is zero through this state. The voltage across the active elements is zero as they are both on. I s 1 is equal to I ir while I D1 is equal to the difference between I L and I ir. 102

118 For the interval (D 1 T < t T): The converter switching state is 0 1 Y. At this state, the diode D 1 is conducting while the switch S 1 is turned off and the input capacitor is charged. As S 1 is turned off, I C i is equal to I ia. The dependency I L on the boost converter switching state is is the key of the proposed control structure it can be observed from Fig. 5.2.e 5.2.h that switch S 1 is turned off at zero voltage while diode D 1 is turned on at zero voltage. This is a method of soft switching which enhances system efficiency by decreasing switching losses [ ]. For the interval (0 < t D 2 T): The converter switching state is X 1 X 2 1. I L passes through S 2 and V O is applied to D 2. For the interval (D 2 T < t T): The converter switching state is X 1 X 2 0. This state is the compliment to the previous one. B. Boost Stage Analysis VS2 X1-X2-1 T X1-X2-0 VD2 X1-X2-1 T X1-X2-0 VO VO D2 1-D2 t D2 1-D2 t a) Boost switch voltage. b) Boost diode voltage. 103

119 IS2 X1-X2-1 T X1-X2-0 ID2 X1-X2-1 T X1-X2-0 X1 - X X1 - X IL IL D2 1-D2 t c) Boost switch current. d) Boost diode current. Figure 5.3. Waveforms of the boost converter intervals. (Cont'd.) D2 1-D2 t 5.3. Converter Design Equations and Characteristics Following the principle of operation explained in Section II, yields For (0 < t D e T s ): C i dv ci dt For (D 1 T s < t T s ): C i dv ci dt = I L I ir (5.1) = I ir (5.2) V cp = I ir(1 D 1 ) f s C i (5.3) where V cp is the peak voltage of the input capacitance shown in Fig. 5.2.a and f s is the switching frequency. Now, let m be the CBB converter conversion ratio; that is m = V 0 V r (t) = V 0 V t V t V r (t) (5.4) where V r (t) is the rectified input voltage, V t is the low frequency average of the intermediate voltage as shown in Fig From Fig. 5.2.f; 104

120 V t = V D1 = D ev cp 2 V r = V ci = (1 D 1 + D e ) V cp 2 (5.5) (5.6) As the Boost converter operates in the CCM. m = V O V r (t) = D e (1 D 2 ) (1 D 1 + D e ) (5.7) D e = V O(1 D 2 ) (1 D 1 ) V r (t) V O (5.8) where V O = V O (1 D 2 ) In order for the CBB converter to operate in DCVM, the value of D e should be less than D 1 (Fig. 5.2.a). Since D e is inversely proportional to V r (t) V O, it is possible to extend the DCVM interval by controlling D 2 appropriately. A. Inherent CBB converter PFC features in DCVM The input impedance of a PFC converter needs to be either zero-order or near zero-order for the converter to have inherent PFC features. From Eqns. 5.3 and 5.6, it can be seen that Z i (t) = V r(t) I ir = (1 D 1)(1 D 1 + D e ) 2 f s C i (5.9) Thus, by combining (5.8) and (5.9) yields Z i (t) = (1 D 1) 2 V r (t) [ 2 f s C i V r (t) V O (1 D 2 ) ] (5.10) 105

121 Z i (t) = (1 D 1) 2 [1 + V O 2 f s C i V r (t) + V O V r (t) 2 + ] (5.11) 2 Thus, it can be concluded that the CBB PFC converter operating in DCVM has a near resistive impedance as long as V O is smaller than the input voltage V r (t). As the sinusoidal input voltage decreases near the zero crossing area, V O should decrease accordingly in order to sustain the PFC features. B. CBB design limitations to operate in DCVM A design equation for D e may be derived as follows P i = P O (5.12) I ir I O = D e (1 D 2 ) (1 D 1 + D e ) (5.13) I ir = V O D e R (1 D 2 ) (1 D 1 + D e ) (5.14) Now, Eqns. 5.3 and 5.6 imply V r = V ci = (1 D 1 + D e ) (1 D 1 ) I ia 2 fc i (5.15) Using Eqns. 5.8 and 5.15 lead to V O = D e (1 D 1 ) I ir 2 f s C i (1 D 2 ) (5.16) While Eqns and 5.16 combine to give D e = kd 2 [D D 2 + D D k ] (5.17) 106

122 as k = f s C i R, D 1 = (1 D 1 ) and D 2 = (1 D 2 ). Eqn represents the condition for the converter to operate in DCVM; that is, D e D 1 (5.18) From the foregoing, the converter conversion ratio may be re-written as m = k [D 2 + D D 1 2 k ] D k D2 [D 2 + D D 1 2 k ] (5.19) Eqn holds only if Eqn is satisfied. Consequently, Eqn. 5.20, derived from Eqns and 5.18, gives the upper limit of the designed input as shown in (5.20). Fig. 5.4 shows the maximum allowed input capacitance (C i ) for the converter to operate in DCVM as in Eqn If the capacitance is higher than the critical designed value at the working duty ratio, the CBB converter will operate in CCM and will thus loose its inherent PFC features. In Fig. 5.4, the plot lines represents the limit of the converter operation in DCVM at different conditions. It can be observed that as the designed C i decreases, the converter works in DCVM over a wider range of the duty ratio (D 1 ). The impact of the change of the boost converter duty ratio (D 2 ) is also observed demonstrating that as D 2 increases, the same C i can cover a wider range of D 1 while still operating in DCVM. 107

123 Figure 5.4. Maximum input capacitance designed at different D 1 and D 2 duty ratios. The lower limit of the designed input capacitor is determined by the peak voltage permitted on the capacitor (C i ) according to Eqn. (5.3). Consequently, Eqn. 20 may be written. I ir(1 D 1 ) V cmp f s C i D 1 2 (1 D 1 ) 2 R f s (1 D 2 ) 2 (5.20) where V cmp is the maximum permitted instantaneous voltage applied on the input capacitor C i at a desired input power Simultaneous Dual Switch Control The proposed control structure in this chapter utilizes both the buck and the boost converter stages simultaneously without the need for any transition or a mode detector. Voltage and current control loops are conventionally used in CBB converter applications, such as in adjustable speed drives, and electric vehicles (EV) charging infrastructures [98], [138]. 108

124 Vi(t) TDPLL t Ii(t) Grid Voltage and Current dq transformations i d P Controller i q Q Controller Vd Vq Id P = 1 2 (V di d + V q I q ) Q = 1 2 (V qi d V d I q ) Iq P Q P Q Figure 5.5. The outer control loop for current reference generation. PQ control is applied in the proposed control structure. An efficient transport delay phase lock loop (TDPLL) topology is implemented to detect the grid frequency and phase [139]. The DQ transformation block equations are shown in ( ) where X is V and I for the voltage and the current transformations respectively. The single phase sinusoidal quantities can be represented in two phase coordinates as X α = X i cos ( t) (5.21) X β = X i sin ( t) (5.22) It would be convenient to represent the two-phase quantities in rotating reference frame using the following transformations. [ X d cos ( t) X ] = [ q sin ( t) sin ( t) cos ( t) ] [X α X ] (5.23) β The actual active and reactive power are calculated as per the equations shown in Fig The settings for the reference active (P ) and reactive power (Q ) are then 109

125 compared to the actual measurements in order to generate the reference direct and quadrature current values. The first stage switch (S 1 ) is responsible to track the dq current values generated from the outer control loop. While the second stage switch (S 2 ) is controlled in such a way to extend the DCVM operation and enhance the converter PFC features. In the studied configuration, it is always desirable to operate at unity power factor so that the reactive power outer control loop is not needed and thus the reference direct current (i d ) is the only reference current value used for the inner control loop. A feedback control is used to find the error between the reference and the actual direct axis input currents. This error is compensated for to generate the required duty ratio, which in turn, is compared to a saw-tooth carrier signal to give the desired PWM for switch S 1. A new open loop control structure is applied to the second stage switch S 2 as it was found in Section III that the boost converter duty ratio can play a significant role in enhancing the PFC features of the CBB converter by extending the DCVM range. It can be concluded from (5.11) that the value of the duty ratio (D 2 ) should be inversely proportional to the magnitude of the grid voltage (V i ). In other words, the duty ratio should be the highest near the zero crossing area and the lowest at the peak value of V i. 110

126 1 y 0-1 π/2 π 3π/2 2π Sin(x) Vdr x Figure 5.6. The delayed reference signal used for the boost converter switch PWM. The main aim of the control applied to the boost converter stage is to achieve the desired performance without the need for an extra feedback control loop or any additional sensors. The control structure uses the TDPLL to obtain the instantaneous angle of the input voltage and introduces a delay of a 1 4 of a cycle. The absolute value of this signal is denoted as V dr. Fig. 5.6 shows V dr relative to the original sin( θ) obtained from the implemented TDPLL. The duty ratio d 1 is used as an input to a lookup table which gives a value from 0 to 1 of a multiplier factor (m r ) to be multiplied with the signal V dr in order to generate the duty ratio d 2. The duty ratio d 2 is generated to enhance the converter PFC features. However, the minimal value of d 2 that can maximize the system power factor is always desired in order to reduce the current stress on the converter components. This tradeoff is discussed in Section VI. Detailed explanation on the proposed formation of the lookup table is provided in the Subsection

127 PWM 1 L i S 1 L D 2 I O I i V i C i D 1 S 2 C O V O R O PWM 2 V i (t) I i (t) TDPLL Power Calculation and Outer Loop Control i d Delay - Sin(u) V O I i (t) Compensator V dr Lookup table i d I e d 1 m r T s - - Figure 5.7. The simultaneous dual switch control structure for CBB PFC converter. The block diagram for the overall proposed dual structure control is shown in Fig. 5.7, where is the grid angle, i d and i d are the actual and the reference direct axis signals of the input current, and I e is the current error fed into the designed compensator to generate the desired duty ratio. While a dual switch control is applied on two switches, only one feedback control loop is required as shown in Fig The second stage converter is controlled using the delayed signal of the sinusoidal input voltage angle and the generated multiplier factor from the lookup table Low Frequency and Small Signal Modeling In this section, a low-frequency averaged behavior model of the CBB converter operating in DCVM is developed. The averaged model is then used to obtain the small signal characteristics of the system. 112

128 A. Low Frequency averaged Model Referring to Figs. 5.1 and 5.2, and assuming that the input capacitor operates in the discontinuous mode, V r is constant over a switching cycle, L is large enough to have a negligible ripple in its current, and C O is large enough to have negligible voltage ripple. The following equations can be written. I ir (1 D 1 ) + (I ir I L )D e = 0 (5.24) D e = I ir(1 D 1 ) I L I ir (5.25) Combining Eqns. 5.3, 5.5, 5.6 and 5.25 yields V ci = I iri L(1 D 1 ) 2 2f s C i (I L I ir) V D1 = I 2 ir (1 D1 ) 2 2f s C i (I L I ir) (5.26) (5.27) Thus the CBB converter can now be simplified to an averaged buck circuit followed by the boost converter. A circuit averaging model technique is then used to model the boost converter. Essentially, the input voltage of the boost converter is the low-frequency buck diode voltage obtained from the buck converter model. That model, shown in Fig. 5.8, allows one to obtain the system low-frequency transfer functions, which may then be linearized to get the small signal characteristics of the input current and the output voltage relative to the source variations. 113

129 L i L 1 D 2 V i V Ci V D1 1 D 2 C O 1 D 2 R O (1 D 2 ) V O Figure 5.8. Averaged model of the CBB converter. The accuracy of the low frequency model shown in Fig. 5.8 is demonstrated by comparing the output voltage resulting from two circuits. The first circuit is the exact simulated circuit of the CBB converter (Fig. 5.1) modeled in Simulink/Matlab framework, while the second circuit is the averaged model shown in Fig The values used in the comparison are: V i = 100 V, D 1 = 0.4, and D 2 = 0.5. Voltage (V) Simulated Vo Modeled Vo Time (s) Figure 5.9. Simulated and modeled low-frequency output voltage. From the averaged model, it can be concluded that 114

130 I ir (s) = V i(s) V ci (s) sl i (5.28) V o (s) V D1 (s) = (1 D 2 ) LC O (s 2 + s 1 RC + (1 D 2) 2 O LC ) O (5.29) B. Small-Signal Model To find the response of the input current (I ir ) and the output voltage (V O ) to variations of D 1, I ir, and D 2 small ac perturbations are introduced into Eqn and 5.28 such that v ci = V ci + V ci = f(d 1, I ir, I L) + k 11 d 1 + k 12 I ir (5.30) v D1 = V D1 + V D1 = f(d 1, I ir, I L) + k 21 d 1 + k 22 I ir (5.31) where v ci and v D1 are the input capacitor and the buck diode voltages, V ci and V D are the low frequency voltages of the input capacitor and the buck diode respectively. While V ci and V D1 are the ac perturbed capacitor and buck diode voltages. Similarly d 1 = D 1 + d 1,d 2 = D 2 + d 2, v o = V 0 + V o, i L = I L + I L, and i ir = I ir + I ir. It is clear from Eqns that I ir is only affected by D 1, while V o is a function of D 1, I ir, and D 2 such that k 11 = dv ci = I iri L(1 D 1 ) dd 1 f s C i (I L I k 21 = dv D1 dd 1 ir) = I ir2 (1 D1 ) f s C i (I L I ir) (5.32) (5.33) 115

131 k 22 = dv D1 di ir 2 = 2C ii ir (I L I ir) C i I ir (5.34) (I L I ir) 2 L i I ir k 21 d 1 L 1 D 2 V i k 11 d 1 1 D 2 k 22 I ir C O 1 D 2 R O (1 D 2 ) V O 1 D 2 (a) (b) L 1 D 2 d 2V o 1 D 2 C o 1 D 2 R O (1 D 2 ) V O d 2I L 1 D 2 (c) Figure Linearized circuits for obtaining the output responses relative to the source variations. (a) Linearized circuit for input current response to D 1 variations. (b) Linearized circuit for output voltage response to D 1 variations. (c) Linearized circuit for output voltage response to D 2 variations. Thus three linearized circuits in Fig represent the response of I ia to the variations of D 1, the response of V o to the variations of D 1, and the response of V o to the variations of D 2 respectively. 116

132 The input current response is evaluated from Fig a for the buck stage duty ratio perturbation as I ir (s) d 1(s) = I iri L (1 D 1 ) sl i f s C O (I L I ir ) (5.35) As the buck converter switch is operated to regulate the input current, Eqn may be used to design the desired input current compensator shown in Fig Further, as the system is first order, with one pole at the origin, a PI controller with a low proportional gain is designed to ensure system stability and to track the sinusoidal reference current. The PI-compensated open loop plant transfer function is given by Eqn Essentially, the plant poles and zero will force the closed loop system to operate in the left half plane, thereby ensuring stability for all positive the system gains. G p (s) = 0.05 I iri L (1 D 1 ) (s + 200) L i f s C O (I L I ir ) s 2 (5.36) The output voltage response is evaluated from Fig b for the buck stage variations (the input duty ratio and the input current) separately results as: V o(s) d 1(s) = (1 D 2 ) k 21 LC O (s 2 + s 1 RC + (1 D 2) 2 ) LC O V o(s) I ir (s) = (1 D 2 ) k 22 LC O (s 2 + s 1 RC + (1 D 2) 2 LC ) O (5.37) (5.38) The variation in the output voltage in response to the boost converter duty ratio perturbation can be represented as: 117

133 V o(s) d 2(s) = I L (s V O (1 D 2 ) I L L ) C O (s 2 + s 1 RC + (1 D 2) 2 LC O ) (5.39) The proposed converter can have an additional closed loop control in which the boost stage switch is regulating the output voltage. In such a scenario, Eqn can be used to design the required output voltage compensator. This option is not applied in this chapter, as only one feedback control loop is used to simplify the control The construction of the lookup table for the boost stage The purpose of the m r lookup table is to enhance the converter PFC features while imposing the least possible current stress on the converter components. It is clear from table 5.1 that as D 2 increases, the inductor current increases. Thus it is desirable to operate the converter at the least D 2 that will provide the required power factor. m r = 0.9 m r = 0.5 m r = 0.1 Figure The reference and the actual input current at different values of m r. 118

134 The waveforms of the reference input current, the actual input current, and the inductor current are shown in Figs. 5.11, and 5.12 at a power level of 430 W. It is observed from the figures that for 3 different values of m r, the system power factor varies as well as the current stress on the inductor. For m r = 0.9, the power factor was high but it imposed a high current stress on the converter. While for m r = 0.5, a high power factor is achieved at a lower current stress. Finally for m r = 0.1, the input current is discontinuous near the zero crossing zone, which yields to a higher current stress due to the accumulation of the current error in the PI controller. m r = 0.9 m r = 0.5 m r = 0.1 Figure The inductor current at different values of m r. Consequently, it is concluded that the lowest current stress that can be applied to the converter is achieved at the minimum m r that provides continuous current from the grid. This value is also the maximum m r value that forces the inductor current to reach zero during the zero crossing zone of each fundamental cycle. In the upper case m r = 0.5 is the minimum value providing continuous current which is also the maximum value that forces I L to zero in every zero crossing instant. 119

135 Thus, the aim of the lookup table is to find the maximum value of m r that will force the inductor current to zero at the zero crossing zone in the fundamental cycle. So an estimator for the inductor current of the CBB converter is built and used to form the lookup table. The converter intermediate inductor voltage for one switching cycle can be written as: where D e = 1 D e, so L i t = V D1 D e D 2 + (V D1 V o )D e D 2 V o D e D 2 (5.41) I L = T s L [V D1 D e V o D 2 ] (5.42) To discretize the system, it can be found that from (5.3) and (5.5) V D1 (n) = D e(n)d 1 (n) I irp sin (w n N T) f s C i (5.43) From Fig. 5.6 D 2 (n) = m r cos (w n T) (5.44) N D e (n) = kd 2 (n) D 1 (n) [D 2 (n) + D 2 2 (n) + 2D 1 (n) 2 ] (5.45) k where D 1 (n) = 1 D 1 (n), and D 2 (n) = 1 D 2 (n) Consequently, 120

136 N 1 I L (n + 1) = I L (n) + T s L [V D 1 (n)d e (n) V O D 2 (n)] n=0 (5.46) where T = 1 f, and N = T 2T s The optimal m r value (m ropt ) is found by computing the set of solutions of m r when (5.46) is equal to zero. Then Eqn is applied, where n s is the number of the computed solutions. n s m ropt = max { m ri } (5.47) i=1 The construction of the lookup table is done offline. Additionally, if the load is preknown, then V o does not need to be an input to the lookup table as it can be estimated from the power balancing equation. The memory allocation of the lookup table can be reduced by discretizing both, the input values and the final optimal solution of m r Components Design and Simulation Results A. Converter Components Stress and Design The power circuit components are designed based on the peak stress applied throughout the different operation modes. Thus, table 5.1 is constructed to show the maximum stress applied to the active and passive elements of the developed converter. The peak inductor current is derived from the state (1-0-1) as the maximum inductor current passes when both of the switches (S 1 and S 2 ) are on. I LP is the peak current passing through the intermediate inductor (L) and 121

137 I avg = V i rms I irms R 1 (1 D 2 ) (40) Table 5.1. Maximum voltage and current stress applied on the converter elements. C i S 1 D 1 V peak I ir (1 D 1 ) f s C i V cp V cp I peak I LP I ir I Lp I Lp L S 2 D 2 V peak V cp V o V o I peak I avg + 1 2f s L D ev cp I Lp I Lp The most critical circuit element to be designed is the input capacitor. The capacitor is designed at a 10 Ω load resistance. In order for the designed capacitance to satisfy Eqn. 5.20, the maximum allowable voltage (V cmp ) is determined to be less than 450 V at an input current value of 5 A. For the design convenience, the grid current and voltage are assumed to be constant during one switching cycle. Thus C i is chosen to be 0.75 µf. While the intermediate inductor is chosen to be 0.8 mh. B. Simulation Results and Discussion Simulations to verify the proposed structure are presented in this section and the results are analyzed. Additionally, a comparison is carried out between the proposed control structure and other control structures found in the literature. 122

138 The circuit is evaluated at a relatively low switching frequency of 9 khz, as was mentioned earlier that one of the main objectives of the proposed control structure is to decrease the switching frequency to yield higher system efficiency. The simulation waveforms for a sinusoidal reference current of 5 A peak is shown in Fig Notice that the input current of Fig a and the grid voltage of Fig b have the same phase. It should be also noted that, although the output voltage and the sinusoidal input voltage overlap, but no transients are caused due to the elimination of the mode selector. The duty ratios of both the buck and the boost switches are introduced in Fig c, as duty ratio (D 2 ) is equal to the absolute value of sin( -90 ) multiplied by the multiplier factor (m r ), while the duty ratio (D 1 ) is fed through a feedback dq current control loop. The discontinuous input capacitor voltage is shown in Fig d indicating the validation of the designed capacitance. The simulation results of the input and output currents at two more power levels are shown in Fig. 5.14, where the sinusoidal reference current is regulated at 10 A and 2.5 A respectively. The proposed structure proved its effectiveness at a wide range of power levels with the need of only one feedback control loop. The minimum current supplied from the grid is limited in this system to the value shown in Fig b as for lower input current, a low duty ratio d 1 will need to be adopted. According to (5.20), a low d 1 will limit the upper value of the capacitor C i, unless the duty ratio d 2 operates near unity which decreases the system efficiency. Thus for very low input currents, the input capacitor shall be redesigned or else the switching frequency can be controlled accordingly. 123

139 a) Sinusoidal input and load output currents. b) Sinusoidal input and output load voltages. c) Buck switch (S 1 ) and boost switch (S 2 ) duty ratios. d) Input Capacitance (C i ) discontinuous voltage. Figure Simulation waveforms for the proposed CBB PFC converter at 5 A input current level. a) Reference input current at 10 A. b) Reference input current at 2.5 A. Figure Input and output current waveforms at different reference current values. A comparison of the input current waveforms is carried out between the conventional mode selector control and the proposed simultaneous control at the same switching frequency. The results shown in Fig illustrates the presence of the current transients in the conventional mode selector control relative to the proposed simultaneous dual switch control. The THD comparison between the proposed simultaneous control and 124

140 the conventional complementary control is shown in Table 5.2, where I ip is the peak value of the input current. Table 5.2. Comparison of the THD values of the input current for different peak values of I ip. Input peak current Proposed simultaneous control Conventional complementary control I ip = 4 A 6.7 % 24 % I ip = 6 A 6.5 % 18 % I ip = 8 A 6.4 % 28 % Mode Transitions Figure Current waveforms for the conventional mode selector control at 6 A reference current. Another comparison of the current stress on the converter elements is added between different control structures utilizing the PFC CBB converter. As shown in Table 5.1, the inductor current is decisive for the rest of the converter switches and diodes. Consequently, a comparison between the inductor current stresses over a grid cycle is presented for: a) Buck based control structure (Fig a), where only the switch of the buck converter (S 1 ) is controlled, and S 2 is open. 125

141 b) Mode selector control (Fig b), as in [ ]. c) Independent simultaneous dual switch control (Fig c), where the control structure shown in Fig. 7 without the use of the multiplier factor (m r ). d) The proposed simultaneous dual switch control shown in Figs. 5.5 and 5.7 are adopted (Fig d). a) Buck based control. b) Mode Selector control. c) Independent simultaneous dual switch control. d) Proposed simultaneous dual switch control. Figure The inductor current waveforms for different control structures at 500 W power level. It is clear from the presented Figs. that the buck based control suffers from high current stress caused by the discontinuity in the input current. It is concluded from Figs c and 5.16.d that the coupling between the duty ratios D 1 and D 2 reduces the current stress significantly on the converter components without distorting the input current waveform. Thus the enhanced performance of this topology does not impose high additional current stress compared to the mode selector control. 126

142 The system dynamics are tested under different operating conditions and various changes. A reference power change is commanded in Fig from 340 W to 680 W. The smooth transition verifies the system stability under varying commands. The circuit is then tested under a sudden load change in Fig The results show that the reference power of 425 W is maintained and the current is restored in two grid cycles. Change in Ref. Current Figure The system dynamics for a sudden change in the reference power from 340 W to 680 W. Testing the dynamics of the designed system at sudden voltage variations is important in todays energy market. A sudden change of the electrical grid voltage is applied to the proposed converter and the results are shown in Fig It is observed that a sudden increase of the grid voltage from 170 V to 180 V results in a decrease in the peak value of the grid current from 5 A to 4.72 A to maintain the extracted power at 425 W. The presented CBB PFC converter with its associated control structure can operate over a wide input voltage range as long as the constraints in (5.17) and (5.21) are 127

143 maintained by keeping the input capacitance value within the operating limits and by ensuring that D e is less than D 1 during the whole operation cycle. Change in the load Figure The system dynamics for a sudden change in the load from 10 to 5 Ω. 170 v 180 v Figure The system dynamics for a sudden increase in the grid voltage from 170 V to 180 V. 128

144 The voltage and current stress waveforms on the first stage switch (𝑆1) and diode (𝐷1 ) are shown in Fig The waveforms demonstrate the zero turn-off switching voltage and the zero turn-on diode voltage in the buck stage. a) Switch voltage and current over 25 ms time interval. b) Switch voltage and current over 600 μs time interval. c) Diode voltage and current over 25 ms time interval. d) Diode voltage and current over 600 μs time interval. Figure Voltage and current stress over the active switching elements in the buck stage It is clear from Fig that the buck stage MOSFET and diode voltage stress waveforms are decided by the peak voltage applied to the input capacitor (𝐶𝑖 ). As previously shown in (5.3) that the input capacitor peak voltage (𝑉𝑐𝑝 ) is inversely proportional to the switching frequency (𝑓𝑠 ) and the capacitance value. Any increment in the capacitance value has to be done while considering the capacitance upper limit shown in (5.20). Increasing the switching frequency would directly decrease 𝑉𝑐𝑝, and consequently will decrease the peak values of the voltage stress applied on the active 129

145 components in the buck converter. It is also important to understand that the peak voltage is only applied during the peak value of the grid cycle, while the voltage value degrades to zero at the zero crossing interval on the input capacitor as well as on the active elements. In the presented work, the switching frequency was chosen to be fixed at 9 khz while maintaining V cp at 450 V for an input current value of 5 A. As the proposed converter provides zero turn-off switching voltage and the zero turn-on diode voltage in the buck stage, then the switching losses are significantly reduced even at higher voltage levels. Although the two converter stages are operating simultaneously, the switching losses are noticeably decreased. Verily, the selection of the switching frequency is independent of the mode of operation. However, the realization of a pure power factor requires much faster controlled switching in the CCM compared to the DCM. This is due to the near resistive nature of the cascaded buck boost converter operating in DCVM. This nature enables the system to achieve a pure power factor without the need for a fast switching as in CCM. Thus, a much lower switching frequency is needed when operating in DCVM compared to the CCM mode of operation Experimental Results Figure CBB PFC prototype converter. 130

146 A laboratory prototype of 1.6 kw unit, operating with 120 V at 60 Hz grid was built (Fig. 5.21) to validate the theoretical and simulation results. The circuit in Fig. 5.1 is implemented using a capacitor (C i ) of 0.75 µf, a converter inductor of 0.8 mh, a switching frequency of 9 khz, and a digital signal processor. The experiment is implemented in two stages. The first is to apply the control on the buck converter to test its PFC features while the boost converter switch is kept open. The results of this test are shown in Fig The proposed simultaneous dual switch control is then applied to eliminate the discontinuity portions found in the input current by achieving a unity power factor at an overlapping input/output voltage. Consequently, the proposed control structure is experimentally implemented on the prototype. Fig a shows that the input current is continuous and in phase with the voltage after applying the simultaneous control. The sinusoidal input current is achieved while limiting any undesirable transients. The continuous operation of the converter in DCVM is clearly shown in Fig b without exceeding the capacitor upper limit designed voltage. The input current and the capacitor voltage are shown on short time intervals in Fig c. The system is then tested at the full rated power of 1.6 kw in Fig to demonstrate the proposed design effectiveness over a wide power range while maintaining a pure power factor as shown in the results. The system dynamics are then experimentally tested under the starting conditions and the reference active power variations. The starting conditions waveform results for the system of 460 W are shown in Fig The change in the reference power is then 131

147 conducted from 700 W to 500 W in one second, then the reference power varies again from 500 W to 1200 W in the next second as shown in Fig a. The results are shown in the Fig. proving the system dynamic ability and fast response for varying reference commands. Fig b shows the time of command change from 500 W to 1200 W to demonstrate the smooth transition achieved using the proposed control structure for the PFC CBB converter. The variation of the output voltage with the input power is expected in this experiment. Input current discontinuity a) Grid voltage and grid current waveforms. b) Input capacitor voltage waveform Figure Experimental waveforms of 315 W reference active power while only controlling the buck switch 132

148 c) Short interval Input capacitor voltage and grid current waveforms. Figure Experimental waveforms of 315 W reference active power while only controlling the buck switch (Cont'd.) a) Grid voltage and grid current waveforms. b) Input capacitor voltage waveform Figure Experimental waveforms of 355 W reference active power using the simultaneous control. 133

149 c) Short interval Input capacitor voltage and grid current waveforms. Figure Experimental waveforms of 355 W reference active power using the simultaneous control. (Cont'd.) Figure Experimental waveforms of 1.6 kw reference active power using the simultaneous control at 4.2 Ω load (1- Grid voltage, 2- Grid current & 3- Output voltage, for 10 ms/div). 134

150 Figure Experimental waveforms at the starting conditions for the system of 460 W reference active power and 4.2 Ω load (1- Grid voltage, 2- Grid current & 3- Output voltage, for 40 ms/div). As the load is chosen to be a resistive load and according to the energy conservation rule, the output voltage is directly proportional to the input current variations. The change in the reference power in these results model the dynamics of the system at load changes. As the change in any load is reflected in a new reference power that is commanded from the DSP controller. This can be applicable for battery charging systems where the charging rate is decisive to the amount of power fed from the grid to the battery through the CBB converter. a) The change of the reference power from 700 W to 500 W, then to 1200 (for 400 ms/div) Figure Experimental waveforms at a varying reference power of 4.2 load (1- Grid voltage, 2- Grid current & 3- Output voltage). 135

151 b) The change of the reference power from 500 W to 1200 (for 10 ms/div) Figure Experimental waveforms at a varying reference power of 4.2 Ω load (1- Grid voltage, 2- Grid current & 3- Output voltage). (Cont'd.) Figure Experimental waveforms at a varying input voltage (1-Grid voltage & 2- Grid current). The system dynamics under varying input voltage is shown in Fig The voltage is increased from 110 RMS voltage to 140 RMS voltage at 3 seconds. As the reference power is maintained at 350 w, then the CBB converter responds by decreasing the current accordingly as shown The PFC Extension for three Phase Systems A similar analysis of the preceding Subsections is applicable to the three phase AC/DC CBB converter shown in Fig The main distinction in designing the system 136

152 will result from the need to place the small capacitor along with the filtering inductor on the AC side of the bridge diode rectifier. Additionally, the capacitors (C i ) sizing need to be re-selected according to the higher voltage stress due to the imposition of line to line voltage on the capacitor compared to line to neutral voltage in the single phase operation. In this topology, the switch S 1 controls the current of phases A, B, and C sequentially. While the signal V dr shown in Fig. 5.6 is updated according to the new control structure where the single reaches its peak value at the moment of switching the control between two phases. I s1 L 1 I L L 2 I D2 I O S 1 V L D 2 N V a V b V c L i C i I D1 D 1 V t S 2 I s2 V O C O R O Figure Three phase PFC CBB converter. More three phase configurations can be found in the literature and the analysis of their applicability with the presented non-inverting Buck-Boost converter is a topic covered in the future work shown in Chapter Conclusion The CBB converter used as the interfacing power electronic system in the PV/battery grid-tied application is being utilized for the purpose of PFC. In this study, the converter operates in DCVM to achieve high power factor values with relatively low switching frequency. Simultaneous dual switch control is applied on the two stages of the 137

153 CBB converter. The proposed control is proved to enhance the inherent high power factor features of the used converter by the means of extending the DCVM duration while using only one feedback control loop. The applied control allows for a continuous sinusoidal input current on an overlapping input/output voltage range. Additionally, the converter possesses a zero turn-off switching voltage and a zero turn-on diode voltage. The converter modes of operation are analyzed and the design equations are derived, proving the contribution of the dual stage control technique. An averaging circuit model is used to develop the system low-frequency model and the small signal transfer function. Simulations and experimental analyses are conducted. Both the steady state and the transient results proved the system dynamic ability and effectiveness over a wide range of power flow and varying conditions. 138

154 CHAPTER VI PV STRING POWER PROCESSING ARCHITECTURE 6.1. Introduction In Chapter 2, a review on the PV power processing architecture is presented to conclude the following points: 1. PV elements are desired to operate at their maximum available power in order to increase their energy contribution in the proposed PV/battery grid tied system. 2. There are two different families of PV converters; the centralized converters and the DICs. 3. The centralized converters suffer from low efficiency that is the resultant of their lack of local MPP tracking. 4. Various approaches of DICs are surveyed concluding that the DPP architectures are more efficient as less power is processed in the PV converters. 5. Different DPP architectures are previously proposed in the literature and reviewed in Chapter II to demonstrate the need for a developed architecture that processes low current with low voltage stress on its components. 139

155 Thus, a novel DPP architecture for a series PV string is proposed in this chapter. The proposed architecture is applicable to the PV/battery grid tied system presented in this Dissertation for EVs charging. The architecture enables each PV element to operate at its local maximum power point (MPP) while processing only a small fraction of its total generated power through the distributed integrated converters (DICs). The current processed through each converter is the difference between the local PV element MPP current, and the local PV string current. This leads to a higher energy capture at an increased conversion efficiency while overcoming the difficulties associated with unmatched MPPs that results from partial shading, temperature gradients, manufacturing defects, cells aging, and etc. Additionally, for higher reliability, the proposed configuration reduces the need for electrolytic capacitors. A state space model of the proposed system is driven and a comparison analysis is carried out with respect to the conventional DPP architectures. A hardware prototype is designed and built for 3 PV panels connected in series to validate the effectiveness of the proposed architecture DPP Concept A. The feasibility of the distributed MPPT The DPP topologies stem from the concept of DICs. However, DPP topologies differ in two main factors. They tend to have higher efficiency ratings due to their capability of partial power processing which reduces the system losses. Additionally, the used converters are of lower cost due to their reduced sizing requirements. 140

156 PV 1 PV 2 PV 3 PV 4 PV 5 I pv1 = 5 A I pv2 = 3 A I pv3 = 4.5 A I pv4 = 4 A I pv5 = 3 A Figure 6.1. Partial shading example across a PV module composed of 5 PV elements. Figure 6.2. The I-V characteristics of the 5 PV elements under partial shading conditions. 300 P Total = w Power (W) 200 PV 2 & PV 5 are bypassed PV 4 is bypassed 100 PV 3 is bypassed Current (A) 4 5 Figure 6.3. The P-V Characteristics of the 5 PV elements system under partial shading conditions using a centralized MPP tracker. 141

157 In order to illustrate the effectiveness of the DPP topology, the feasibility of DICs needs to be demonstrated first. Thus a partial shading case study example is shown in Fig In this example 5, PV modules are connected in series to form a PV string. Each PV module considered having different I-V characteristics as shown in Fig. 6.2 to consider the effect of partial shading. The P-I characteristics of the integrated system are shown in Fig. 6.3 where each PV module is equipped with a bypassing diode as presented in Fig. 2.7.a. Although the total available power from the panels is w, the maximum power that can be extracted from the string connection is w. Moreover, local MPPs will be created in the system that will occur due to the operation of the bypass diodes as illustrated in Fig. 2.7.a. For example, if the string current exceeds the short circuit level of PV 2 and PV 5 short circuit currents, then these modules will be shorted leading to a significant drop in the system output power. The same phenomena is repeated at the short circuit current values of PV 4, and PV 3 respectively. The creation of local MPPs adds to the complexity of the MPP tracking topology that needs to be applied in the studied system in order to track the global MPP. The results shows that the use of DICs would lead to a minimum of 30% increment in the captured power. B. Existing DPP Topologies The presented configurations differ from each other in terms of the DIC ratings, and the total amount of processed current. The PV to main bus (PVMB) configuration is shown in Fig. 6.4.a [48, 160]. The total summation of the maximum power of the individual PV elements can be captured in this topology. Additionally, an independent local control 142

158 can be applicable if the central converter is fast enough to track the MPP of one of the PV elements while using N 1 DICs for N PV elements. Another control technique can be applied by using N DICs and utilize the central converter in optimizing the power flow through the associated DICs [161]. The main disadvantage of this configuration is that all the DICs have to be either sized to the DC bus voltage, or an isolation transformer has to be inserted. This increases the weight and the cost of the system. A solution for the PVMB limitation is proposed in [51, 162] where the PV elements provide the differential power to an auxiliary DC bus through an electrolytic capacitor. The insertion of this capacitor decreases the system reliability. Additionally, the use of isolated DICs is necessary and a coordinated control needs to be applied. A similar approach is shown in [148] where the differential power is fed into an inductor instead of a capacitor, but the needed centralized control and the inductor size requirements at high shading factors are still challenges that need to be rectified with this configuration. L 4 M 4b PV 4 C i4 M 3b PV 4 C i4 M 4a L 3 L 3 PV 3 PV 2 C i3 L 2 C i2 M 3a M 2a M 3b M 2b I main Central Converter M 2b M 2a C i3 L 2 PV 2 PV 3 C i2 M 3a M 1b I t Central Converter L 1 L 1 M 1b PV 1 C i1 M 1a C i1 PV 1 M 1a a) PVMB (Non-isolated). b) PV to PV (ladder configuration). Figure 6.4. DPP MPP tracker configurations. 143

159 Another widely used topology is the ladder topology as shown in Fig. 6.4.b [53, 163]. The main concept of this topology is to shuffle the power between the neighboring PV elements in order to track the individual MPPs. In this topology, the central converter has to be fast enough to track the MPP of one of the PV elements. MPP will be tracked using the central converter. In [50], a reconfiguration of the system is proposed by redefining the control objectives to be the voltage difference between the neighboring PV elements. This approach eliminates the need for the central converter to control one of the elements but it requires communication between the neighboring elements. Another extension of this topology is found in [164] using a switched capacitor converter instead of the switched inductor shown in Fig However, this leads to high current spikes that are associated with the hard switching of the capacitor converter. In order to mitigate some of these effects, a resonant ladder converter is proposed in [54], where the intermediate capacitor is replaced with an impedance Z x, and the circuit is switched at the resonant frequency. In general, the main drawback of the configurations proposed in [50] is that they are mostly effective with fixed duty ration in order to equalize the voltage between the neighboring PV elements. Although, this simplifies the control scheme, the MPP power of the PV elements varies significantly in a small voltages range Proposed DPP Topology The proposed PV to series string (PVSS) configuration, shown in Fig. 6.5, is based on a distributed DICs performing individual MPP for each connected PV element. The PVSS converters track the MPP by processing the difference between the local PV element MPP and the local series string current. The differentially processed power is fed back to the system through the same series string using an averaging technique. This way the series 144

160 string current at any point on the string is the resultant of the average MPP current of the lower PV elements. However, the DICs voltage ratings vary according to the placement of the associated PV module in the circuit structure as shown in Fig PV 1 I pv1 PV 2 I pv2 PV 3 I pv3 PV 4 I pv4 I ss0 I ss1 I ss2 I ss3 I ss4 DC/DC Converter 2 DC/DC Converter 3 DC/DC Converter 4 Central Converter I t Figure 6.5. The configuration of the proposed series string DPP topology. A. The Theory of Operation The operation modes of the proposed DPP topology for the unshaded and shaded (under-performing) PV elements are shown in Fig. 6.6, where PV sh is a shaded PV element and PV ush is an unshaded PV element. The mosfet M ia is used to charge the DC/DC converter inductor using the associated PV element voltage (V PVi ), while the anti-parallel diode equipped with the mosfet M 1b is used to discharge the inductor through the voltage of the preceding PV element voltages declared as i 1 j=1 V PVj. A similar explanation is true for the shaded PV elements where the inductor is charged using j=1 V PVj and discharged through V PVi. It is clear that the series string current will be directly proportional to the power delivered from the preceding PV elements over their corresponding voltages as i 1 145

161 shown in (6.1). While by analyzing the node 1 in Fig. 6.6, and considering a zero current over a switching cycle in the capacitor C i, following Eqns. can be written: j=1(v pv I pv ) j For i = 1: N s ; I ss i = i i j=1 V pvj (6.1) For i = 2: N s ; I L i = I pvi I ss i 1 (6.2) as I ss is the mean local series string current, V pv is the PV voltage, I pv is the PV current and I L is the average inductor current and i is the corresponding PV location. I pv i I ssi On-State for PV ush & Off-State for PV sh PV i 1 C i L i i 1 V PVj I L2 I ai M ia On-State for PV sh & Off-State for PV ush M ib Central Converter I t I ssi 1 j =1 I bi Figure 6.6. Theory of operation of the PV elements proposed DICs. B. Current Sensor-less Control The current sensors represent a high volume in the total pricing of the interfacing power electronic system. Thus, it is desirable to use the sensor-less current control in the designed DICs. This is achievable when the converters operate at discontinuous current mode as shown in Fig The voltage applied on the DIC inductors is shown in Fig

162 In order to track the various MPPs, the PV element currents should be accurately estimated. This is done by relating them to the duty ratio commands which are updated accordingly, as well as the applicable voltages. In this subsection, the relation of the duty ratio to the PV current is generally driven for the proposed topology. I Lpi T T Current(A) V PVi Voltage(V) i 1 D i t(s) D ci D fi Figure 6.7. The inductor current waveform of the DICs in DCM. j =1 V PVj D i t(s) D ci D fi Figure 6.8. The inductor voltage waveform of the DICs in DCM. The unshaded PV elements are evaluated for sensor-less current control algorithm. The analysis is applicable for the shaded PV elements. According to Fig. 6.7 and 6.8, the inductor current change can be represented as follows. I Li = I Lpi = V PV i D i f s L i (6.3) where I LPi is the peak inductor current of the corresponding PV elements, V PVi is the voltage of the corresponding PV element, D i is the converter duty ratio, and f s is the switching frequency. Knowing that the average inductor voltage over a switching cycle is zero, implies (6.4). The average inductor current can be driven as shown in (6.5). 147

163 D ci = V PV i D i i 1 j=1 V pvj (6.4) i j=1 Thus, by combining (6.3) and (6.5), we can have. I L i = I Lp i D i 2 ( V pv j ) (6.5) i 1 j=1 V pvj i j=1 I L i = V 2 PV i D i 2f s L ( V pv j ) (6.6) i 1 j=1 V pvj From (6.2) and (6.6), it can be concluded that D i = 2f sl [I PVi i 1 j=1 V pvj i 1(I PV V PV ) j V PVi i j=1 V pvj j=1 ] (6.7) I PVi = [ D i 2 i V PVi j=1 V PVj 2f s L i 1 j=1 V PVj i 1 + j=1 P PVj ] (6.8) Using (6.8), the PV element current is estimated using the commanded duty ratio, the voltage of the PV element and the knowledge of the PV power in the preceding PV elements. Using the same analysis, (6.8) is applicable for the shaded PV elements operation just by replacing D i with D ci. Thus, the MPP can be tracked in a distributed manner without the need for any current sensors except for the main bus current sensor. This current is referred to as I t as shown in Fig Although a distributed control is applied but a cost effective communication link between the PV elements is needed. The need for this link is limited to only sensor-less control algorithm. 148

164 C. The reduction of the power decoupling capacitor size The PV is desired to operate at the MPP at all times, however, as the state of the applied circuit changes, the output power of the PV changes accordingly. This requires energy storage elements to be equipped with the PV element in order to maintain the variation in the PV output power within reasonable limits. Electrolytic capacitors are used as the power decoupling element. However, the short lifetime of electrolytic capacitors impacts the overall reliability of the PV power electronic interfacing system [165]. Thus, it is desired to replace those electrolytic capacitors with ceramic capacitors that would have a longer lifetime as well as a better performance at a lower price. The main downside of the ceramic capacitors is that they are available only at relatively low capacitance values. The proposed circuit is evaluated for the purpose of validating the possibility of capacitance reduction in the proposed DICs. The system is analyzed under CCM and then the analysis is extended for the DCM to allow sensor-less current control. The waveforms of the DIC inductor and input capacitor currents are shown in Figs. 6.9 and 6.10 respectively for the CCM operation. The change in the PV voltage is directly related to the change in the charge of the connected capacitor as: V PVi = Q C i = I L i 8 f s C i (6.9) C i = D i 8 L f 2 s ( V PVi V PVi ) (6.10) 149

165 Current(A) T T IL Current(A) T 2 t(s) I L t(s) D i 1 D i Figure 6.9. The inductor current waveform of the DICs in the CCM. D i 1 D i Figure The input capacitor current waveform of the DICs in the CCM. The reduction in the capacitance size is realized due to the fact that as opposed to the DMPPT topologies shown in Fig. 2.7, the capacitor is not the only path for the PV current during any of the operation modes. In order to investigate the impact of using the current senseless control on the capacitor size, the proposed system is analyzed under DCM. The capacitor current during this mode of operation is shown in Fig During the time interval 0 t(s) (D i + D ci )T, the capacitor current is combined with the inductor current to balance the KCL in node 1 as shown in Fig. 6.6, while during the interval (D i + D ci )T t(s) D fi T, the capacitor is the only path for the differential current. Thus, (6.12) is concluded, while (6.13) is driven from Fig

166 I ai T Current(A) X IL i -I bi D i t(s) D ci D fi Figure The capacitor current waveform of the DICs in the DCM. D fi = 1 D i D ci (6.11) I ai = I pvi I ssi 1 (6.12) I bi = I Li I ai (6.13) From Fig and using the charge balancing equation of the capacitor, can be written as: I ai D fi I a i (1 D fi X) = 1 2 I b i X (6.14) where X can be determined as i j=1 V pv j i 1 j=1 V pvj (I PVi I ssi 1 ) [2 D i ( )] f s L i (6.15) X = V PVi D i The input capacitor is sized based on the change of the capacitor charge as: 151

167 V PVi = Q C i = XT 2C i I bi (6.16) X C i = 2f s ( V PVi V PVi ) ( D i I PV i + I ss i 1 ) (6.17) f s L i V PVi V PVi The input capacitor sizing design Eqns. for the proposed system are shown in (6.10) and (6.17) for the CCM and the DCM operations respectively. It is concluded that the ceramic capacitors will be appropriate for these applications as the required capacitance is found to be less than 20 μf for a switching frequency more than 30 khz System Modeling and Comparison Analysis In order to understand the impact of the control variables on the output signals, a state space model is shown in this Section, followed by a comparison of the amount of processed current in the DICs of the proposed topology and a conventional one. A. State Space Model Consider the configuration shown in Fig. 6.5 which is composed of three DICs used for four PV elements, while the central converter is used to track the MPP of the first PV element. The central converter is assumed to be a boost converter in this model. The output of the central converter is a resistance (R o ) connected in parallel with a capacitor (C o ) The input variables will be the three duty ratios of the DICs and I t, which is the total current passing through the main DC bus and controlled by the central converter/inverter. i ε N, i > 1: dv Ci N dt = 1 (I C PVi D i I Li I t + D j I Lj ) (6.18) i j=i+1 152

168 di Li dt = 1 L i (D i V ci + D i i 1 j=1 V Cj ) (6.19) For i = 1: dv Ci N dt = 1 (I C PVi I t + D j I Lj ) (6.20) i j=i+1 For the central converter: N di t dt = 1 ( V L cj + D c V o ) (6.21) c j=1 dv O dt = 1 C 0 (D c I t V o R o ) (6.22) In order to develop the state-space model of the system, the state vector (x), the input vector (u), the output vector (y), and the Matrices (A, B, C, and D) need to be developed as shown in ( ). The PV elements are linearized and modeled as resistors (R 1, R 2, R 3 and R 4 ) for simplification, while the central converter is modeled as a variable currents source (I t ) that varies to track the MPP of PV 1 as shown in Fig I t is chosen as an input in this system in order to generalize the model for various kinds of centralized converters. Clearly, I t is controllable through the centralized converter. x = Ax + Bu (6.23) y = Cx + Du (6.24) x T = [v c1 v c2 v c3 v c4 i L2 i L3 i L4 i t v o ] (6.25) u T = [d c d 2 d 3 d 4 ] (6.26) y T = [i PV1 i PV2 i PV3 i PV4 ] (6.27) As can be seen in (6.24), the model is composed of 2N 1 state variables that represent N capacitors and N 1 inductors for N PV elements, N 1 DICs, and one central converter. As shown in ( ), all the states are controllable using the chosen 153

169 control variables. The existence of non-zero values for the elements (1,1), (2,2), (3,3) and (4,4) in matrix B enables for control without any communication. However, communication signals are still needed if the converters operate in DCM to achieve sensorless current control. The presence of more than one control variable which is capable of controlling every output signal is observed in the model. This feature enhances the system overall reliability during fault conditions. The inductor currents can be directly controlled using their associate DIC duty ratios as shown in rows (5-7) in (6.27). A = [ 1 R 1 C R 2 C D 2 D 2 1 R 1 C C 1 C 1 C 1 C 1 D 3 D D 2 D 3 D 4 1 C 2 C 2 C 2 C R 1 C D 3 C 3 D 4 C 3 1 C 3 0 D 4 1 C 4 C 4 0 D L 2 L 2 D 3 D 3 D L 3 L 3 L 3 D 4 L 4 L 4 L 4 L 4 D 4 D 4 D C 1 C 1 C 1 C D D c C O V o R o ] (6.28) 154

170 0 I L 2 C 1 I L 3 C 1 I L 4 C 1 0 I L 2 C 2 I L 3 C 2 I L 4 C I L 3 C 3 I L 4 C 3 B = I L 4 C 4 0 V c 2 (V c1 ) L V c 3 (V c1 + V c2 ) L V c 4 (V c1 + V c2 + V c3 ) L 4 V O L c I t [ C o ] (6.29) C = 1 R R R [ 1 R ] (6.30) D = 0 (6.31) B. Current Processing Comparative Analysis A comparison between the processed current of the ladder topology (Fig. 6.4.b) and the proposed averaging topology (Fig. 6.5) is shown to illustrate the lower current rating requirements of the DICs in the proposed topology. For the purpose of performing the comparison analysis, five PV panels are connected in series are used in this case study. Every one of the PV panels operates at 10 A and 20 V during unshaded conditions. Two different shading scenarios are used for comparison. The first scenario assumes a 155

171 concentrated shade on one of the elements as shown in Fig The results of this scenario are shown in Fig While the second scenario assumes a tapering shading across three neighboring PV elements in the series string as shown in Fig. 6.14, and the associated results are provided in Fig The figures represent the total current processed in all the DICs for both of the topologies at different shading factors (SF) and various shading locations. The SF varies between 0 and 1, where 1 represents a completely shaded PV element. Thus the SF and the total current processed in the DICs are directly proportional. The shading location represents which of the PV elements is shaded in the first scenario and which of them is the most shaded in the second one. The slight changes in the PV voltages as an impact of the different shading conditions are ignored in this analysis in order to simplify the calculations. PV 1 PV 2 PV 3 PV 4 PV 5 Figure Potential concentrated shading scenario for the comparative study. 156

172 Ladder Topology Averaging Topology Figure Comparison study results for the concentrated shading scenario. PV 1 PV 2 PV 3 PV 4 PV 5 Figure Potential tapering shading scenario for the comparative study. 157

173 Ladder Topology Averaging Topology Figure Comparison study results for the tapering shading scenario. It is clear from the provided results, that the proposed averaging topology yields lower current than the conventional ladder topology in both of the scenarios. For the concentrated shade, it is observed that the ladder topology imposes the highest current on the DICs when the shading location is near the lower or the upper PV element, while the averaging topology imposes a relatively higher current when the shaded element is in the middle of the string. While for the tapering shade, the ladder topology imposes the highest current at location 1 and the averaging topology imposes the least current at location 3. It is also clear from the figures that the DICs current increases proportionally to the SF in both of the topologies Experimental Results A laboratory prototype of three DC/DC converters is used to control three PV elements and to track their associated MPPs as shown in Fig The DC/DC converters are locally controlled using DSPs. The experiment is implemented on both the conventional 158

174 ladder and the proposed averaging topologies. The DC/DC converters are named DIC 1,2&3 in the ladder topology and DIC 2,3&C respectively in the averaging topology, where DIC 3 and DIC c are the central converters in the two topologies respectively. DC/DC 3 DC/DC 2 DC/DC 1 Figure PCB circuit Implementation. The first test is implemented on the setup using the ladder topology where all the MPPs of the three PV elements are 7.7 A, 7.2 A, and 4 A respectively as shown in Fig The inductor currents in the DC/DC converters are measured as they represent the average current processed in every DIC. I t is the total current passing through the DC bus after tracking the individual MPPs. The duty ratios of converters 1 and 2 are almost identical due to the fact that the voltages of the PV elements are slightly varying under shading conditions. The setup is then configured to apply the proposed averaging topology under various conditions. The first case study was applied for the three PV elements where their MPP currents are at 5 A, 7 A, and 7 A sequentially. It is shown in Fig a and 6.18.b that the MPP is being successfully tracked for the 3 PV elements, additionally the total 159

175 current (I t ) is available at the DC bus after treatment of the differential current. It is clear from Fig c that the current passing through DIC 2 is the difference between I PV2 and I PV1, while the current passing though DIC 3 is the difference between I PV3 and I ss2 where (4) applies on I ss2. This is the main feature that leads to lower processed current compared to the conventional topologies. The duty ratios of the three converters are shown in Fig d. The topology is then tested under different mismatching conditions where the MPP currents of the 3 PV elements are at 7, 5, and 5 A. This kind of current mismatch will force both of DIC 2,3 to operate in the opposite direction to the previous case study. The MPP current is tracked for the PV sources in Figs a and 6.19.b, and it is clear that the total DC bus current is lower in this case than the previous one due to the generation of less current from the PVs at relatively close voltages. The same argument about the inductor currents shown in Fig c can be made here similar to the previous case study. The negative values of the duty ratios in Fig d represents the flow of the current in the opposite direction of the previous shading conditions. The last set of results are obtained for the dynamic performance of the proposed averaging system topology under varying shading conditions and thus, different insolation levels that yield to various MPP currents for the three PV panels. The applied sequence is composed of four phases and is shown in (30) as I PV1 I PV2 I PV3. 160

176 I PV1 I t I PV2 I PV3 a) PV 1 and PV 2 currents. b) PV 3 and DC bus currents. I L2 I L1 c) DIC 1 and DIC 2 inductor currents. d) Duty ratios of the three DICs. Figure Experimental Results for the ladder topology. I PV2 I PV3 I t I PV1 a) PV 1 and PV 2 tracked MPP currents. b) PV 3 MPP current and DC bus current. Figure Results for the proposed topology under the first scenario 161

177 I L2 I L3 c) DIC 2 and DIC 3 inductor currents. d) Duty ratios of the three DICs. Figure Results for the proposed topology under the first scenario.(cont'd.) (6.31) I PV1 I t I PV3 I PV2 a) PV 1 and PV 2 tracked MPP currents. b) PV 3 MPP current and DC bus current. I L2 I L3 c) DIC 2 and DIC 3 inductor currents. d) Duty ratios of the three DICs. Figure Results for the proposed topology under the second scenario. 162

178 The current in the second and third PV panels along with their associated average DIC currents are shown in Fig a-6.20.d, respectively. The results in this Fig. demonstrates the averaging concept and the low current stress of the proposed topology under rapidly varying shading conditions. Fig shows the first PV panel, the DC bus, the load currents (I PV1, I t, and I Load respectively), as well as the variations in the DICs duty cycles during the sequence and the system voltage at the DC bus and at the load side. Phase 1 Phase 2 Phase 3 Phase 4 Phase 1 Phase 2 Phase 3 Phase 4 a) PV 2 tracked MPP current. b) DIC 2 inductor current. Phase 1 Phase 2 Phase 3 Phase 4 Phase 1 Phase 2 Phase 3 Phase 4 c) PV 3 tracked MPP current. d) DIC 3 inductor current. Figure Results for PV 2,3 and DIC 2,3 under the dynamic performance test. 163

179 I Load Phase 1 Phase 2 Phase 3 Phase 4 Phase 1 Phase 2 I t Phase 4 Phase 3 a) PV 1 MPP tracked current. b) DC bus and load currents. V series string Phase 1 Phase 3 Phase 2 Phase 4 Phase 1 Phase 2 Phase 3 Phase 4 V Load c) Duty ratios of the 3 DICs. d) The DC bus (series string) and the load voltages. Figure Results for PV 1 DC bus, load and the duty ratios under the dynamic performance test. The presented results demonstrate the effectiveness of the applied configuration and its control under dynamic conditions as it is shown that the MPP currents are tracked and low inductor currents are maintained at all times. It is also observed that the duty ratios are changed dynamically and that the output current is filtered using the central DC/DC converter. 164

180 6.6. Conclusion DPP topologies proved to be offering several advantages for a series string PV system over the classical PV configurations. This is due to the fact that only a small fraction of the PV power is processed in the DICs which enables for a higher system efficiency and a lower sized active and magnetic components. An overview of the existing DPP topologies is summarized and their downsides are explained. Consequently, a novel DPP topology is proposed in this dissertation to mitigate the limitations of the aforementioned topologies. The proposed topology uses an averaging concept and imposes less current on the associated DICs compared to the conventional ones while decreasing the voltage stress on the converter components in comparison to the PVDC topology. The topology suits a current sensorless technique, and the necessary equations are driven. Additionally, the proposed topology is proven to reduce the capacitance of the power decoupling capacitor associated with every PV element. The proposed system is verily a MIMO system and is modeled to link the control variables to the output signals. Finally, the averaging topology is tested under different shading and mismatching conditions, proving its effectiveness and its dynamic ability under varying insolation levels. 165

181 CHAPTER VII SUMMARY 7.1. Conclusion The use of on-site solar energy sources associated with battery storage has shown to be an effective and an economically viable method to achieve high charging rates for electric vehicles (EVs). The development of an efficient and reliable system requires the adoption of a cost-effective power flow management algorithm along with innovative hardware configurations and control structures. Consequently, an optimal power flow technique of a photovoltaic (PV)/battery powered fast EV charging station is presented to continuously minimize the operation cost. The novelty of the proposed power flow technique comes from the inclusion of the battery degradation cost into the optimization problem, the utilization of two levels of optimization to manage the power flow, and the ability to compensate for the system forecasting errors. Accordingly, a battery degradation cost model is presented which accounts for the operating temperature, average state of charge (SOC), and the cycle depth of discharge. Particle swarm optimization is used as an offline predictive optimization tool to set the battery SOC limits according to the forecasts of the PV available power, the load power, and the dynamic grid prices. An online dynamic programming (DP) approach is utilized to 166

182 manage the system power flow on a lower level for short time intervals. The inclusion of the DP into the system helps in improving the computation time and efficiency. Additionally, the DP is used for error compensation at times when the forecasted data differs from the measured data. Simulation and experimental results were presented to prove the system effectiveness under dynamic operating conditions. Based on the power flow management results, a fast charger DC/DC converter is developed in Chapter IV to charge the EV at 80 kw charging rates using the proposed PV/battery grid tied system. A comparison between various high power bi-directional converters is presented and the interleaved cascaded buck boost (CBB) converter is selected for development. The interleaving feature proved its effectiveness in reducing the current stress on the passive and active components while decreasing the voltage and current ripples at the output. The Li-ion battery electrical and thermal models are presented and the battery thermal stress is analyzed. It is concluded that the use of the available advanced thermal management systems such as phase change material is recommended in the presented system due to the high temperature stress associated with the high proposed charging rates. The experimental setup is developed for an 80 kw CBB converter and experimental tests are carried out under different charging scenarios. The test results validated the effectiveness of the fast charger converter for EV charging infrastructure. The operation of an efficient and a reliable PV/battery grid-tied system requires the adoption of hardware configurations and control structures that improve the quality of the power system. The power quality of the proposed system in this dissertation focuses on enhancing the grid mains power supply by reducing its associated harmonics, and 167

183 extracting the maximum power from the PV sources while improving the system efficiency. Thus, two power quality improvement techniques are developed in Chapters V, and VI focusing on the electrical grid mains current and the PV source energy production. A novel power factor correction (PFC) topology is proposed in Chapter V to reduce the grid harmonics and improve its power factor using the hardware configuration introduced in Chapter IV. The designed CBB converter is controlled to correct the power factor of the system in order to maximize the amount of power that can be supplied from the grid at a minimal current stress on the interfacing system components. The CBB converter operates in discontinuous capacitor voltage mode (DCVM), while a simultaneous dual switch control is applied on the two stages of the CBB converter. The proposed control is proved to enhance the inherent high PFC features of the converter by extending the DCVM duration while using only one feedback control loop. The applied control allows for a continuous sinusoidal input current on an overlapping input/output voltage range. Additionally, the converter possesses a zero turn-off switching voltage and a zero turn-on diode voltage. The converter modes of operation are analyzed and the design equations are derived, proving the contribution of the dual stage control technique. An averaging circuit model is used to develop the low-frequency model and the small signal transfer function of the system. Simulations and experimental analysis are conducted. Both, the steady state and the transient results proved the effectiveness of the system over a wide range of power flow and under varying operational conditions. 168

184 Battery Storage Ci3 Ci4 M 1 b M 1 a M 3 a L 1 C i 1 C i 2 PV 1 PV 2 PV 3 M 3 b PV 4 L2 L3 C o 1 C o2 C o3 M 2 b M 2 a Grid LC-Filter Uncontrolled Rectifier PWM Inverter Interleaving Cascaded Buck Boost Converter Interleaving Boost Converter Series PV String with DPP Architecture Electric Vehicle Figure 7.1. Overall system architecture. 169