Status of GaN device qualification standards effort by new JEDEC committee JC-70.1

Transcription

1 Status of GaN device qualification standards effort by new JEDEC committee JC-70.1 Tim McDonald Senior Consulting Advisor CoolGaN TM Technology Development Infineon Technologies JEDEC JC-70.1 Chair, JC-70 Vice Chair Kurt Smith VP Reliability VisIC JEDEC JC-70.1 Vice Chair Stephanie Watts Butler, PhD, PE HV Technology Innovation Architect Texas Instruments JEDEC JC-70 Chair SEMICON-EUROPA- Munich November 15, 2018

2 3 Agenda Brief history of (US) GaN Standards Activities in Power Electronics JEDEC Approach to qualifying silicon and GaN devices Formation and Structure of new JEDEC subcommittee JC-70.1 focused on GaN devices Work focus and progress for GaN Standards (JC-70.1) JC-70 Scope and Structure, JC-70.1 (GaN), JC70.2 (SiC) Concluding comments and invitation

3 History of ~independent GaN activities before creation of GaNSPEC DWG 4 March 2014, UCSB Institute for Energy Efficiency Technology Roundtable: Stds for GaN Power Electronics (Mishra, NIST) APEC 2015, IEEE PELS Standards Group meets with SiC Focus IEDM 2015, IEEE EDS Holds Discussion: Guidelines and Standards for Reliability Testing in Power Electronics Dec. 2015, IEEE PELS Launches Proposal for International Technology Roadmap for Wide Bandgap WiPDA at VT Nov 2015, Tim McDonald Presents on GaN Reliability Generates Several Volunteers for GaN Standards activity to Tim McDonald & Stephanie Watts Butler APEC 2016: Assess Interest & Launch GaNSPEC DWG (JEDEC a member) JEDEC Board of Directors Investigates Future Needs of Industry Ultimately Issuing Survey Right after APEC 2016

4 JC-70 created October 2017: Scope Products discrete devices and integrated circuits wide bandgap and ultra wide bandgap semiconductors power conversion circuits regardless of device type, polarity, mode of operation, packaging, electrical ratings, and end applications. RF/microwave amplification and signal conditioning applications are generally not covered Industry standards concerned with reliability verification and qualification procedures, test methods and measurement techniques, data sheet elements and device specifications, unique packaging considerations cataloging and consideration of mission profiles, and formulation of terms, definitions, and symbols

5 6 What comes to mind when you hear JEDEC Qualification : a typical qualification table REQUIRED RELIABILITY TESTS Parameter Part Type Test Conditions Duration Quantity Part no X TC -55 C/150 C 1000 cy 0/168/500/ x 77 H 3 TRB 85 C/85%RH/100V 1000 hrs 0/168/500/ x 77 HTRB 150 C/960V 1000 hrs 0/168/500/ x 77 HTGB 150 C/20V 1000 hrs 0/168/500/ x 77 IOL delta Tj = 100 C 5,000 cy 0/2500/ x 77 AC 121 C/15psig 96 hrs 0/96 3 x 77 From : State of Demonstrated HV GaN Reliability and Further Requirements, T. McDonald, APEC 2015 Industry session JEDEC offers test methods to support these and other tests. Partial list: JESD22 A104, Temperature Cycling JESD22-A101, Steady-State Temperature Humidity Bias Life Test JESD22 A-108, High Temperature Reverse Bias (HTRB and HTGB) JESD-A102, Accelerated Moisture Resistance-Unbiased Autoclave. But there is much more..

6 JEDEC Approach to Qualification: JESD94B Application Specific Qualification Using Knowledge Based Test 7

7 JC-70.1 approach in JESD94B terminology 8 INPUTS PROCESSING {Methodology} MISSION PROFILE JEDEC GUIDELINES OUTPUTS: REL PROCEDURE TEST METHODS DATASHEET PARAMETRICS

8 10 JEDEC Committee JC-70.1 structure JC-70.1 Subcommittee GaN Power Electronic Conversion Semiconductor Standards Task Group TG701_1 GaN Power Electronic Conversion Semiconductor Reliability and Qualification Procedures Task Group TG701_2 GaN Power Electronic Conversion Semiconductor Datasheet Elements and Parameters Task Group TG701_3 GaN Power Electronic Conversion Semiconductor Test and Characterization Methods

9 Example failure mechanism: Charge Trapping How to measure it? I D (A) 11 Observe Charge Trapping by measuring Dynamic R DS (ON) : Post application of DC bias Stress, R DS (ON) shifts (increases) and peak output current reduces. This phenomenon is attributed to surface states and trapping in the device The result could be unstable increase in conduction losses that might result in failure. Output o C Slope shifts (R DS (on) increases) V DS (V) Current reduces ( collapses ) Pre 10V Stress Post 4.5V Stress

10 Normal conduction through 2DEG Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, Oct Initial RDS(ON) reading taken from steady state with full populated two dimensional electron gas (2DEG) 12

11 After bias removed: fewer electrons Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, Oct After bias, traps temporarily attract electrons which reduces concentration of 2DEG and increases measured R DS (ON) 13

12 After time: electrons repopulate 2DEG Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, Oct Steady state can be recovered with time 14

13 Dynamic R DS (ON): interaction between the 3 focus teams REL Charge Trapping Transient reduction of 2DEG electron concentration due to trapping effects Test Dynamic R DS (ON) What voltage applied? Delay time between applied V DS and measurement? How to measure? Datasheet How to account for transient behavior of R DS (ON)? Standard static value is insufficient 15

14 Progress Getting competitors to work together is a challenge; we had to climb the ladder to overcome obstacles Members already had fulltime GaN jobs Progress sometimes slows or even slides back Overall cooperation and results have been remarkable! 16

15 Proposed Items for Guidelines/Standards 17 REL List of Failure Mechanisms & Resulting Failure Mode Focusing on Charge Trapping, Charge Injection, Hot Electron, Corrosion, TDDB Like Mechanism, Delam Corresponding Acceleration & Stress Procedure Test Dynamic R DS (ON) Thermal Resistance (only for cascodes) Safe Operating Area (SOA) Datasheet Include effect of Dynamic R DS (ON) Nomenclature of parameters to adjust for uniqueness of GaN power transistors Transistor circuit symbol to reflect distinctive operation GaN HEMTs

16 18 Global Standards for the Microelectronics Industry JEDEC has developed standards with industry-wide, international acceptance since JEDEC s member companies are worldwide and represent a large proportion of the microelectronics industry. JEDEC partners with other standards groups such as IEC, ANSI, ESDA, China Electronics Standardization Institute (CESI), JEITA JEDEC formed its first task groups in China in 2016 Over 1,000 JEDEC standards and publications serving all segments of the microelectronics industry

17 19 JEDEC Committee JC-70.1 structure: GaN JC-70.1 Subcommittee GaN Power Electronic Conversion Semiconductor Standards Task Group TG701_1 GaN Power Electronic Conversion Semiconductor Reliability and Qualification Procedures Task Group TG701_2 GaN Power Electronic Conversion Semiconductor Datasheet Elements and Parameters Task Group TG701_3 GaN Power Electronic Conversion Semiconductor Test and Characterization Methods

18 20 JEDEC Committee JC-70.2 structure: SiC JC-70.2 Subcommittee SiC Power Electronic Conversion Semiconductor Standards Task Group TG702_1 SiC Power Electronic Conversion Semiconductor Reliability and Qualification Procedures Task Group TG702_2 SiC Power Electronic Conversion Semiconductor Datasheet Elements and Parameters Task Group TG702_3 SiC Power Electronic Conversion Semiconductor Test and Characterization Methods

19 JC-70 Structure: Wide Bandgap (GaN & SiC) JC-70 Wide Bandgap Power Electronic Conversion Semiconductors JC-70.1 Subcommittee GaN Power Electronic Conversion Semiconductor Standards JC-70.2 Subcommittee SiC Power Electronic Conversion Semiconductor Standards

20 JC-70 Structure: Interactions with Others Cooperates through JEDEC with other International Stds Bodies JC-70 Wide Bandgap Power Electronic Conversion Semiconductors Communicate and collaborate with JC-14 and JC-13 and other JEDEC committees JC-70.1 Subcommittee GaN Power Electronic Conversion Semiconductor Standards JC-70.2 Subcommittee SiC Power Electronic Conversion Semiconductor Standards

21 JC-70 Structure: Leadership JC-70 Wide Bandgap Power Electronic Conversion Semiconductors Chair: Dr. Stephanie Watts Butler (Texas Instruments) Vice-Chair Mr. Tim McDonald (Infineon) JC-70.1 Subcommittee GaN Power Electronic Conversion Semiconductor Standards Chair: Mr. Tim McDonald (Infineon) Vice-Chair Dr. Kurt Smith (VisIC) JC-70.2 Subcommittee SiC Power Electronic Conversion Semiconductor Standards Chair: Dr. Jeffrey Casady (Wolfspeed, a Cree Company) Vice-Chair Dr. Peter Friedrichs (Infineon)

22 JC-70 Member List ABB Alpha and Omega Semiconductors, Inc Accel RF Instruments Corporation Analog Devices Inc. Efficient Power Conversion Corp ExaGan Freebird Semiconductor Corporation GaN Systems General Electric Hewlett Packard Enterprise Co Hirex Engineering Huawer Technologies Co. LTD Infineon Innoscience Technology Co., Ltd. Innotron Memory Co., Ltd. Intel Keysight Technologies Inc Lenovo M/A-COM Technology Solutions Mentor, a Siemens Company Micron Technology Inc Microsemi Corporation Monolith Semiconductor Inc 50...and still growing! Navitas Semiconductor NSWC Crane NXP Semiconductors ON Semiconductor Panasonic Corporation Power Integrations QROMIS Inc Renesas Rohde & Schwarz GmbH & Co KG Rohm Semiconductor Silicon Works STMicroelectronics Sumitomo Electric Industries Taiwan Semiconductor Mfg Company Tektronix Texas Instruments Inc The Boeing Company Transphorm, Inc. United Silicon Carbide U.S. Army AMRDEC Vishay Corporation VisIC Technologies Wolfspeed, a Cree Company Xiamen Sanan Integrated Circuit Co Xi an Semipower Electronic Technologies Yangtze Memory Technologies Col, Ltd. ZTE Corporation

23 Acknowledgements 25 Mikhail Guz, JEDEC Secretary to JC-70, Consultant, IP and Technology Experts JC-70.1 Task Group Leaders TG701_1 (REL) Co-Chairs: Kurt Smith (VisIC) Mark Wasilewski (ON), Sameh Khalil (Infineon) Sandeep Bahl (TI) TG701_3 (Test) Co-Chairs: Deepak Veereddy (Infineon), Jaume Roig (ON) TG701_2 (Datasheet) Co-Chairs Peter Di Maso (GaNSystems), Nick Fichtenbaum (Navitas) JC-70.2 Chair Jeff Casady (Wolfspeed), Co-Chair Peter Friedrichs (Infineon) TG702_1 (REL) Chair Don.Gajewski (Wolfspeed) TG702_3 (test) Co-Chairs: Thomas Basler (Infineon) Ryo Takeda of Keysight The University Community

24 How Can You Become One of These Companies? 26 Interested companies worldwide are welcome to join JEDEC to participate in this important standardization effort. Find more information about membership or contact Emily Desjardins to learn more

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