64 OON DIVE FO DOT ATIX D INTODUTION The (TQFP type: S6B2107) is an D driver SI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver TQFP type: S6B2108). The is fabricated by low power OS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver). FEATUES Dot matrix D common driver with 64 channel output 64-bit shift register at internal D driver circuit Internal timing generator circuit for dynamic display Selection of master/slave mode Applicable D duty: 1/48, 1/64, 1/96, 1/128 Power supply voltage: + 5V ± 10% D driving voltage: 8V - 17V ( - ) Interface Driver ontroller OON SEGENT Other S6B0108 PU igh voltage OS process 100QFP / 100TQFP or bare chip available 1
64 OON DIVE FO DOT ATIX D BOK DIAGA 1 2 3 62 63 64 64 bit 4- evel Driver 64 bit Bi-Directional Shift egister DIO1 P S Data Shift Direction & Phase Selection ontrol ircuit DIO2 2 OS Timing Generator ircuit F K1 V SS DS1 DS2 S FS 2
64 OON DIVE FO DOT ATIX D 3 PIN ONFIGUATION 100 QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VEE VDD DIO1 FS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DS1 DS2 S V SS S K1 F P DIO2 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VEE 2
64 OON DIVE FO DOT ATIX D PAD DIAGA (IP AYOUT FO TE 100QFP) DIO1 FS DS1 DS2 S V SS S K1 F P DIO2 2 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 21 2 79 44 20 3 78 45 19 4 77 46 18 5 76 47 17 6 75 48 16 7 74 49 15 8 73 50 14 13 9 10 Y 72 71 51 52 12 11 70 53 11 12 69 54 10 13 68 55 9 8 14 15 (0, 0) X 67 66 56 57 7 16 65 58 6 5 4 3 17 18 19 20 hip size: 3450 4000 PAD size: 100 100 Unit : µm 64 63 62 61 59 60 61 62 2 21 60 63 1 22 59 64 VEE 23 58 VEE 24 57 25 56 26 55 27 54 There is the mark on the center of the chip. 4
64 OON DIVE FO DOT ATIX D PAD ENTE OODINATES (100QFP) Pad Number Pad Name oordinate Pad Number Pad Name oordinate Pad Number Pad Name oordinate X Y X Y X Y 1 22-1314.5 1775.4 32 DS2-677.6-1775 71 52 1500.9 630 2 21-1499.9 1630 34-527.6-1775 72 51 1500.9 755 3 20-1499.9 1505 35-377.6-1775 73 50 1500.9 880 4 19-1499.9 1380 37-227.6-1775 74 49 1500.9 1005 5 18-1499.9 1255 39 S -77.6-1775 75 48 1500.9 1130 6 17-1499.9 1130 40 VSS 113.8-1775 76 47 1500.9 1255 7 16-1499.9 1005 42 S 308.7-1775 77 46 1500.9 1380 8 15-1499.9 880 43 458.7-1775 78 45 1500.9 1505 9 14-1499.9 755 44 K1 608.7-1775 79 44 1500.9 1630 10 13-1499.9 630 46 F 758.7-1775 80 43 1310.5 1775.4 11 12-1499.9 505 47 908.7-1775 81 42 1185.5 1775.4 12 11-1499.9 380 49 P 1058.7-1775 82 41 1060.5 1775.4 13 10-1499.9 255 50 DI02 1208.7-1775 83 40 935.5 1775.4 14 9-1499.9 130 52 2 1358.7-1775 84 39 810.5 1775.4 15 8-1499.9 5 54 1500.9-1495 85 38 685.5 1775.4 16 7-1499.9-120 55 1500.9-1370 86 37 560.5 1775.4 17 6-1499.9-245 56 1500.9-1245 87 36 435.5 1775.4 18 5-1499.9-370 57 1500.9-1120 88 35 310.5 1775.4 19 4-1499.9-495 58 VEE 1500.9-995 89 34 185.5 1775.4 20 3-1499.9-620 59 64 1500.9-870 90 33 60.5 1775.4 21 2-1499.9-745 60 63 1500.9-745 91 32-64.5 1775.4 22 1-1499.9-870 61 62 1500.9-620 92 31-189.5 1775.4 23 VEE -1499.9-995 62 61 1500.9-495 93 30-314.5 1775.4 24-1499.9-1120 63 60 1500.9-370 94 29-439.5 1775.4 25-1499.9-1245 64 59 1500.9-245 95 28-564.5 1775.4 26-1499.9-1370 65 58 1500.9-120 96 27-689.5 1775.4 27-1499.9-1495 66 57 1500.9 5 97 26-814.5 1775.4 28 VDD -1345.6-1775 67 56 1500.9 130 98 25-939.5 1775.4 29 DI01-1127.6-1775 68 55 1500.9 255 99 24-1064.5 1775.4 30 FS -977.6-1775 69 54 1500.9 380 100 23-1189.5 1775.4 31 DS1-827.6-1775 70 53 1500.9 505 5
64 OON DIVE FO DOT ATIX D 6 100 TQFP (S6B2107) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S6B2107 (100 TQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 2 DIO2 P F K1 S VSS S DS2 DS1 FS DIO1 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
64 OON DIVE FO DOT ATIX D PAD DIAGA (IP AYOUT FO TE 100-TQFP) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 19 1 45 18 17 16 2 3 4 46 47 48 15 14 5 6 49 50 13 12 11 7 8 9 Y 51 52 53 10 9 10 11 54 55 8 7 6 12 13 14 (0, 0) X 56 57 58 5 4 3 2 1 15 16 17 18 19 hip size: 3850 X 100 PAD size: 100 X 100 Unit : µ m 59 60 61 62 63 VEE 20 21 22 64 VEE 23 24 VDD 25 DIO1 FS DS1 DS2 S V SS S K1 F P DIO2 2 There is the mark S6B2107 on the center of the chip. 7
64 OON DIVE FO DOT ATIX D PAD ENTE OODINATES (100-TQFP) Pad Number Pad Name oordinate Pad Number Pad Name oordinate Pad Number Pad Name oordinate X Y X Y X Y 1 19-1697 1534 35 69 51 1697 784 2 18-1697 1409 36 S -195-1821 70 50 1697 909 3 17-1697 1284 37 VSS 0-1821 71 49 1697 1034 4 16-1697 1159 38 72 48 1697 1159 5 15-1697 1034 39 S 195-1821 73 47 1697 1284 6 14-1697 909 40 345-1821 74 46 1697 1409 7 13-1697 784 41 K1 495-1821 75 45 1697 1534 8 12-1697 659 42 76 44 1500 1822 9 11-1697 534 43 F 645-1821 77 43 1375 1822 10 10-1697 409 44 795-1821 78 42 1250 1822 11 9-1697 284 45 79 41 1125 1822 12 8-1697 159 46 P 945-1821 80 40 1000 1822 13 7-1697 34 47 DIO2 1095-1821 81 39 875 1822 14 6-1697 -91 48 82 38 750 1822 15 5-1697 -216 49 2 1245-1821 83 37 625 1822 16 4-1697 -341 50 84 36 500 1822 17 3-1697 -466 51 1697-1466 85 35 375 1822 18 2-1697 -591 52 1697-1341 86 34 250 1822 19 1-1697 -716 53 1697-1216 87 33 125 1822 20 VEE -1697-841 54 1697-1091 88 32 0 1822 21-1697 -966 55 VEE 1697-966 89 31-125 1822 22-1697 -1091 56 64 1697-841 90 30-250 1822 23-1697 -1216 57 63 1697-716 91 29-375 1822 24-1697 -1341 58 62 1697-591 92 28-500 1822 25 VDD -1697-1466 59 61 1697 466 93 27-625 1822 26 DIO1-1245 -1821 60 60 1697-341 94 26-750 1822 27 FS -1095-1821 61 59 1697-216 95 25-875 1822 28 DS1-945 -1821 62 58 1697-91 96 24-1000 1822 29 DS2-795 -1821 63 57 1697 34 97 23-1125 1822 30-645 -1821 64 56 1697 159 98 22-1250 1822 31 65 55 1697 284 99 21-1375 1822 32-495 -1821 66 54 1697 409 100 20-1500 1822 33 67 53 1697 534 34-345 -1821 68 52 1697 659 8
64 OON DIVE FO DOT ATIX D PIN DESIPTION Table 1. Pin Description Pin Number QFP (TQFP) 28(25) 40(37) 23(20), 58(55) Symbol I/O Description V SS Power For internal logic circuit (+5V ± 10%) GND ( = 0 V) For D driver circuit 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52),,,, Power Bias supply voltage terminals to drive D. Slelect evel Non-Select evel (), () (), () and ( &, &, & ) should be connected by the same voltage. 42(39) S Input Selection of master/slave mode - aster mode (S = 1) DIO1, DIO2, 2 and is output state. - Slave mode (S = 0) S = 1 DIO1 is input state (DIO2 is output state) S = 0 DIO2 is input state (DIO1 is output state) 2 and are input state. 39(36) S Input Selection of data shift direction. S Data Shift Direction DIO1 1... 64 DIO2 DIO2 64... 1 DIO1 49(46) P Input Selection of shift clock (2) phase. P Shift lock (2) Phase Data shift at the rising edge of 2 Data shift at the falling edge of 2 30(27) FS Input Selection of oscillation frequency. - aster mode When the frame frequency is 70 z, the oscillation frequency should be fosc = 430kz at FS = 1( ) fosc = 215kz at FS = 0(V SS ) - Slave mode onnect to. 9
64 OON DIVE FO DOT ATIX D Table 1. Pin Description (ontinued) Pin Number QFP (TQFP) 31(28) 32(29) Symbol I/O Description DS1 DS2 Input Selection of display duty. - aster mode DS1 DS2 Duty 1/48 1/64 1/96 33(30) 35(32) 37(34) 1/128 - Slave mode onnect to Oscillator - aster mode: Use these terminals as shown below. f f Open External Open - Slave mode: Stop the oscillator as shown below. Open Open 44(41) 43(40) K1 Output Operating clock output for the S6B0108 - aster mode: connection to K1 and of the S6B0108 - Slave mode: open 46(43) F Output Synchronous frame signal. - aster mode: connection to F of the S6B0108 - Slave mode: open 47(44) Input/ Output 52(49) 2 Input / Output Alternating signal input for D driving. - aster mode: output state onnection to of the S6B0108 - Slave mode: input state onnection to the controller Data shift clock - aster mode: output state onnection to of the S6B0108 - Slave mode: input state onnection to shift clock terminal of the controller. 10
64 OON DIVE FO DOT ATIX D 29(26) 50(47) DIO1 DIO2 Input/ Output Data input/output pin of internal shift register. S DS2 DIO1 DIO2 Output Output Output Output Input Output Output Input 11
64 OON DIVE FO DOT ATIX D Table 1. Pin Description (ontinued) Pin Number QFP (TQFP) 22-1(19-1) 100-59(100-56) Symbol I/O Description 1-64 Output ommon signal output for D driving. Data Out V 1 V 4 V 5 V 0 34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50) No connection AXIU ABSOUTE IIT haracteristic Symbol Value Unit Note Operating voltage -0.3 to +7.0 V (1) Supply voltage -19.0 to +0.3 V (4) Driver supply voltage V B -0.3 to +0.3 V (1), (2) V D -0.3 to +0.3 V (3), (4) Operating temperature T OP -30 to +85 - Storage temperature T STG -55 to +125 - NOTES: 1. Based on V SS = 0V 2. Applies to input terminals and I/O terminals at high impedance. (Except (), (), () and ()) 3. Applies to (), (), () and (). 4. Voltage level: = = = =. 12
64 OON DIVE FO DOT ATIX D EETIA AATEISTIS D AATEISTIS ( = +5V ± 10%, V SS = 0V, - =8-17V, TA = -30 - +85 ) haracteristic Symbol ondition in Typ ax Unit Note Input Voltage igh V I - 0.7 - V (1) ow V I V SS - 0.3 Output igh V O I O = -0.4mA -0.4 - - V (2) voltage ow V O I O = 0.4mA - - 0.4 Input leakage current I KG V IN = -V SS -1.0-1.0 µa (1) OS frequency On resistance (VDIV- i) f OS ON Operating current I DD1 Supply current I DD2 I EE Operating f op1 f = 47kΩ ± 2% f = 20pf ± 5% - = 17V oad current = ± 150µA aster mode 1/128 Duty Slave mode 1/128 Duty aster mode 1/128 Duty aster mode External clock 315 450 585 kz - - 1.5 KΩ - - 1.0 ma (3) - - 200 µa (4) - - 100 (5) 50-600 kz Frequency f op2 Slave mode 0.5-1500 NOTES: 1. Applies to input terminals FS, DS1, DS2,, S, S and P and I/O terminals DIO1, DIO2, and 2 in the input state. 2. Applies to output terminals K1, and F and I/O terminals DIO1, DIO2, and 2 in the output state. 3. This value is specified at about the current flowing through V SS. Internal oscillation circuit: f = 47kΩ, f = 20pF. Each terminal of DS1, DS2, FS, S and S is connected to and out is no load. 4. This value is specified at about the current flowing through V SS. Each terminal of DS1, DS2, FS, S, P and is connected to, and S is connected to V SS. 2,, DIO1 is external clock. 5. This value is specified at about the current flowing through. Don t connect to V D (-). 13
64 OON DIVE FO DOT ATIX D A AATEISTIS ( = 5V ± 10%, TA = -30 - +85 ) aster ode (S =, P =, f = 20pF, f = 47kW) 2 0.7 0.3 t W t W t W DIO1 (S = ) DIO2 (S = V SS ) t su t D t su t D DIO2 (S = ) DIO1 (S = V SS ) t D t DF F t D t D 0.7 0.3 t F t tw1 K1 t W1 t D12 t D21 t W2 t F t 14
64 OON DIVE FO DOT ATIX D aster ode haracteristic Symbol in Typ ax Unit Data setup time t SU 20 - - µs Data hold time t D 40 - - Data delay time t D 5 - - F delay time t DF -2-2 delay time t D -2-2 2 low level width t W 35 - - 2 high level width t W 35 - - K1 low level width t W1 700 - - ns low level width t W2 700 - - K1 high level width t W1 2100 - - high level width t W2 2100 - - K1- phase difference t D12 700 - - -K1 phase difference t D21 700 - - K1, rise/fall time t /t F - - 150 15
64 OON DIVE FO DOT ATIX D Slave ode (S = V SS ) 2 (PK2 = V SS ) t F t t W1 0.7V DD 0.3 t W1 t SU t W2 t W 2 (PK2 = ) DIO1 (S = ) DIO2 (S = V SS ) Input Data t t t t D F 0.7 0.3 t DIO1 (S = ) DIO2 (S = V SS ) Onput Data 0.7 0.3 haracteristics Symbol in Typ ax Unit Note 2 low level width t W1 450 - - ns P = V SS 2 high level width t W1 150 - - ns P = V SS 2 low level width t W2 150 - - ns P = 2 high level width t W 450 - - ns P = Data setup time t SU 100 - - ns Data hold time t D 100 - - ns Data delay time t D - - 200 ns (NOTE) Output data hold time t 10 - - ns 2 rise/fall time t /t F - - 30 ns NOTE: onnect load = 30pF Output 30pF 16
64 OON DIVE FO DOT ATIX D FUTIONA DESIPTION Oscillator The Oscillator generates 2,, F of the, and K1 and of the S6B0108 by the oscillation resister and capacitor. When selecting the master/slave mode, the oscillation circuit is as following: aster ode: In the master mode, use these terminals as shown below. f f 47KΩ 20pF Internal Oscillation Open External lock External lock Open Slave ode: In the slave mode, stop the oscillator as shown below. Open Open Timing Generation ircuit It generates 2,, F, K1 and by the frequency from the oscillation circuit. Selection of aster/slave (/S) ode - When /S is, it generates 2,, F, K1 and internally. - When /S is, it operates by receiving and 2 from the master device. Frequency Selection (FS) To adjust F frequency by 70z, the oscillation frequency should be as follows: FS Oscillation Frequency f OS = 430kz f OS = 215kz In the slave mode, it is connected to. 17
64 OON DIVE FO DOT ATIX D Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 DS2 DUTY 1/48 1/64 1/96 1/128 Data Shift & Phase Select ontrol Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the 2 according to P. P Phase Selection Data shift on rising edge of 2 Data shift on falling edge of 2 Data Shift Direction Selection When /S is connected to, DIO1 and DIO2 terminal is only output. When /S is connected to V SS, it depends on the S. S S DIO1 DIO2 Direction of Data Output Output 1 64 Output Output 64 1 Input Output DIO1 1 64 DIO2 Output Input DIO2 64 1 DIO1 18
64 OON DIVE FO DOT ATIX D TIING DIAGA 1/48 DUTY TIING (ASTE ODE) ondition: DS1 =, DS2 =, S = (), P = K1 1 2 3 63 64 2 F DIO1 ( DIO2 ) 1 ( 48 ) 2 ( 47 ) 1 2 3 46 47 48 1 2 3 46 47 48 47 ( 2 ) 48 ( 1 ) DIO2 ( DIO1 ) elation of 2 & DIO1 ( DIO2 ) 2 DIO1 ( DIO2 ) 19
64 OON DIVE FO DOT ATIX D 1/128 DUTY TIING (ASTE ODE) ondition: DS1 =, DS2 =, S = (), P = K1 1 2 3 23 24 2 1 2 3 126 127 128 1 2 3 126 127 128 F DIO1 ( DIO2 ) 1 ( 128 ) 2 ( 127 ) 127 ( 2 ) 128 ( 1 ) DIO2 ( DIO1 ) elation of 2 & DIO1 ( DIO2 ) 2 DIO1 (DIO2) 20
64 OON DIVE FO DOT ATIX D 1/48 DUTY TIING (SAVE ODE) ondition: P =, S = () 1 2 46 47 48 1 2 46 47 48 2 DIO1 ( DIO2 ) 1 ( 48 ) 2 ( 47 ) 47 ( 2 ) 48 ( 1 ) DIO2 ( DIO1 ) 21
64 OON DIVE FO DOT ATIX D POWE DIVE IUIT / 1 / 1 V2 2 V3 To S6B0108 1 / 1 V / elation of Duty & Bias Duty Bias DIV 1/48 1/8 2 = 41 1/64 1/9 2 = 51 1/96 1/11 2 = 71 1/128 1/12 2 = 81 When duty factor is 1/48, the value of 1 & 2 should satisfy. 1/(41 + 2) = 1/8 1 + 3kΩ, 2 = 12kΩ 22
64 OON DIVE FO DOT ATIX D APPIATION IUIT 1/128 duty Segment driver (S6B0108) interface circuit 15 / V2/ V3/ / S3 S2B S1B S6B0108 DB0 -DB7 STB E /W S F K1 V SS S 1 - S 64 SEG128 S 1 - S 64 / V2/ V3/ S3 S2B S6B0108 S1B DB0 -DB7 STB E /W S V SS F K1 D Panel / V2/ V3/ / / / V2/ V3/ / 15 15 5 S3 S2B S1B S6B0108 DB0 -DB7 STB E /W S F K1 V SS S 1 - S 64 SEG1 O1 O128 S 1 - S 64 S3 S2B S6B0108 S1B DB0 -DB7 STB E /W S V SS F K1 15 S /W E 15 STB DB0 - DB7 S1B S2B S3 5 PU 1 1 1 S FS S V SS 64 V 0/ V 1/ V 4/ V 5/ DIO1 DIO2 DS1 2 DS2 (master) P K1 F open open 2 5 1 DIO2 2 V 0/ 64 V 1/ P V 4/ FS V 5/ DS1 (slave) KS2 V SS S K1 F S open open open open open V 0 V 1 V 2 V 3 V 4 V 5 23