Chapter 8 Registers SKEE2263 igital Systems Mun im Zabidi {munim@utm.my} Ismahani Ismail {ismahani@fke.utm.my} Izam Kamisian {e-izam@utm.my} Faculty of Electrical Engineering, Universiti Teknologi Malaysia March 27, 28
Table of Contents Registers 2 Shift Registers 3 Accumulators 4 Register Files 5 Register Transfer Language
Basic Register 3 2 Clk 3 2 Clk Ignored [3:] [3:]
Resettable Register 3 2 CLR CLR CLR CLR Clk Clear 3 2 Clk [3:] Clear [3:] xxxx Cleared
Register with Load Enable 3 2 Load Clk 3 2 Clk [3:] Load [3:] xxxx
Basic Shift Register Input Clk 3 2
Shift Register Animation Initial condition CLK After first clock pulse After second clock pulse After third clock pulse After fourth clock pulse After fifth clock pulse CLK CLK CLK CLK CLK
Shift Register Timing iagram Clk Input 3 2
Enabled Shift Register Input Shift Clk 3 2 Clk Input Shift [3:]
Universal Shift Register 3 2 RSI S S LSI Clear Clk S S Function Hold Shift left Shift right Load new input 3 2 Can be used in either serial-to-serial, serial-to-parallel, parallel-to-serial, parallel-to-parallel, left shifting as well as right shifting. Useful in arithmetic operations to shift data left for multiplication or to shift data right for division.
Universal Shift Register Schematic 3 2 RSI LSI 3 2 3 2 3 2 3 2 S: S: S: S : Clear Clk 3 2
Universal Shift Register Timing iagram Clk RSI LSI [3:] 2 4 6 8 A C E 2 S[:] 3 3 2 2 3 [3:] 2 4 8 A 5 2 2
Accumulators Accumulator 6 + Acc Clock Accumulator: register that keeps results of arithmetic ops. Registers + Adders Accumulator-based counter. Any adder architecture may be used. Clk Acc 2 3 4 5 3E 3F Accumulator overflow
6-bit Accumulator-Based Counter 5 4 3 2 HA HA HA HA HA HA Clk 5 4 3 2
Resettable Counter + Accumulator Acc Clear Function Run Clear Clear Clock Check your understanding. This is Milestone 2.
Multi-Function Counter No. + +2-2 3 Accumulator Acc S S Function Clear Add Add 2 Subtract S S Clock
Multi-Function Counter No.2 2 3 4 Adder Accumulator 4 4 Acc S S Function Hold Add Add 2 Subtract S S Clock
Prescaler.5s s - 25 Hz x7784 Preload (25,,) 5 MHz 25-bit accumulator
Timer sec Trig Out Timer Clock 5 MHz Clock Trig Out sec
Timer - x2faf8 26 26-bit accumulator Out Preload (5,,) Trig 5 MHz Trig
Register Files vs RAM Register Files RAM Capacity Small Large Speed Fast Slow Ease of esign Easy Harder
Minimal Register File 8 2 2 atain WriteAddr WriteEn ReadAddr 4 x 8 register file ataout Four 8-bit registers 8 atain : n-bit input ataout : n-bit output WriteAddr: log 2 n-bit write address ReadAddr: log 2 n-bit read address WriteEn: write enable
Minimal Register File atain ReadAddr WriteAddr 2:4 decoder Register Ld Register Ld Register 2 Ld Register 3 Ld 4: MUX ataout WriteEn
Register File with 2 Read Ports 8 2 2 2 atain WriteAddr WriteEn ReadAddrA ReadAddrB OutA OutB 8 8 4 x 8 register file
Register File with 2 Read Ports ReadAddrA Register Register Register 2 Register 3 4: MUX OutA 4: MUX OutB ReadAddrB
Overview of RTL atapath: combination of registers and combinational circuits which manipulate data atapath design is derived from high-level algorithms RTL: high-level description of micro-operations happening in the datapath RTL allows designers to solve problems at high-level; and worry about details later
Elements of RTL Elements: Register set Operations performs on data in the registers The sequence of operations R2 Combinational logic Control circuit Load Ld R Clock RTL syntax:
RTL Instruction Set Notation Intended Operation X Y Transfer contents of reg. Y to reg. X R Clear contents of REG X all s Set all bits of reg. X X Set the LSB of X and reset all other bits X shl X -bit left-shift X shr X -bit right-shift X 3: X 3: X 3:4 4-bit end-around right-shift X M[x234] X content of memory address x234 X M[Y ] X content of memory pointed by Y X Y Z X Y OR Z (bitwise) X Y Z X Y AN Z (bitwise) X Y Z X Y XOR Z (bitwise) X Y X s complement of Y X Y X 2 s complement of Y X Y + Z X addition of Y and Z X Y Z X subtraction of Z from Y K + + Shorthand for K K + X Y, A B Parallel transfers (cond)/a B if (cond) is true, then transfer B to A S:A B when in state S, transfer B to A P:(x y)/a B when in state P, if x AN y is true, then transfer B to A
Simple atapath RTL emo ReadAddrA 4 x 8 reg file ReadAddrB WriteAddr WriteEn OutA + Inata atain OutB Mode Input Mode Mode R d R a R d R a + R b
Simple atapath RTL emo RTL ReadAddrA ReadAddrB WriteAddr Mode R R XX R R3 XX R3 R + R Mode Mode R d R a R d R a + R b
Simple atapath RTL emo uestion: What is the RTL sequence to exchange R with R (R R)? Assume R2 and R3 are available for temporary storage.