A Hybrid Si IGBT and SiC MOSFET Module Development

360 CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, DECEMBER 2017 A Hybrid Si IGBT and Module Development Puqi Ning, Member, IEEE, Lei Li, Xuhui Wen, Member, IEEE and Han Cao Abstract A compact wirebond packaged phase-leg SiC/Si hybrid was designed, developed, and tested. Details of the layout and gate drive designs are described. The IC chip for gate drive is carefully selected and compared. Dual pulse test confirmed that, the switching loss of hybrid is close to pure, and it is much less than pure Si IGBT device. The cost of hybrid is closer to Si IGBT. Index Terms Gate drive design, hybrid, SiC device. I. INTRODUCTION N recent years, the silicon carbide (SiC) power Isemiconductor has emerged as an attractive alternative that pushes the limitations of junction temperature, power rating, and switching frequency of silicon (Si) devices [1-3]. Some manufactures have successfully fabricated s which demonstrated these advantages. s have very low on-state voltage drop and faster switching speed compared to Si devices. However, the price of is commonly 3 to 5 times of the same rating Si IGBT device. Table I shows the comparison between some discrete SiC MOSFETs and some discrete Si IGBT [4]. Although the advanced properties of will lead converters to higher power density [3], some issues still need to be resolved to take full advantage of SiC. For example, almost all the SiC s are still using Si device based conventional packages. These packaging structures have large parasitic parameters (15~70 nh) and limit the operation temperature (less than 150 C). Furthermore, most of these SiC s are lack of reliability testing data. Unfortunately, these s are very expensive and some product s are listed in Table II [4]. This work is supported by The National key research and development program of China (2016YFB0100600), the Key Program of Bureau of Frontier Sciences and Education, Chinese Academy of Sciences (QYZDBSSW-JSC044), and the National Natural Science Foundation of China (No. 51507166). Puqi Ning is with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, 100190 China and Collaborative Innovation Center of Electric Vehicles in Beijing (e-mail: npq@ mail.iee.ac.cn). Lei Li is with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, 100190 China (e-mail: lilei@ mail.iee.ac.cn). Xuhui Wen is with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, 100190 China (e-mail: wxh@ mail.iee.ac.cn). Han Cao is with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, 100190 China (e-mail: chan@ mail.iee.ac.cn). TABLE I PRICE COMPARISON OF SIC AND SI DISCRETE DEVICES Part number Type & voltage Rated current Price ST SCT50N120 65 A @ 25 C 50 A @ 100 C 35.13 $ for 1 pc. 30.95 $ for 25 pc. IXYS IXFN70N120SK 68 A @ 25 C 48 A @ 100 C 109 $ for 1 pc. 99.14 $ for 25 pc. CREE C2M0025120D 90 A @ 25 C 60 A @ 150 C 69.8 $ for 1 pc. 67.12 $ for 100 pc. Rohm SCT3030KL 72 A @ 25 C 51 A @ 150 C 44.21 $ for 1 pc. 39.52 $ for 25 pc. Microsemi 56 A @25 C 78.36 $ for 1 pc. APT80SM120J Infineon IGW60T120FKS A1 IXYS IXYH82N120C3 Si IGBT Si IGBT 40 A @125 C 100 A @25 C 60 A @100 C 160 A @25 C 82 A @110 C 66.49 $ for 100 pc. 7.12 $ for 1 pc. 5.33 $ for 100 pc. 13.44 $ for 1pc. 8.52 $ for 1000pc. Reference [5], reported the development of a 1200 kv/880a SiC which can handle megawatt. The cost was estimated close to 2500$. Reference [6] presented the design and development of a HP1 package based SiC three-phase, and the power rating is / 300A for each phase-leg. There were 36 SiC MOSETs and 36 SiC diodes in the, which makes the cost for each close to 7000 $. An Int-A-Pak version was also presented in [6]. Without any SiC diode, the cost is cut to 5000$. All these s are too expensive for regular industrial applications. TABLE II PRICE COMPARISON OF SIC AND SI MODULES Manufacture and Part Rated voltage number and current Topology Price (US dollar) Infineon DF11MR12W1M1_B11 50 A Boost 119.04 $ for 1 pc. 107.88 $ for 25 pc. Rohm BSM180D12P3C007 180 A Phase-leg 506.97 $ for 1 pc. 476.42 $ for 5 pc. Rohm SiCMOSFET BSM300D12P2E001 300 A Phase-leg 668.18 $ for 1 pc. 654.43 $ for 5 pc. CREE/ Wolfspeed SiC Phase-leg 330 $ for 1 pc. CAS120M12BM2 193 A Infineon Si IGBT Phase-leg 145.33 $ for 1 pc. FF400R12KT3 Microsemi APTGLQ400A120T6G 580 A 625 A Phase-leg 136.38 $ for 25 pc. 184.36$ for 100 pc. Because of bipolar carriers and long tail current at turn-off phase, IGBTs can t switch over 20kHz generally. On the contrary, MOSFETs have no tail current but the rated currents become too small when the voltage is over 900 V. In many future applications, for example, Wireless power transmission (WPT) for Electric Vehicle (EV), more electric aircraft (MOA) and solid state transformer (SST), the converter requires high speed switching, medium/high power, low on-resistance and

NING et al. : A HYBRID SI IGBT AND SIC MOSFET MODULE DEVELOPMENT 361 reasonable price. In many countries, the line frequency of WPT of EV is set to 85 khz in standards, which bring a tough challenge to develop a 30 kw WPT fast charging converter. To overcome the challenges, the combination of IGBT and MOSFET devices was investigated by compensating disadvantages [7]. Among them, hybrid switches based on parallel connection between Si IGBT and were studied [8-10]. In these paper, the losses and costs of hybrid switches have been investigated and verified. In [11], to further reduce the switching loss, the switching pattern using commutation was analyzed in detail. Most of these papers focus on discrete device hybrid, which brings in large inductance in the circuit. They didn t demonstrate any larger current case (none is over 100 A). This paper evaluates the performance of a /200A hybrid phase-leg. The detailed packaging, development, gate drive circuit design, and performance comparison are presented. It gives an novel approach of hybrid switches used for over 10 kw applications. Based on datasheets, the conduction performance of hybrid is shown in Fig.2. The conduction loss of hybrid is very close to Si IGBT, while the cost is also close to Si IGBT. Current (A) Output Characteristics 350 350 300 300 250 250 200 200 150 150 100 100 SiC MOS Si IGBT Hybrid 50 50 00 0 0.5 1 1.5 2 2.5 3 3.5 Voltage(V) Conduction performance comparison II. HYBRID MODULE DEVELOPMENT The design target is a /200 A hybrid phase-leg. To evaluate the paralleling possibility of devices in hybrid, each leg includes two same rating Si IGBTs, one and one Si Diode. To reduce the parasitic parameters and prevent interference from the main power, Kelvin source pin of gates (Gates1 and Gates2) are added to both legs. The circuit of the hybrid is shown in Fig.1. Fig. 1. Hybrid circuit. Some high performance dies are chosen for this, and the properties are listed in Table III. Based on the safe operation suggestion from [11], the total current of s and Si IGBTs are selected as maximum 1:4 matching. Table III PROPERTIES OF SIC/SI DEVICES Device SiC Si IGBT Si Diode MOSFET Part number CPM2-1200- IRG8CH97K10F IRD3CH82DB6 0025B Rated voltage (V) 1200 1200 1200 Rated current (A) 90@25 C 100@175 C 150@175 C 50@150 C Dimensions 4.04 mm 10.5 mm 6.44 mm 9.3 mm Cost 75$ 8.26$ 4.96$ 9.07 mm 9.07 mm Cost comparison Fig. 2. Conduction performance and cost comparison. The packaging design target is reliable 175 C operation and possible 200 C operation. Based on a comprehensive survey and lab evaluation, materials for each part of the power package were compared and selected. The final materials selection is listed in Table IV. Since high speed switching is required for this, power terminals and gate signal terminals are bonded to DBC with ultrasonic bonding methods to reduce parasitic parameters. Baseplate Substrate TABLE IV MATERIAL SELECTION FOR 200 ºC MODULE. Aluminum Silicon Carbide (AlSiC), 3 mm thick Aluminum nitride (AlN) direct bond copper (DBC) with 15 mils thick AlN, 8 mils thick copper Die attachment Au-Sn solder (280ºC melting point) Wirebond 6 mils aluminum wire for gate pads 15 mils aluminum wire for other pads Encapsulant Nusil R-2188 Power terminal 0.8 mm thick copper terminal Signal terminal 1 mm diameter copper pin The next step is layout design, and a genetic algorithm (GA) based layout optimization in [12] is utilized to generate a high performance design. The design space of the layout is fully searched. By considering the reduction of the parasitic parameters, minimizing the footprint, and balancing the thermal dissipation path, the decoupling gate paths, and the power paths, devices are placed and routed on the substrate. The compact layout is shown in Fig.3, and the fabricated prototype is shown in Fig.4.

362 CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, DECEMBER 2017 temperature. The value can t be directly tested. The gate drive conceptual diagram is shown in Fig.6. In this paper, Delay1 is fixed to zero, and the value of Delay 3 can be estimated by datasheets of IGBTs and MOSFETs. Delay 2 is implemented by a simple analog circuit with Schmitt inverters. The length of Delay 2 can be adjusted by C1, R1 and R2. In fact, the length is adjusted and optimized during experiments. Since the turn-off delay of IGBTs is larger than those of MOSFETs, Delay 2 should be long enough to ensure the full turn-off of IGBTs before the beginning of MOSFETs turn-off. In this paper, Delay 2 is finally set to 2 μs. Fig. 3. Hybrid layout design. Fig. 4. Hybrid prototype. III. GATE DRIVE DESIGN WITHOUT MILLER CLAMP To eliminate large switching loss in Si IGBT, is turn-on earlier than Si IGBT. Then, Si IGBT will be turn-off prior to. It is also expected to realize zero voltage switching (ZVS) for IGBT for both turn-on and turn-off phase. The gate signal pattern (delay 1 and delay2) will affect the total loss of the hybrid switch. The gate drive signal (pulse1 and pulse2) and turn on/off voltage are shown in Fig.5. Fig. 6. Gate drive conceptual diagram (without miller clamp). The performance of this gate drive is evaluated by a dual pulse test setup. The dual pulse test is a classical experiment test for power semiconductor s. Most characteristics of switches and diodes within the power s can be obtained by the dual pulse test. The test principle and diagram are illustrated in Fig.7. The test setup is shown in Fig.8. Fig. 7. Dual pulse test circuit and principle. Fig.5. Gate drive time delay. Delay 1 and Delay2 can be controlled in the circuit. Delay 3 and Delay 4 will change with DC bus voltage, current and The test waveform is shown in Fig.9. During the turn-off phase, a miller effect can be clearly found from the figure. For fast switching of, high dv/dt will bring electrical interference to Si IGBT drive path. A Miller current appears and the gate voltage of Si IGBT device (V GE) increases. This

NING et al. : A HYBRID SI IGBT AND SIC MOSFET MODULE DEVELOPMENT 363 voltage exceeds the threshold voltage of V GE and a fault re-turn-on happens (shown in Fig.7). Si IGBTs share part of current from, and the tail current happens again. The same phenomenons can be found from [9] and [11]. IV. GATE DRIVE DESIGN WITH MILLER CLAMP Negative off-state gate voltage is generally used to prevent the Miller effect [13]. However, in each leg of this hybrid, the and Si IGBTs shares the same ground. can only accept a -5 V negative off gate voltage. While -5 V can t fully mitigate the miller effect and tail current. At the same time, additional isolated DC source should be added to the gate drive, which increase the complexity and the total cost. Fig. 8. Double Pulse Test Setup. It means that, IGBT chips are turned on in ZVS mode, but not fully ZVS in turn off phase. Although the length of the tail current is shorter than the conventional IGBT, the power loss is much larger than that of a pure turn-off. The detailed comparison is listed in Section 3. Fig. 10. Function block diagram of ACPL-332J. In [13], commercial chips ACPL-332J with built-in turn-on/turn-off path separators were utilized. When IGBT is off, a low-impedance path is established inside the gate drive chips and the gate voltage spikes can be reduced. The function block diagram of ACPL-332J is depicted in Fig.10. During turn-off, the gate voltage is monitored and the low impedance path is activated when the gate voltage goes below 2V. For Si IGBT gate, the gate drive chip HCNW3120 is changed to A332J to overcome the miller effect. HCNW3120 is still used for gate to reduce the complexity and cost. The gate drive conceptual diagram is shown in Fig.11. (a) Turn off at 600V/ 200 A (b) Turn on at 600V/ 200 A Fig. 9. Hybrid without miller clamp. Fig. 11. Gate drive conceptual diagram (with miller clamp). The improved gate drive circuit was evaluated to compare the switching losses. The hybrid was tested up to 600

364 CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, DECEMBER 2017 V/200 A. The gate resistor of is 47Ω, and the gate resistor of Si IGBT is 15Ω. The experimental results are shown in Fig.12. It is noticed that the miller effect is mitigated within an acceptable range and the induced gate voltage of Si IGBT didn t pass the threshold voltage. Thus no obvious tail current was found in the tests. To compare the hybrid performance, a /150 A prototype was fabricated with the same package, which is shown in Fig.14. The was tested up to 600 V/ 150 A by the same dual pulse test setup. One of experimental waveform is shown in Fig.15. Turn off at 600V/ 200 A Fig. 14. 150 A. The gate resistor was also adjusted for pure. Test results of 15 Ω set and 10 Ω set are listed in Table 5. Lower speed drive (15 Ω set) has larger power loss during turn on and turn off (close to 4 times), but smaller overshoot voltage (about 60 V). Turn on at 600V/ 200 A Fig. 12. Hybrid with miller clamp. The gate resistor was also adjusted to increase the turn on/off speed of. When gate resistor is reduced to 15Ω, a clear vibration is noticed, as shown in Fig.13. During the turn off phase, is operated 3 times larger of the rated current. It is very close to the safe operation area (SOA) boundary. A over speed gate drive may induce an unreliable switching. (a) Turn off at 600V/150A (b) Turn on at 600V/ 150 A Fig. 13. Hybrid vibrates with over speed turn-off. Fig. 15. switching.

NING et al. : A HYBRID SI IGBT AND SIC MOSFET MODULE DEVELOPMENT 365 Item TABLE V DOUBLE PULSE TEST RESULTS COMPARISON Hybrid without miller clamp Hybrid with miller clamp Hybrid with only IGBT operated SiC MOSFET SiC MOSFET V CC (V) 600 600 600 600 600 I C (A) 200 200 200 150 150 L (uh) 50 50 50 50 50 Vge_on MOS 20 MOS 20 MOS 0 20 20 (V) IGBT 15 IGBT 15 IGBT 15 Vge_off 0/0 0/0 0/0-5/-5-5 (V) Rg_ext MOS 5 MOS 47 IGBT 15 15 10 (Ω) IGBT 15 IGBT 15 t rv(ns) 296.8 120 400 130.8 48 t fi(ns) 104.8 200 83 104 36 t off(ns) 537.6 460 1861 613.6 304 E off(mj) 34.11 11.03 40.26 14.3 3.4 V CEpk(V) 676 664.81 676 666 730 t ri(ns) 68 100 62 160 46 t fv(ns) 72.8 120 207 214.4 84 t on(ns) 134.4 160 307 322.8 78 E on(mj) 8.16 10.99 12.14 15.72 4.1 Table V also compares hybrid performance with and without miller clamp. To compare the performance of pure Si IGBT device, the hybrid is tested up to 600 V/200A with only IGBT switching. In this test, gate pins of SiC MOSFET (MOSg1 and MOSg2) were shorted to source pins of MOSFET (Gates1 and Gates2). Fig. 16. Time related parameter definition in Table V. The time related parameters in table 5 is defined in Fig.16. It can be learned that, with miller clamp and proper gate resistor selection, the switching loss of hybrid is close to pure, and it is much less than pure Si IGBT device. Because of the propagation delay difference and the pcb layout design, E on of hybrid with miller clamp is little larger than that of hybrid without clamp. When choosing gate drive ICs with miller clamps, small propagation delay and large supply current is preferred. In the next step, the will be evaluated by dual pulse test under 175 C and 200 C. A converter over 30 kw will be developed based on hybrid s. This converter can help to investigate the continuous performance of hybrid s. V. SUMMARY AND CONCLUSION In order to better utilize the advantages of SiC devices, this paper presents a systematic design procedure. With the details in packaging design, layout design, and gate drive design, a compact hybrid is obtained. The promising results of dual pulse tests validated the design methods and demonstrated a reasonable operation. Together with the parameter adjustment, some practical considerations in the gate drive development are presented. The hybrid combines low conduction loss of Si IGBT and low switching loss of, and the cost is closer to Si IGBT.The proved high performances of SiC/Si hybrid power will result in considerable achievement to enhance power density of a converter system. REFERENCES [1] C J. Rabkowski, D.Peftitsis, H. Nee, "Silicon Carbide power transistors: A new era in power electronics is initiated," in IEEE Industrial Electronics Magazine, Vol.6, Issue 2, pp.17-26, June 2012. [2] D. Han, J. Noppakunkajorn, B. Sarlioglu, "Comprehensive efficiency, weight, and volume comparison of SiC and Si based bidirectional DC-DC converters for hybrid electric vehicles," in IEEE Trans. on Vehicular Technology, Vol. 63, No. 7, pp.3001-3010, Sep. 2014.. [3] Y. Murakami, Y. Tajima, S. Tanimoto, "Air-Cooled Full-SiC High Power Density Inverter Unit," in Proc. IEEE EVS27, 2013. [4] www.mouser.com. [5] J. Richmond, M. Das, S. Leslie, and etc., "Roadmap for megawatt class power switch s ulilizing large area silicon carbide MOSFETs and JBS diodes," in IEEE proc. ECCE 2009, pp. 106-111.. [6] P. Ning, L. Li and X. Wen, "Engineering Investigation on Compact Power Module for EV Application," in IEEE proc. IECON 2017, pp.1-7. [7] K. Hoffmann, J. Karst, "High frequency power switch improved performance by MOSFETs and IGBTs connected in parallel," in IEEE proc. EPE 2005, pp.11. [8] A. Deshpande, F. Luo, "Design of a silicon-wbg hybrid switch," IEEE WiPDA 2015, pp. 296-299. [9] J. He, R. Katebi, N. Weise, A Current-Dependent Switching Strategy for Si/SiC Hybrid Switch Based Power Converters, in IEEE Trans. on Industrial Electronics,Vol. PP, Issue. 99, pp, 1-1, 2017. [10] D. Aggeler, F. Canales, J. Biela, and etc., Dv/Dt -Control Methods for the SiC JFET/Si MOSFET Cascode, in IEEE Trans. on Power Electronics, Vol. 28, Issue. 8, pp. 4074-4082. [11] S. Ueno, N. Kimura, T. Morizane and etc., "Study on Characteristics of Hybrid Switch using Si IGBT and depending on External Parameters," in IEEE proc. EPE2017, pp.1-10. [12] P.Ning, and Xuhui Wen, "A Fast Universal Power Module Layout Method", in IEEE proc. ECCE2015, pp.4132-4237. [13] P. Ning, F. Wang, and D. Zhang, "A High Density 250 C Junction Temperature SiC Power Module Development," in IEEE Journal of Emerging & Selected Topics in Power Electronics, pp. 415-424, 2014. Puqi Ning received his Ph.D. degree from electrical engineering of Virginia Tech, Blacksburg, US in 2010. He is full professor in Institute of Electrical Engineering, Chinese Academy of Sciences. Dr. Ning has been involved in high temperature packaging and high density converter design for more than 10 years.

366 CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, DECEMBER 2017 Lei Li is a Ph.D. student in Institute of Electrical Engineering, Chinese Academy of Sciences. He has been involved in power device modeling and high density converter design for 3 years. Xuhui Wen received her B.S, M.S and PhD degree in electrical engineering from Tsinghua University in 1984, 1989, 1993 respectively. She is full professor in Institute of Electrical Engineering, Chinese Academy of Sciences. Dr. Wen has been involved in high power density electrical drive and generation especially for electric vehicle application for more than 20 years. Han Cao is a Master student in Institute of Electrical Engineering, Chinese Academy of Sciences. He has been working on power device modeling and high density converter design for 1 year.