Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 20 Assembly and Packaging
Four Important Functions of IC Packaging 1. Protection from the environment and handling damage. 2. Interconnections for signals into and out of the chip. 3. Physical support of the chip. 4. Heat dissipation.
Traditional Assembly and Packaging Wafer Test and Sort Die Separation Die Attach Wire Bond Plastic Package Final Package and Test Figure 20.1
Typical IC Packages Dual in-line package (DIP) Single in-line package (SIP) Thin small outline package (TSOP) Quad flat pack (QFP) Plastic leaded chip carrier (PLCC) Leadless chip carrier (LCC) Figure 20.2
Design Constraints for IC Packaging Performance Size/weight/form Materials Cost Assembly RC Time delay Number of signal I/Os Wirebond vs. bump attachment Package impedance Signal rise time Switching transients Thermal Chip size Package size Bond pads size and pitch Package leads size and pitch Substrate carrier pads size and pitch Design of heat sink Chip substrate (plastic, ceramic, metal) Carrier (organic, ceramic) Thermal expansion mismatch Lead metallurgy Integration into existing process Package materials Yield Method of die attach Package attach (through hole, surface mount, bumped) Heat sink assembly Encapsulation
Levels of IC Packaging First level packaging: IC packaging Metal leads for mounting onto printed circuit board Leads Pins 2nd level packaging: Printed circuit board assembly Final product assembly: Final assembly of circuit boards into system Surfacemount chips are soldered on top of tinned pads on the PCB. Pins are inserted into holes then soldered on rear of PCB. Edge connector plugs into main system. PCB subassembly Main electronics assembly board Figure 20.3
Traditional Assembly Wafer preparation (backgrind) Die separation Die attach Wire bonding
Schematic of the Backgrind Process Downforce Rotating and oscillating spindle Wafer on rotating chuck Table rotates only during indexing of wafers Figure 20.4
Wafer Saw and Sliced Wafer Wafer Stage Blade Figure 20.5
Typical Leadframe for Die Attach Leadframe Lead Die Plastic DIP Figure 20.6
Epoxy Die Attach Die Epoxy Leadframe Figure 20.7
Au-Si Eutectic Attach Gold/silicon eutectic alloy Gold film Silicon Al 2 O 3 Figure 20.8
Wires Bonded from Chip Bonding Pads to Leadframe Die Moulding compound Bond wire Bonding pad Leadframe Pin tip Figure 20.9
Wirebonding Chip to Leadframe Photo 20.1
Thermocompression Bonds Post Device bond pad Figure 20.10
Ultrasonic Wirebonding Sequence Wedge tool Wire Al bonding pad Ultrasonic energy Die Pressure Tool moves upward. More wire is fed to tool. (1) (2) (3) Ultrasonic energy Pressure Wire breaks at the bond. Tool moves upward. Lead frame (4) (5) Figure 20.11
Gold wire Capillary tool Thermosonic Ball Bond Pressure and ultrasonic energy Tool moves up and more wire is fed. Ball H2 torch Die Bonding ball on pad Die (1) (2) (3) (4) Pressure and heat form bond. Tool moves upward. Lead frame Wire breaks at the bond. (5) (6) Figure 20.12
Wirebond Pull Test Hook Post Device Chip under test Specimen clamp Figure 20.13
Traditional Packaging Plastic Packaging Ceramic Packaging
TO-Style Metal Package Figure 20.14
Tie Bar Removal from Leadframe Leadframe Die Tie bar Tie bar removal lines Figure 20.15
Plastic Dual In-Line Package (DIP) for Pin-In-Hole (PIH) Figure 20.16A
Single In-Line Package (SIP) Figure 20.16B
Thin Small Outline Package (TSOP) with Gull wing Surface Mount Leads Figure 20.16C
Single In-Line Memory Module (SIMM) Figure 20.16D
Quad Flatpack (QFP) with Gull Wing Surface Mount Leads Figure 20.16E
Plastic Leaded Chip Carrier (PLCC) with J-Leads for Surface Mount Figure 20.16F
Leadless Chip Carrier (LCC) Figure 20.16G
Laminated Refractory Ceramic Process Sequence Ceramic interconnect layers 4-layer laminate Figure 20.17
Ceramic with Pin Grid Array Courtesy of Advanced Micro Devices Photo 20.2
CERDIP Package Plane of cross-section Indexing notch Chip on epoxy and leadframe Cross-section Ceramic lid Glass seal Metal lead Ceramic base Figure 20.18
Test Socket for IC Package Figure 20.19
Advanced Packaging Flip chip Ball grid array (BGA) Chip on board (COB) Tape automated bonding (TAB) Multichipmodules (MCM) Chip scale packaging (CSP) Wafer-level packaging
Flip Chip Package Connecting pin Substrate Via Metal interconnection Silicon chip Solder bump on bonding pad Figure 20.20
C4 Solder Bump on Wafer Bonding Pad Bonding pad Nitride Oxide Al 3-layer metal stack Cu-Sn Cr+Cu Cr Metal Deposition and Etch (1) 2-layer metal deposition Sn Pb Solder bumps form during reflow Reflow Process (2) (3) (4) Figure 20.21
Epoxy Underfill for Flip chip Solder bump Chip Epoxy Substrate Figure 20.22
Flip Chip Area Array Solder Bumps Versus Wirebond Flip chip bump area array Bonding pad perimeter array Figure 20.23
Chip with Ball Grid Array Photo 20.3
Ball Grid Array Bonding pad Molded cover Wire Chip Epoxy Substrate Metal via Solder ball Thermal via Figure 20.24
Chip on Board (COB) IC chip Printed circuit board Figure 20.25
Tape Automated Bonding (TAB) Poyimide tape Copper leads Figure 20.26
Multichip Module (MCM) Individual die MCM substrate Figure 20.27
Trends for Advanced Packaging Units (millions) 1800 1500 1200 900 600 300 0 1996 1997 1998 1999 2000 2001 Direct Chip Attach Flip Chip on Board Tape Auto. Bonding Other Years Redrawn from S. Winkler, Advanced IC Packaging Markets and Trends, Solid State Technology, (June 1998): p. 63. Figure 20.28
Diversity of Chip Scale Packages 18 General CSP Approach CSP Package Name Company Custom Leadframe Interposer (flexible material with interconnects) between die and substrate Rigid Substrate Area array, bumped CSP Small outline no-lead/c-lead (SON/SOC) Bump chip carrier (BCC) Micro-stud-array (MSA) Bottom leaded plastic (BLP) Quad flat no-lead (QFN) Memory CSP Quad outline non-leaded Enhanced flex CSP FleXBGA FBGA Chip-on-flex CSP Multi chip scale package (MCSP) CSP for memory devices IZM flexpac Molded Ball Grid Array Chip-on-flex Chip Size Package Fine-pitch BGA (FPBGA) MicroBGA Chip Array Package (CABGA) CSP Ceramic mini-bga Molded array process CSP Plastic chip carrier CSP Transformed grid array package Ceramic/plastic fine-pitch BGA Amkor/Anam Fujitsu Fujitsu Hitachi LG Semicon Matsushita TI Japan Toshiba 3M Amkor/Anam Fujitsu GE Hightec MC AG Hitachi Fraunhofer Institute Mitsubishi Electric Motorola Singapore NEC Tessera Amkor/Anam Cypress Semiconductor IBM Motorola National Oki Electric Sony Toshiba Table 20.2
Wafer-Level Packaging Single chip with C4 bumps Figure 20.29
C4 Bumped Wafer Photograph provided courtesy of Advanced Micro Devices Photo 20.4
Design Concept for Wafer-Level Packaging Bonded wire Solder bump Adhesive Chip Redrawn from V. Di Caprio, M. Liebhard, and L. Smith, The Evolution of a New Wafer-level Chip Size Package, Chip Scale Review, (May/June 1999). Figure 20.30
Comparison of Standard Test Flow with Wafer-Level Package Test Flow Standard Test Flow Wafer probe WLP Test Flow WLP fabrication Dice wafer In-situ WLBI Package individual ICs Wafer-level functional test Socket/burn-in at package level Dicing Functional test at package level Wafer-level pick at board assembly Load into tape and reel Figure 20.31
Wafer-Level Packaging Features and Benefits Parameter Package size Mounted package height Component reliability Solder joint reliability Electrical performance Integration with existing SMT infrastructure Alpha-particle protection Low system cost Benefits The package is equal to the chip size in x and y dimensions. It is the smallest possible IC package and minimizes the package weight. It is extremely thin with a total height < 1.0 mm as measured from the circuit board surface after 2 nd level assembly. Test results indicate that wafer-level packaging components pass existing reliability tests for passivated components. Test results indicated solder joint reliability meets standard thermal cycle (-65 to 125 C) reliability tests. Electrical simulation tests indicates that the die face-down (flip chip) configuration of wafer-level packaging with its short circuit traces results in very good electrical performance for minimizing inductance and parasitic capacitance losses. The wafer-level package is compatible with existing surface mount technology and uses standard solder balls and ball pitches. Radioactive elements occurring naturally in packaging materials emit alpha-particles that can cause voltage loss in memory cells. The use of polyimide tape and film adhesive provides alpha-particle protection for memory chips. The use of existing materials with wafer integration to reduce handling and a wafer test strategy to minimize duplicate testing provides for a low overall system cost. Table 20.3