Statement f Wrk (SOW) inemi Bard Assembly TIG PCB Warpage Characterizatin and Minimizatin Prject Versin # 3.1 Date: June 5, 2017 Prject Leader: Srinivasa Aravamudhan (Intel) inemi Staff: Haley Fu Backgrund/Prblem Statement: Custmer demands fr smaller frm factr electrnic devices are driving the use f thinner electrnic cmpnents and thinner printed circuit bard (PCB) in the assembly prcess. The use f thinner cmpnents and thinner multi-up panel PCBs ( 40 mils) has led t PCB warpage issues in the surface munt (SMT) assembly prcess, which in turn impacts the PCB assembly yield. PCBs with excessive warpage impact paste print quality in print prcess and slder jint frmatin during reflw sldering leading t SMT assembly defects. Lack f industry standard fr PCB warpage at reflw temperature further cmpunds the PCB warpage risk t SMT assembly yield. PCB warpage is impacted by three vectrs: PCB fabricatin prcess, PCB design and Bard assembly prcess cnditins. Previus inemi wrk n PCB warpage characterizatin highlighted the impact f PCB fabricatin prcess t warpage and recmmended t evaluate PCB fabricatin prcesses impact t PCB warpage. Additinally, there has been sparse assessment n the impact f PCB design and assembly prcess cnditins impact PCB warpage. This prject addresses the abve-mentined gap and will prvide the slutins t minimize PCB warpage and imprve SMT yield. Scpe f Wrk: The prject will cnsist f designing, building, and evaluating a test vehicle r vehicles t examine the impact f PCB fabricatin prcesses, PCB design factrs and bard assembly prcess cnditins t PCB warpage that fit the defined envelpe set by the wrk grup. This prject will fcus n PCB with thickness at r belw 0.8mm (32mil). The cnclusin f the prject will result in a reprt with guidelines fr PCB designer and PCBA assembly engineers t minimize PCB warpage and imprve SMT yield in assembly. Additinally, webinar detailing the results f the testing will be shared with the inemi members. It is expected the prject will take apprximately 18 mnths t cmplete. The scpe f this prject separated ut int 3 steps and is listed belw. Step 1: PCB fabricatin prcesses. PCB fabricatins prcesses plays a critical rle in mdulating PCB warpage at rm and reflw temperature. Evaluatin will be perfrmed n varius laminatin prcess cnditins, pst prcessing t minimize PCB warpage and the lcatin f the PCB in manufacturing panel. PCB warpage will be characterized fr each f the prcess cnditins steps and will help develp guidelines t minimize PCB warpage. Page 1 f 8
Step 2: PCB design factrs. Evaluatin will be perfrmed n PCB design factr such as cpper balancing acrss PCB layers, utrigger-bard area cpper balancing, utrigger tab size and placement. Optimized PCB fabricatin prcess cnditins will be used t fabricate the PCBs used in Step 2. Step 3: Bard assembly prcess cnditin. Evaluatin will be perfrmed t evaluate the impact f reflw pallet design t PCB warpage. Factrs such as reflw pallet material, reflw pallet supprt mechanism will be evaluated using the test vehicles defined by the team This prject will have checkpints after each step which may cause the variatin f detailed experiment scpe frm the initial plan. The experiment scpe, resurce matrix and schedule will be refined and agreed by the prject members at each checkpint befre mving t the next steps. Purpse f Prject This inemi prject will help t explre the three vectrs (PCB fabricatin prcess, PCB design and Bard assembly prcess cnditins) and develp guidelines fr each f these vectrs which will help t minimize PCB warpage and imprve SMT margin/yield t the benefit f participants. This Prject IS: This Prject IS NOT: Prvide initial analysis f what the Prject IS and IS NOT Evaluatin f PCB warpage n bard with thickness 0.8mm (32mil) Evaluatin f PCB warpage and lcal area f interest (BGA, Shield) Develpment f Industry specificatin fr PCB r lcal area warpage Evaluatin f BGA package warpage Generate guidelines f PCB fabricatin prcesses t minimize PCB warpage Generate guidelines f PCB design factrs t minimize PCB warpage Generate guidelines f reflw pallet design factrs t minimize PCB warpage Previus Related Wrk In 2008-09, inemi a study t evaluate the PCB dynamic cplanarity f several PCB designs frm fur market segments. inemi PCB cplanarity WG helped t establish the test cnditin and metrlgy t quantify PCB warpage at rm and reflw temperature. The study als helped t understand relatinship between rm temperature and reflw temperature warpage and identified PCB fabricatin prcesses as an area fr future evaluatin. Prspective Participants inemi encurages the participatin f individuals frm different disciplines and divisins within their rganizatins t cntribute n the range f tasks utlined in the prject plan. We expect participatin frm PCB fabricatrs, laminate material suppliers, OEMs and EMS/ODMs, wh are cncerned with the PCB warpage impact t bard assembly prcess. NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 2 f 8
Executin Definitin The fllwing cmpanies have participated in the meetings fr develping this prject plan. Wistrn, Micrsft, Takaka Tk, ist, Jabil, Akrmetrix, Dynamic Electrnics, Flex, Intel, Nihn Superir, Celestica, Jabil, Lenv, IBM, Shengyi, Dell, Lenv, TTM, Elmatica and Insidix. Prject Plan Schedule with Milestnes 2017 2018 Q2 Q3 Q4 Q1 Q2 Q3 Segment Steps Task Apr May Jun July Aug Sep Oct Nv Dec Jan Feb Mar Apr May Jun July Aug Sep 0 Prject Initatin Define Scpe Draft preliminary DOE plans Draft and Ratify SOW Finalize Member Sign-up & Resurce cmmitments Finalize Experimental Plans Design Test Vehciles Check Pint #1 Order PCBs 1 Execute PCB fabricatin DOE and Cllect Data Preliminary Reprt frm Step 1 Finalize Experimental Plans Check Pint #2 2 Execute PCB factr DOE and Cllect Data Preliminary Reprt frm Step 2 Finalize Experimental Plans End Pint 3 Execute Reflw pallet factr DOE and Cllect Data Preliminary Reprt frm Step 3 Final Reprt Cmpletin External Publicatin Step 1 Detailed Infrmatin Task 1 Finalize Experimental Plan Get cmmitments frm wrk grup fr each test vehicle design, executin f testing, analysis, and reprt writing. Decide n sample sizes and prvide design attributes fr each f the prpsed test vehicle design. Get cmmitments frm team members n test vehicle attributes (laminate, Panel dimensin, Panel thickness, PCB stack up). Get cmmitments frm fabricatr/s t build test bards. Get cmmitment frm design service fr design f test vehicle/s. Prpsed Experimental Design PCB laminatin prcess (cnditin A, cnditin B, cnditin C). T be finalized based n PCB fabricatrs inputs PCB lcatin within manufacturing panel (center vs. crner) PCB pst prcessing (PCB pre-bake befre shipment t custmers, Yes vs. N) PCB panel dimensin (2 Test Vehicle sizes t envelp industry sizes) PCB thickness (0.8mm and 0.6mm) NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 3 f 8
PCB material (cre and Prepeg material) PCB fabricatrs (supplier A and supplier B) Testing Prcedures Use IPC 9641 High temperature printed bard flatness guidelines t measure PCB & lcal area f interest warpage (i.e., BGA larger than 35mm, shield fence area) at rm temperature and reflw temperatures Resurces Prject participants time t review, amend, agree, and sign up t execute the testing and test vehicle characterizatin defined in the design f experiments Task 2 Design Test Vehicles Prpsed Test Vehicle elements PCB Thickness PCB Size 0.8mm 0.6mm Small t Medium (t be finalized based n team member s inputs) e.g. 100x150mm Medium t large (t be finalized based n team member s inputs) Need t finalize panel size Lcal areas f interest fr warpage measurements BGAs with size 35 mm (Need t finalize n BGA land pattern) ensure FCBGA is used fr evaluatin (Intel t prvide the land pattern and BGA needed fr evaluatin) Shield fence area BGA r CSP packages with pitch 0.4mm and size (X, Y) 15mm Resurces Design resurce t cmpile all test vehicle elements and layut in a test bard frmat Task 3 Order PCB Secure selected materials fr builds. Review design requirements with fabricatrs (Need a minimum f 2 PCB fabricatrs) Fabricatr cnducts builds and prvides fabricatin feedback t wrk grup Fabricatr ships test bards t designated receivers Resurces PCB fabricatrs t supply fabricatin resurces t review, cnduct, and ship the builds Task 4 Execute PCB fabricatin DOE and cllect Data Execute the data cllectin as utlined in the design f experiments. Characterize PCB warpage fr the belw items as per IPC 9641 PCB panel warpage Lcal areas f interest warpage Reprt ut the findings frm the step 1 Design f Experiments Resurces Prject participants time and resurces t execute the testing and test vehicle characterizatin defined in the design f experiments. Cmpany wh sign up fr the test task is suppsed t take care f the test result and analysis NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 4 f 8
Step 2 Detailed Infrmatin Task 1 Finalize Experimental Plan Get cmmitments frm wrk grup fr each test vehicle design, executin f testing, analysis, and reprt writing. Decide n sample sizes and prvide design attributes fr each f the prpsed test vehicle design. Get cmmitments frm team members n test vehicle attributes (laminate, Panel dimensin, Panel thickness, PCB stack up). Get cmmitments frm fabricatr/s t build test bards. Get cmmitment frm design service fr design f test vehicle/s. Prpsed Experimental Design PCB cpper balance acrss layers (cnditin A, cnditin B, cnditin C). T be finalized based n team inputs PCB utrigger t bard area cpper balance (cnditin A, cnditin B, cnditin C). T be finalized based n team inputs PCB panel dimensin (2 Test Vehicle sizes t envelp industry sizes) PCB thickness (0.8mm and 0.6mm) Resurces Prject participants time t review, amend, agree, and sign up t execute the testing and test vehicle characterizatin defined in the design f experiments Testing Prcedures Use IPC IPC 9641 High temperature printed bard flatness guidelines t measure PCB & lcal area f interest warpage (i.e., BGA larger than 35mm, shield fence area) at rm temperature and reflw temperatures Task 2 Execute PCB Design factrs DOE and cllect Data Execute the data cllectin as utlined in the design f experiments. Characterize PCB warpage fr the belw items as per IPC 9641 PCB panel warpage Lcal areas f interest warpage Reprt ut the findings frm the step 2 Design f Experiments Resurces Prject participants time and resurces t execute the testing and test vehicle characterizatin defined in the design f experiments. Cmpany wh sign up fr the test task is suppsed t take care f the test result and analysis Step 3 Detailed Infrmatin Task 1 Finalize Experimental Plan Get cmmitments frm wrk grup fr each test vehicle design, executin f testing, analysis, and reprt writing. Decide n sample sizes and prvide design attributes fr each f the prpsed test vehicle design. Get cmmitments frm team members n test vehicle attributes (laminate, Panel dimensin, Panel thickness, PCB stack up). Get cmmitments frm fabricatr/s t build test bards. NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 5 f 8
Get cmmitment frm design service fr design f test vehicle/s. Prpsed Experimental Design Reflw pallet material Aluminum Cmpsite Reflw pallet supprt cnditin Tp hat N Tp hat (end clamps) PCB panel dimensin (2 Test Vehicle sizes t envelp industry sizes) PCB thickness 0.8mm 0.6mm DOE leg withut reflw pallet t characterize warpage and SMT impact t thin PCB Testing Prcedures Use IPC 9641 High temperature printed bard flatness guidelines t measure PCB & lcal area f interest warpage (i.e., BGA larger than 35mm, shield fence area) at rm temperature and reflw temperatures Resurces Prject participants time t review, amend, agree, and sign up t execute the testing and test vehicle characterizatin defined in the design f experiments Task 2 Execute Reflw pallet design factrs DOE and cllect Data Execute the data cllectin as utlined in the design f experiments. Characterize PCB warpage fr the belw items as per IPC 9641 PCB panel warpage Lcal areas f interest warpage Reprt ut the findings frm the step 3 Design f Experiments Resurces Prject participants time and resurces t execute the testing and test vehicle characterizatin defined in the design f experiments. Cmpany wh sign up fr the test task is suppsed t take care f the test result and analysis Task 3 SMT Assemble t understand impact f reflw pallet design factrs t SMT Yield In additinal t PCB warpage characterizatin, PCBs will be assembled thru SMT prcess agreed by the team members and SMT yield will be characterized fr the abve factrs SMT yield will be measured by Autmated X-ray inspectin and limited destructive analysis (DnP and XS) Resurces Prject participants time and resurces t assemble the test bards defined in the design f experiments and quantify the SMT yield. Cmpany wh sign up fr the test task is suppsed t take care f the test result and analysis NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 6 f 8
Cmpletin Data Analysis and Reprt Writing Test executrs analyze data and review results with wrk grup. Test executrs write up reprt sectins metrlgy and results f testing. Designated wrk grup member/s t write up intrductry sectins and cnclusins fr final reprt. Designated wrk grup member t edit final reprt and review with grup Publish final reprt Prject Mnitring Plans Ensure pen lines f cmmunicatin amng participants. Review all prject requirements with participants befre the prject begins. Prject participants will meet weekly r bi-weekly t review varius aspects f the prject and make plans fr next phases f the prject. Design f experiment and the resurce allcatin will be submitted t inemi Technical Cmmittee fr review t make sure the team have an apprpriate scpe and sufficient resurce cmmitment t accmplish the planned tests. Meeting minutes prvided thrugh e-mail. Fllw-up with individuals n an as-needed basis. Prvide any prject specific mnitring r cmmunicatins plans, e.g., multiple prject meetings t cver multiple regins (EMEA, Asia, and Americas). Wrkshps and face-t-face meetings as determined by the prject team. Prgress reprts will be prvided upn request fr presentatin at regularly scheduled inemi meetings (e.g. a shrt series f PwerPint slides shwing the wrk in prgress at member cuncil meetings). Track and dcument apprximate man-mnths per quarter per team member (this will require the active members f the team t prvide estimates). Track and dcument apprximate number f peple n the prject per quarter (this can be tracked thrugh inemi's WebEx accunt.) Outcme f the Prject Successful cmpletin f this prject will include the publicatin and presentatin in the public dmain f the knwledge acquired frm the activities f this prject n the PCB warpage mitigatin techniques and impact t bard assembly yield. Deliverables f this prject include the fllwing: Webinar and assciated slides fr prject members summarizing the data and cnclusins frm the prject activities n the relevant guidelines t minimize PCB warpage Prject results will be shared with the industry in rder t drive alignment amngst the supply chain and the users. Results will be shared thrugh presentatins at leading industry cnferences and jurnals, subject t grup participant apprval prcess. NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 7 f 8
Resurce Needed Matrix Resurce matrix is included in the prject statement agreement t cllect inputs frm signing prject members. Then resurce allcatin will be reviewed and determined. Area Resurce Needed Participating Cmpany Test Vehicle PCB Test Vehicle layut Small t Medium size (~100 t 150mm in X, Y) PCB Test Vehicle layut Medium t Large size (~200 t 300mm in X, Y) 35mm BGA land pattern/drawing and cmpnent fr assembly 0.4mm pitch BGA land pattern/drawing and cmpnent fr assembly Shield fence area and cmpnent fr assembly Other area f interest/cmpnent t be included in the study PCB Design Resurces PCB Fabricatin Warpage data cllectin PCB design resurces t tape ut 4 bards Small t Med PCB Size, 0.8mm thick Small t Med PCB Size, 0.6mm thick Med t Large PCB Size, 0.8mm thick Med t Large PCB Size, 0.6mm thick Need help frm PCB suppliers (minimum 2) t fabricate the PCBs needed fr this prject Warpage data cllectin (PCB panel & lcal areas f interest) using IPC 9641 fr Step 1 Step 2 Step 3 Bard Assembly Assemble PCB fr warpage evaluatin (Step 3) Reflw Pallet Inspectin & FA (crss-sectin) as needed Design resurces t tape ut reflw pallet designs identified by the team Prcurement f Reflw pallets fr evaluatin Data Analysis Reprt Data analysis t understand the warpage interactin fr Step 1 Step 2 Step 3 Analyze results, write and publish findings t inemi WG NOTE: All changes t SOW must be apprved by the Technical Cmmittee fr versin cntrl Page 8 f 8