Revision History Revision 0.0 (May, 1999) PC133 first published. Revision 0.1 (June, 1999) - Changed PCB Dimensions in PACKAGE DIMENSIONS This datasheet has been downloaded from http://www.digchip.com at this page
KMM366S3323AT SDRAM DIMM 32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung KMM366S3323AT is a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S3323AT consists of sixteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM366S3323AT is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE Performance range Part No. KMM366S3323AT-GA Max Freq. (Speed) 133MHz (7.5ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,375mil), double sided component PIN CONFIGURATIONS (Front side/back side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front DQ8 DQ9 0 1 2 3 4 5 *CB0 *CB1 WE 0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front 1 0 DU A0 A2 A4 A6 A8 A10/AP BA1 CLK0 DU 2 2 3 DU *CB2 *CB3 6 7 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front 8 9 0 *VREF CKE1 1 2 3 4 5 6 7 8 9 0 1 CLK2 WP **SDA **SCL 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 *CB4 *CB5 CAS 4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back 5 1 RAS A1 A3 A5 A7 A9 BA0 A11 CLK1 *A12 CKE0 3 6 7 *A13 *CB6 *CB7 8 9 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back 0 1 2 *VREF 3 4 5 6 7 8 9 0 1 2 3 CLK3 **SA0 **SA1 **SA2 PIN NAMES Name A0 ~ A11 BA0 ~ BA1 ~ 3 CLK0 ~ CLK3 CKE0 ~ CKE1 0 ~ 3 RAS CAS WE 0 ~ 7 *VREF SDA SCL SA0 ~ 2 WP DU Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Write protection Don t use No connection * These pins are not used in this module. ** These pins should be in the system which does not support SPD. SAMSUNG ELECTRONI CO., Ltd. reserves the right to change products and specifications without notice.
PIN CONFIGURATION DESCRIPTION Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CKE A0 ~ A11 BA0 ~ BA1 RAS CAS WE 0 ~ 7 Chip select Clock enable Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Disables or enables device operation by masking or enabling all inputs except CLK, CKE and. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tshz after the clock and masks the output. Blocks data input when active. (Byte masking) ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. WP Write protection WP pin is connected to through 47KΩ Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. / Power supply/ground Power and ground for the input buffers and the core logic.
FUTIONAL BLOCK DIAGRAM 1 0 0 1 DQ8 DQ9 0 1 2 3 4 5 3 2 2 6 7 8 9 0 1 2 3 3 4 5 6 7 8 9 0 1 4 U0 U1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 5 U2 U3 U8 U9 U10 6 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 U4 U5 7 U11 U6 U7 U12 U13 U14 U15 A0 ~ An, BA0 & 1 RAS CAS WE SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 10KΩ SCL Serial PD A0 A1 A2 SA0 SA1 SA2 SDA WP 47KΩ CKE0 SDRAM U0 ~ U7 CKE1 SDRAM U8 ~ U15 Vss DQn 10Ω Two 0.1uF Capacitors per each SDRAM Every DQpin of SDRAM To all SDRAMs CLK0/1/2/3 10Ω U0/U1/U2/U3 U4/U5/U6/U7 U8/U9/U10/U11 U12/U13/U14/U15 3.3
ABSOLUTE MAIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on supply relative to Vss, Q -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 16 W Short circuit current IOS 50 ma Note : Permanent device damage may occur if "ABSOLUTE MAIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTI Recommended operating conditions (Voltage referenced to = 0V, TA = 0 to 70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage, Q 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 Q+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current ILI -10-10 ua 3 Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN Q. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITAE ( = 3.3V, TA = 23 C, f = 1MHz, VREF = 1.4V ± 200 mv) Symbol Min Max Unit Address (A0 ~ A11, BA0 ~ BA1) RAS, CAS, WE CKE (CKE0 ~ CKE1) Clock (CLK0 ~ CLK3) (0, 2) (0 ~ 7) DQ ( ~ 3) CADD CIN CCKE CCLK C C COUT 70 70 45 35 25 15 10 95 95 55 40 30 20 15
DC CHARACTERISTI (Recommended operating condition unless otherwise noted, TA = 0 to 70 C) Parameter Symbol Test Condition Version -A Unit Note Operating current (one Bank Active) ICC1 Burst length =1 trc trc(min) IO = 0 ma 1,200 ma 1 Precharge standby current in power-down mode ICC2P CKE VIL(max), tcc = 10ns 16 ICC2PS CKE & CLK VIL(max), tcc = 16 ma Precharge standby current in non power-down mode ICC2N ICC2NS CKE VIH(min), VIH(min), tcc = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tcc = Input signals are stable 320 112 ma Active standby current in power-down mode ICC3P CKE VIL(max), tcc = 10ns 80 ICC3PS CKE & CLK VIL(max), tcc = 80 ma Active standby current in non power-down mode (One bank active) ICC3N ICC3NS CKE VIH(min), VIH(min), tcc = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tcc = Input signals are stable 480 ma 320 ma Operating current (Burst mode) ICC4 IO = 0 ma Page burst 4Banks activated tccd = 2CLKs 1,440 ma 1 Refresh current ICC5 trc trc(min) 2,000 ma 2 Self refresh current ICC6 CKE 0.2V 24 ma Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=Q/Q).
AC OPERATING TEST CONDITIONS ( = 3.3V ± 0.3V, TA = 0 to 70 C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω Output VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50Ω 870Ω 50 50 (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) (Fig. 2) AC output load circuit Parameter Symbol Version Row active to row active delay trrd(min) 15 ns 1 RAS to CAS delay trcd(min) 20 ns 1 Row precharge time trp(min) 20 ns 1 Row active time Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time -A Unit tras(min) 45 ns 1 tras(max) 100 us Row cycle time trc(min) 65 ns 1 Last data in to row precharge trdl(min) 2 CLK 2 Last data in to Active delay tdal(min) 2 CLK + 20 ns Last data in to new col. address delay tcdl(min) 1 CLK 2 Last data in to burst stop tbdl(min) 1 CLK 2 Col. address to col. address delay tccd(min) 1 CLK 3 Number of valid output data and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. CAS latency=3 2 - - 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Note ea 4
AC CHARACTERISTI (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter Symbol CLK cycle time tcc 7.5 1000 ns 1 CLK to valid tsac 5.4 ns 1,2 Output data toh 2.7 ns 2 CLK high pulse width tch 2.5 ns 3 CLK low pulse width tcl 2.5 ns 3 Input setup time tss 1.5 ns 3 Input hold time tsh 0.8 ns 3 CLK to output in Low-Z tslz 1 ns 2 CLK to output tshz 5.4 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Min -A Max Unit Note
SIMPLIFIED TRUTH TABLE Command CKEn-1 CKEn RAS CAS WE BA0,1 A10/AP A11, A9 ~ A0 Register Mode register set H L L L L OP code 1,2 Refresh Auto refresh Self refresh H 3 H L L L H Entry L 3 Exit L H Note L H H H 3 H 3 Bank active & row addr. H L L H H V Row address Read & column address Write & column address Auto precharge disable L Column 4 H L H L H V address Auto precharge enable H (A0 ~ A9) 4,5 Auto precharge disable L Column 4 H L H L L V address Auto precharge enable H (A0 ~ A9) 4,5 Burst stop H L H H L 6 Precharge Clock suspend or active power down Precharge power down mode Bank selection H L L H L V L All banks H Entry H L H L V V V Exit L H Entry H L Exit L H H L H H H H L V V V H V 7 No operation command H Notes : 1. OP Code : Operand code H L H H H (V=Valid, =Don t care, H=Logic high, L=Logic low) A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 6. Burst stop command is valid at every burst length. 7. sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read latency is 2)
PACKAGE DIMENSIONS Units : Inches (Millimeters) 0.118 (3.000) 5.250 (133.350) 5.014 (127.350) 0.089 (2.26) R 0.079 (R 2.000) 1.375 (34.925) 0.118 (3.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.700 (17.780).118DIA ± 0.004 (3.000DIA ± 0.100) 0.350 (8.890) A B C.450 (11.430) 0.250 (6.350) 1.450 (36.830) 4.550 (115.57) 0.250 (6.350) 2.150 (54.61) 0.100 Min (2.540 Min) 0.150 Max (3.81 Max) 0.200 Min (5.08 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 0.250 (6.350) 0.250 (6.350) 0.100 Min (2.540 Min) 0.039 ± 0.002 (1.000 ± 0.050) Detail A 0.079 ± 0.004 (2.000 ± 0.100) 0.123 ± 0.005 (3.125 ± 0.125) Detail B 0.079 ± 0.004 (2.000 ± 0.100) 0.123 ± 0.005 (3.125 ± 0.125) Detail C 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Tolerances : ±.005(.13) unless otherwise specified The used device is 16Mx8 SDRAM, TSOP SDRAM Part No. : KM48S16030AT