Automotive LPDDR SDRAM

Automotive LPDDR SDRAM MT46H28M6LF 32 Meg x 6 x 4 Banks MT46H64M32LF 6 Meg x 32 x 4 Banks 2Gb: x6, x32 Automotive LPDDR SDRAM Features Features V DD /V DDQ =.7.95V Bidirectional data strobe per byte of data DQS Internal, pipelined double data rate DDR architecture; two data accesses per clock cycle Differential clock inputs and # Commands entered on each positive edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs 4 internal banks for concurrent operation Data masks DM for masking write data; one mask per byte Programmable burst lengths BL: 2, 4, 8, or 6 Concurrent auto precharge option is supported Auto refresh and self refresh modes.8v LVCMOS-compatible inputs Temperature-compensated self refresh TCSR 2 Partial-array self refresh PASR Deep power-down DPD Status read register SRR Selectable output drive strength DS Clock stop capability 64ms refresh; 32ms for the automotive temperature range Options Mark V DD /V DDQ.8V/.8V H Configuration 28 Meg x 6 32 Meg x 6 x 4 banks 28M6 64 Meg x 32 6 Meg x 32 x 4 banks 64M32 Addressing JEDEC-standard LF Plastic "green" package 6-ball VFBGA 8mm x 9mm DD 9-ball VFBGA 8mm x 3mm BQ Timing cycle time 4.8ns @ CL = 3 28 MHz -48 Special Options Automotive package-level burn-in A Operating temperature range From 4 C to +85 C IT From 4 C to +5 C AT Design revision :C Notes:. Contact factory for availability. 2. Self refresh supported up to 85 ºC. Table : Key Timing Parameters CL = 3 Speed Grade Clock Rate Access Time -48 28 MHz 4.8ns Table 2: Configuration Addressing 2Gb Architecture 28 Meg x 6 64 Meg x 32 Configuration 32 Meg x 6 x 4 banks 6 Meg x 32 x 4 banks Refresh count 8K 8K Row addressing 6K A[3:] 6K A[3:] Column addressing 2K A, A[9:] K A[9:] Products and specifications discussed herein are subject to change by Micron without notice.

Features See Package Block Diagrams for descriptions of signal connections and die configurations for each respective architecture. Figure : 2Gb Mobile LPDDR Part Numbering MT 46 H 64M32 LF KQ -6 A IT :C Micron Technology Product Family 46 = Mobile LPDDR Operating Voltage H =.8/.8V HC =.8/.2V Configuration depth, width 28 Meg x 6 64 Meg x 32 28 Meg x 32 256 Meg x 32 Addressing LF = JEDEC-standard addressing L2 = 2-die stack standard addressing L4 = 4-die stack standard addressing Design Revision :C = Design generation Operating Temperature IT = Industrial 4 C to +85 C AT = Automotive 4 C to +5 C WT = Wireless 25 C to +85 C Special Options Multiple processing codes are separated by a space and are listed in hierarchical order. Blank = None A = Automotive Speed Grade -48 = 4.8ns t -5 = 5ns t Package Codes DD = 6-ball 8mm x 9mm VFBGA, green BQ = 9-ball 8mm x 3mm VFBGA, green KQ = 68-ball 2mm x 2mm WFBGA, green LE = 68-ball 2mm x 2mm TFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron s FBGA part marking decoder is available at www.micron.com/decoder. 2

Features Contents Important Notes and Warnings... 8 General Description... 8 Functional Block Diagrams... Ball Assignments... 2 Ball Descriptions... 4 Package Block Diagrams... 6 Package Dimensions... 7 Electrical Specifications... 9 Electrical Specifications I DD Parameters... 22 Electrical Specifications AC Operating Conditions... 28 Output Drive Characteristics... 32 Functional Description... 35 Commands... 36 DESELECT... 37 NO OPERATION... 37 LOAD MODE REGISTER... 37 ACTIVE... 37 READ... 38 WRITE... 39 PRECHARGE... 4 BURST TERMINATE... 4 AUTO REFRESH... 4 SELF REFRESH... 42 DEEP POWER-DOWN... 42 Truth Tables... 43 State Diagram... 48 Initialization... 49 Standard Mode Register... 52 Burst Length... 53 Burst Type... 53 CAS Latency... 54 Operating Mode... 55 Extended Mode Register... 56 Temperature-Compensated Self Refresh... 56 Partial-Array Self Refresh... 57 Output Drive Strength... 57 Status Read Register... 58 Bank/Row Activation... 6 READ Operation... 6 WRITE Operation... 72 PRECHARGE Operation... 84 Auto Precharge... 84 Concurrent Auto Precharge... 84 AUTO REFRESH Operation... 9 SELF REFRESH Operation... 9 Power-Down... 93 Deep Power-Down... 94 Clock Change Frequency... 96 Revision History... 97 Rev. I 5/8... 97 3

Features Rev. H - /7... 97 Rev. G - 2/5... 97 Rev. F - 9/4... 97 Rev. E 7/4... 97 Rev. D 3/4... 97 Rev. C 2/4... 97 Rev. B /4... 97 Rev. B /3... 97 Rev. A 7/3... 97 4

Features List of Figures Figure : 2Gb Mobile LPDDR Part Numbering... 2 Figure 2: Functional Block Diagram x6... Figure 3: Functional Block Diagram x32... Figure 4: 6-Ball VFBGA Top View, x6 only... 2 Figure 5: 9-Ball VFBGA Top View, x32 only... 3 Figure 6: Single Rank, Single Channel Die Package Block Diagram... 6 Figure 7: 6-Ball VFBGA 8mm x 9mm, Package Code: DD... 7 Figure 8: 9-Ball VFBGA 8mm x 3mm, Package Code: BQ... 8 Figure 9: Typical Self Refresh Current vs. Temperature... 27 Figure : ACTIVE Command... 38 Figure : READ Command... 39 Figure 2: WRITE Command... 4 Figure 3: PRECHARGE Command... 4 Figure 4: DEEP POWER-DOWN Command... 42 Figure 5: Simplified State Diagram... 48 Figure 6: Initialize and Load Mode Registers... 5 Figure 7: Alternate Initialization with E LOW... 5 Figure 8: Standard Mode Register Definition... 52 Figure 9: CAS Latency... 55 Figure 2: Extended Mode Register... 56 Figure 2: Status Read Register Timing... 58 Figure 22: Status Register Definition... 59 Figure 23: READ Burst... 62 Figure 24: Consecutive READ Bursts... 63 Figure 25: Nonconsecutive READ Bursts... 64 Figure 26: Random Read Accesses... 65 Figure 27: Terminating a READ Burst... 66 Figure 28: READ-to-WRITE... 67 Figure 29: READ-to-PRECHARGE... 68 Figure 3: Data Output Timing t DQSQ, t QH, and Data Valid Window x6... 69 Figure 3: Data Output Timing t DQSQ, t QH, and Data Valid Window x32... 7 Figure 32: Data Output Timing t AC and t DQS... 7 Figure 33: Data Input Timing... 73 Figure 34: Write DM Operation... 74 Figure 35: WRITE Burst... 75 Figure 36: Consecutive WRITE-to-WRITE... 76 Figure 37: Nonconsecutive WRITE-to-WRITE... 76 Figure 38: Random WRITE Cycles... 77 Figure 39: WRITE-to-READ Uninterrupting... 78 Figure 4: WRITE-to-READ Interrupting... 79 Figure 4: WRITE-to-READ Odd Number of Data, Interrupting... 8 Figure 42: WRITE-to-PRECHARGE Uninterrupting... 8 Figure 43: WRITE-to-PRECHARGE Interrupting... 82 Figure 44: WRITE-to-PRECHARGE Odd Number of Data, Interrupting... 83 Figure 45: Bank Read With Auto Precharge... 86 Figure 46: Bank Read Without Auto Precharge... 87 Figure 47: Bank Write With Auto Precharge... 88 Figure 48: Bank Write Without Auto Precharge... 89 Figure 49: Auto Refresh Mode... 9 Figure 5: Self Refresh Mode... 92 5

Features Figure 5: Power-Down Entry in Active or Precharge Mode... 93 Figure 52: Power-Down Mode Active or Precharge... 94 Figure 53: Deep Power-Down Mode... 95 Figure 54: Clock Stop Mode... 96 6

Features List of Tables Table : Key Timing Parameters CL = 3... Table 2: Configuration Addressing 2Gb... Table 3: Ball Descriptions... 4 Table 4: Absolute Maximum Ratings... 9 Table 5: AC/DC Electrical Characteristics and Operating Conditions... 9 Table 6: Capacitance x6, x32... 2 Table 7: I DD Specifications and Conditions, 4 C to +85 C x6... 22 Table 8: I DD Specifications and Conditions, 4 C to +85 C x32... 23 Table 9: I DD Specifications and Conditions, 4 C to +5 C x6... 24 Table : I DD Specifications and Conditions, 4 C to +5 C x32... 25 Table : I DD 6 Specifications and Conditions... 26 Table 2: Electrical Characteristics and Recommended AC Operating Conditions... 28 Table 3: Target Output Drive Characteristics Full Strength... 32 Table 4: Target Output Drive Characteristics Three-Quarter Strength... 33 Table 5: Target Output Drive Characteristics One-Half Strength... 34 Table 6: Truth Table Commands... 36 Table 7: DM Operation Truth Table... 37 Table 8: Truth Table Current State Bank n Command to Bank n... 43 Table 9: Truth Table Current State Bank n Command to Bank m... 45 Table 2: Truth Table E... 47 Table 2: Burst Definition Table... 53 7

Important Notes and Warnings Micron Technology, Inc. "Micron" reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and 2 require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage "Critical Applications". Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. General Description 2Gb: x6, x32 Automotive LPDDR SDRAM Important Notes and Warnings The 2Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 2,47,483,648 bits. It is internally configured as a quad-bank DRAM. Each of the x6 s 536,87,92-bit banks is organized as 6,384 rows by 248 col- 8

umns by 6 bits. Each of the x32 s 536,87,92-bit banks is organized as 6,384 rows by 24 columns by 32 bits. Note: 2Gb: x6, x32 Automotive LPDDR SDRAM General Description. Throughout this data sheet, various figures and text refer to DQs as DQ. DQ should be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x6 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte DQ[7:], DM refers to LDM and DQS refers to LDQS. For the upper byte DQ[5:8], DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes. For DQ[7:], DM refers to DM and DQS refers to DQS. For DQ[5:8], DM refers to DM and DQS refers to DQS. For DQ[23:6], DM refers to DM2 and DQS refers to DQS2. For DQ[3:24], DM refers to DM3 and DQS refers to DQS3. 2. Complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. Any specific requirement takes precedence over a general statement. 9

Functional Block Diagrams Functional Block Diagrams Figure 2: Functional Block Diagram x6 E # CS# WE# CAS# RAS# Command decode Control logic Refresh counter Bank 3 Bank Bank 2 Standard mode register Extended mode register Rowaddress Mux Bank rowaddress latch and decoder Bank memory array 6 Data Sense amplifiers 32 Read latch 6 MUX 6 DRVRS DQS generator 2 Address BA, BA Address register 2 2 Bank control logic Columnaddress counter/ latch I/O gating DM mask logic Column decoder 32 32 Write FIFO and drivers out in COL Mask Data 4 32 COL 2 2 6 6 Input registers 2 2 6 6 DQS 2 6 2 RCVRS DQ[5:] LDQS, UDQS LDM, UDM

Functional Block Diagrams Figure 3: Functional Block Diagram x32 E # CS# WE# CAS# RAS# Command decode Control logic Refresh counter Bank 3 Bank Bank 2 Standard mode register Extended mode register Rowaddress MUX Bank rowaddress latch and decoder Bank memory array 32 Data Sense amplifiers 64 Read latch 32 MUX 32 DRVRS Address, BA, BA Address register 2 2 Bank control logic Columnaddress counter/ latch I/O gating DM mask logic Column decoder 64 64 Write FIFO and drivers out in COL Mask Data 8 64 COL DQS generator 4 4 32 32 Input registers 4 4 32 32 2 DQS 4 32 4 RCVRS DQ[3:] DQS DQS DQS2 DQS3 DM DM DM2 DM3

Ball Assignments Ball Assignments Figure 4: 6-Ball VFBGA Top View, x6 only 2 3 4 5 6 7 8 9 A V SS DQ5 V SSQ V DDQ DQ V DD B V DDQ DQ3 DQ4 DQ DQ2 V SSQ C V SSQ DQ DQ2 DQ3 DQ4 V DDQ D V DDQ DQ9 DQ DQ5 DQ6 TEST E V SSQ UDQS DQ8 DQ7 LDQS V DDQ F V SS UDM NC A3 LDM V DD G E # WE# CAS# RAS# H A9 A A2 CS# BA BA J A6 A7 A8 A/AP A A K V SS A4 A5 A2 A3 V DD Notes:. D9 is a test pin that must be tied to V SS or V SSQ in normal operations. 2. Unused address pins become RFU. 2

Ball Assignments Figure 5: 9-Ball VFBGA Top View, x32 only 2 3 4 5 6 7 8 9 A V SS DQ3 V SSQ V DDQ DQ6 V DD B V DDQ DQ29 DQ3 DQ7 DQ8 V SSQ C V SSQ DQ27 DQ28 DQ9 DQ2 V DDQ D V DDQ DQ25 DQ26 DQ2 DQ22 TEST E V SSQ DQS3 DQ24 DQ23 DQS2 V DDQ F V DD DM3 NC A3 DM2 V SS G E # WE# CAS# RAS# H A9 A A2 CS# BA BA J A6 A7 A8 A/AP A A K A4 DM A5 A2 DM A3 L V SSQ DQS DQ8 DQ7 DQS V DDQ M V DDQ DQ9 DQ DQ5 DQ6 V SSQ N V SSQ DQ DQ2 DQ3 DQ4 V DDQ P V DDQ DQ3 DQ4 DQ DQ2 V SSQ R V SS DQ5 V SSQ V DDQ DQ V DD Notes:. D9 is a test pin that must be tied to V SS or V SSQ in normal operations. 2. Unused address pins become RFU. 3

Ball Descriptions Table 3: Ball Descriptions Symbol Type Description The ball descriptions table is a comprehensive list of all possible balls for all supported packages. Not all balls listed are supported for a given package., # Input Clock: is the system clock input. and # are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and the negative edge of #. Input and output data is referenced to the crossing of and # both directions of the crossing. E E, E CS# CS#, CS# Input Input Clock enable: E HIGH activates, and E LOW deactivates, the internal clock signals, input buffers, and output drivers. Taking E LOW enables PRECHARGE power-down and SELF REFRESH operations all banks idle, or ACTIVE power-down row active in any bank. E is synchronous for all functions except SELF REFRESH exit. All input buffers except E are disabled during power-down and self refresh modes. E is used for a single LPDDR product. E is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. CS# is used for a single LPDDR product. CS# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. UDM, LDM x6 DM[3:] x32 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. BA, BA Input Bank address inputs: BA and BA define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA and BA also determine which mode register is loaded during a LOAD MODE REGISTER command. A[3:] Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit A for READ or WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA, BA or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE REGISTER command. The maximum address range is dependent upon configuration. Unused address balls become RFU. TEST Input Test pin: Must be tied to V SS or V SSQ in normal operations. DQ[5:] x6 DQ[3:] x32 LDQS, UDQS x6 DQS[3:] x32 Input/ output Input/ output Data input/output: Data bus for x6 and x32. Data strobe: Output with read data, input with write data. DQS is edge-aligned with read data, center-aligned in write data. It is used to capture data. TQ Output Temperature sensor output: TQ HIGH when LPDDR T J exceeds 85 C. V DDQ Supply DQ power supply. 2Gb: x6, x32 Automotive LPDDR SDRAM Ball Descriptions 4

Ball Descriptions Table 3: Ball Descriptions Continued Symbol Type Description V SSQ Supply DQ ground. V DD Supply Power supply. V SS Supply Ground. NC No connect: May be left unconnected. RFU Reserved for future use. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. 5

Package Block Diagrams Package Block Diagrams Figure 6: Single Rank, Single Channel Die Package Block Diagram V DD V DDQ V SS V SSQ CS# E # Address BA, BA DM[3:] LPDDR Die WE# CAS# RAS# DQ[3:] DQS[3:] 6

Package Dimensions Package Dimensions Figure 7: 6-Ball VFBGA 8mm x 9mm, Package Code: DD A. A 6X Ø.45 Dimensions apply to solder balls postreflow on Ø.4 SMD ball pads. 9 8 7 Ball A ID covered by SR 3 2 Ball A ID 9 ±. 7.2 CTR.8 TYP A B C D E F G H J K.8 TYP 6.4 CTR.9 ±..25 MIN 8 ±. Notes:. All dimensions are in millimeters. 2. Solder ball material: SAC35 96.5% Sn, 3% Ag,.5% Cu. 7

Package Dimensions Figure 8: 9-Ball VFBGA 8mm x 3mm, Package Code: BQ Seating plane A. A 9X Ø.45 Dimensions apply to solder balls postreflow on Ø.4 SMD ball pads. 9 8 7 3 2 Ball A ID covered by SR Ball A ID 3 ±..2 CTR A B C D E F G H J K L M N P R.8 TYP.8 TYP.9 ±. 6.4 CTR 8 ±..25 MIN Notes:. All dimensions are in millimeters. 2. Solder ball material: SAC35 96.5% Sn, 3% Ag,.5% Cu. 8

Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 4: Absolute Maximum Ratings Note applies to all parameters in this table Parameter Symbol Min Max Unit V DD /V DDQ supply voltage relative to V SS V DD /V DDQ. 2.4 V Voltage on any pin relative to V SS V IN.5 2.4 or V DDQ +.3V, whichever is less Storage temperature plastic T STG 55 5 C V Note:. V DD and V DDQ must be within 3mV of each other at all times. V DDQ must not exceed V DD. Table 5: AC/DC Electrical Characteristics and Operating Conditions Notes 5 apply to all parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Min Max Unit Notes Supply voltage V DD.7.95 V 6, 7 I/O supply voltage V DDQ.7.95 V 6, 7 Address and command inputs Input voltage high V IH.8 V DDQ V DDQ +.3 V 8, 9 Input voltage low V IL.3.2 V DDQ V 8, 9 Clock inputs, # DC input voltage V IN.3 V DDQ +.3 V DC input differential voltage V IDDC.4 V DDQ V DDQ +.6 V, AC input differential voltage V IDAC.6 V DDQ V DDQ +.6 V, AC differential crossing voltage V IX.4 V DDQ.6 V DDQ V, 2 Data inputs DC input high voltage V IHDC.7 V DDQ V DDQ +.3 V 8, 9, 3 DC input low voltage V ILDC.3.3 V DDQ V 8, 9, 3 AC input high voltage V IHAC.8 V DDQ V DDQ +.3 V 8, 9, 3 AC input low voltage V ILAC.3.2 V DDQ V 8, 9, 3 Data outputs DC output high voltage: Logic I OH =.ma V OH.9 V DDQ V DC output low voltage: Logic I OL =.ma V OL. V DDQ V Leakage current Input leakage current Any input V V IN V DD All other pins not under test = V I I μa 9

Electrical Specifications Table 5: AC/DC Electrical Characteristics and Operating Conditions Continued Notes 5 apply to all parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Min Max Unit Notes Output leakage current DQ are disabled; V V OUT V DDQ Operating temperature I OZ.5.5 μa Commercial T A 7 C Wireless T A 25 85 C Industrial T A 4 85 C Automotive T A 4 5 C Notes:. All voltages referenced to V SS. 2. All parameters assume proper device initialization. 3. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. Outputs measured with equivalent load; transmission line delay is assumed to be very small: I/O 5 5 I/O 2pF pf Full drive strength Half drive strength 5. Timing and I DD tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V DDQ/2 or to the crossing point for /#. The output timing reference voltage level is V DDQ/2. 6. Any positive glitch must be less than one-third of the clock cycle and not more than +2mV or 2.V, whichever is less. Any negative glitch must be less than one-third of the clock cycle and not exceed either 5mV or +.6V, whichever is more positive. 7. V DD and V DDQ must track each other and V DDQ must be less than or equal to V DD. 8. To maintain a valid level, the transitioning edge of the input must: 8a. Sustain a constant slew rate from the current AC level through to the target AC level, V ILAC Or V IHAC. 8b. Reach at least the target AC level. 8c. After the AC target level is reached, continue to maintain at least the target DC level, V ILDC or V IHDC. 9. V IH overshoot: V IHmax = V DDQ +.V for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate. V IL undershoot: V ILmin =.V for a pulse width 3ns and the pulse width cannot be greater than one-third of the cycle rate.. and # input slew rate must be V/ns 2 V/ns if measured differentially.. V ID is the magnitude of the difference between the input level on and the input level on #. 2. The value of V IX is expected to equal V DDQ/2 of the transmitting device and must track variations in the DC level of the same. 3. DQ and DM input slew rates must not deviate from DQS by more than %. 5ps must be added to t DS and t DH for each mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. 2

Electrical Specifications Table 6: Capacitance x6, x32 Notes and 2 apply to all the parameters in this table Parameter Symbol Min Max Unit Notes Input capacitance:, # C. 2. pf Delta input capacitance:, # C D.25 pf 3 Input capacitance: command and address C I. 2. pf Delta input capacitance: command and address C DI.5.5 pf 3 Input/output capacitance: DQ, DQS, DM C IO.25 2.5 pf Delta input/output capacitance: DQ, DQS, DM C DIO.6.6 pf 4 Notes:. This parameter is sampled. V DD /V DDQ =.7.95V, f = MHz, T A = 25 C, V OUTDC = V DDQ /2, V OUT peak-to-peak =.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. This parameter applies to die devices only does not include package capacitance. 3. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 4. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 2

Electrical Specifications I DD Parameters 2Gb: x6, x32 Automotive LPDDR SDRAM Electrical Specifications I DD Parameters Table 7: I DD Specifications and Conditions, 4 C to +85 C x6 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Operating bank active precharge current: t RC = t RC MIN; t = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Auto refresh: Burst refresh; E = HIGH; Address and control inputs are switching; Data bus inputs are stable Symbol Speed -48 Unit Notes I DD 75 ma 6 I DD2P 9 μa 7, 8 I DD2PS 9 μa 7 I DD2N 5 ma 9 I DD2NS 9 ma 9 I DD3P 5 ma 8 I DD3PS 5 ma I DD3N 7 ma 6 I DD3NS 4 ma 6 I DD4R 9 ma 6 I DD4W 9 ma 6 t RFC = 38ns I DD5 7 ma t RFC = t REFI I DD5A 2 ma, Deep power-down current: Address and control balls are stable; Data bus inputs are stable I DD8 μa 7, 3 22

Electrical Specifications I DD Parameters Table 8: I DD Specifications and Conditions, 4 C to +85 C x32 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Operating bank active precharge current: t RC = t RC MIN; t = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Auto refresh: Burst refresh; E = HIGH; Address and control inputs are switching; Data bus inputs are stable Symbol Speed -48 Unit Notes I DD 75 ma 6 I DD2P 9 μa 7, 8 I DD2PS 9 μa 7 I DD2N 5 ma 9 I DD2NS 9 ma 9 I DD3P 5 ma 8 I DD3PS 5 ma I DD3N 7 ma 6 I DD3NS 4 ma 6 I DD4R 9 ma 6 I DD4W 9 ma 6 t RFC = 38ns I DD5 7 ma t RFC = t REFI I DD5A 2 ma, Deep power-down current: Address and control balls are stable; Data bus inputs are stable I DD8 μa 7, 3 23

Electrical Specifications I DD Parameters Table 9: I DD Specifications and Conditions, 4 C to +5 C x6 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Operating bank active precharge current: t RC = t RC MIN; t = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stables Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Auto refresh: Burst refresh; E = HIGH; Address and control inputs are switching; Data bus inputs are stable Symbol Speed -48 Unit Notes I DD ma 6 I DD2P 5 μa 7, 8 I DD2PS 5 μa 7 I DD2N 9 ma 9 I DD2NS 3 ma 9 I DD3P 9 ma 8 I DD3PS 9 ma I DD3N 2 ma 6 I DD3NS 8 ma 6 I DD4R 3 ma 6 I DD4W 3 ma 6 t RFC = 38ns I DD5 7 ma t RFC = t REFI I DD5A 3 ma, Deep power-down current: Address and control balls are stable; Data bus inputs are stable I DD8 5 μa 7, 3 24

Electrical Specifications I DD Parameters Table : I DD Specifications and Conditions, 4 C to +5 C x32 Notes 5 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Operating bank active precharge current: t RC = t RC MIN; t = t MIN; E is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable Precharge power-down standby current: All banks idle; E is LOW; CS is HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge power-down standby current: Clock stopped; All banks idle; E is LOW; CS is HIGH, = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: All banks idle; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Precharge nonpower-down standby current: Clock stopped; All banks idle; E = HIGH; CS = HIGH; = LOW, # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: bank active; E = LOW; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active power-down standby current: Clock stopped; bank active; E = LOW; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: bank active; E = HIGH; CS = HIGH; t = t MIN; Address and control inputs are switching; Data bus inputs are stable Active nonpower-down standby: Clock stopped; bank active; E = HIGH; CS = HIGH; = LOW; # = HIGH; Address and control inputs are switching; Data bus inputs are stable Operating burst read: bank active; BL = 4; CL = 3; t = t MIN; Continuous READ bursts; Iout = ma; Address inputs are switching every 2 clock cycles; 5% data changing each burst Operating burst write: One bank active; BL = 4; t = t MIN; Continuous WRITE bursts; Address inputs are switching; 5% data changing each burst Auto refresh: Burst refresh; E = HIGH; Address and control inputs are switching; Data bus inputs are stable Symbol Speed -48 Unit Notes I DD ma 6 I DD2P 5 μa 7, 8 I DD2PS 5 μa 7 I DD2N 9 ma 9 I DD2NS 3 ma 9 I DD3P 9 ma 8 I DD3PS 9 ma I DD3N 2 ma 6 I DD3NS 8 ma 6 I DD4R 5 ma 6 I DD4W 5 ma 6 t RFC = 38ns I DD5 7 ma t RFC = t REFI I DD5A 3 ma, Deep power-down current: Address and control pins are stable; Data bus inputs are stable I DD8 5 μa 7, 3 25

Electrical Specifications I DD Parameters Table : I DD 6 Specifications and Conditions Notes 5, 7, and 2 apply to all the parameters/conditions in this table; V DD /V DDQ =.7.95V Parameter/Condition Symbol Value Units Self refresh: E = LOW; t = t MIN; Address and control inputs are stable; Data bus inputs are stable Full array, 5 C I DD6 n/a 4 μa Full array, 85 C 2 μa Full array, 45 C 9 μa /2 array, 85 C 45 μa /2 array, 45 C 7 μa /4 array, 85 C 23 μa /4 array, 45 C 6 μa /8 array, 85 C 9 μa /8 array, 45 C 575 μa /6 array, 85 C 2 μa /6 array, 45 C 55 μa Notes:. All voltages referenced to V SS. 2. Tests for I DD characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Timing and I DD tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V DDQ/2 or to the crossing point for /#. The output timing reference voltage level is V DDQ/2. 4. I DD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. 5. I DD specifications are tested after the device is properly initialized and values are averaged at the defined cycle rate. 6. MIN t RC or t RFC for I DD measurements is the smallest multiple of t that meets the minimum absolute value for the respective parameter. t RAS MAX for I DD measurements is the largest multiple of t that meets the maximum absolute value for t RAS. 7. Measurement is taken 5ms after entering into this operating mode to provide settling time for the tester. 8. V DD must not vary more than 4% if E is not active while any bank is active. 9. I DD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level.. E must be active HIGH during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is registered, E must be active at each rising clock edge until t RFC later.. This limit is a nominal value and does not result in a fail. E is HIGH during REFRESH command period t RFC MIN else E is LOW for example, during standby. 2. Values for I DD6 85 C are guaranteed for the entire temperature range. All other I DD6 values are estimated. 3. Typical values at 25 C, not a maximum value. 4. Self refresh is not supported for AT 85 C to 5 C operation. 26

Electrical Specifications I DD Parameters Figure 9: Typical Self Refresh Current vs. Temperature 6 5 4 3 2 Full Array /2 Array /4 Array /8 Array /6 Array Current [µa] 9 8 7 6 5 4 3 2 45 35 25 5 5 5 5 25 35 45 55 65 75 85 Temperature C 27

Electrical Specifications AC Operating Conditions Electrical Specifications AC Operating Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Notes 9 apply to all the parameters in this table; V DD /V DDQ =.7.95V Parameter Symbol -48-5 Min Max Min Max Access window of DQ from /# CL = 3 t AC 2. 5. 2. 5. ns CL = 2 2. 6.5 2. 6.5 Clock cycle time CL = 3 t 4.8 5. ns CL = 2 2 2 high-level width t CH.45.55.45.55 t low-level width t CL.45.55.45.55 t E minimum pulse width high and low t E t Auto precharge write recovery + precharge time DQ and DM input hold time relative to DQS fast slew rate DQ and DM input hold time relative to DQS slow slew rate DQ and DM input setup time relative to DQS fast slew rate DQ and DM input setup time relative to DQS slow slew rate DQ and DM input pulse width for each input Unit Notes t DAL 2 t DH f.48.48 ns 3, 4, 5 t DH s.58.58 ns t DS f.48.48 ns 3, 4, 5 t DS s.58.58 ns t DIPW.8.8 ns 6 Access window of DQS from /# CL = 3 t DQS 2. 5. 2. 5. ns CL = 2 2. 6.5 2. 6.5 ns DQS input high pulse width t DQSH.4.6.4.6 t DQS input low pulse width t DQSL.4.6.4.6 t DQS DQ skew, DQS to last DQ valid, per group, per access WRITE command to first DQS latching transition DQS falling edge from rising hold time DQS falling edge to rising setup time t DQSQ.4.4 ns 3, 7 t DQSS.75.25.75.25 t t DSH.2.2 t t DSS.2.2 t Data valid output window DVW n/a t QH - t DQSQ ns 7 Half-clock period t HP t CH, t CL t CH, t CL ns 8 Data-out High-Z window from /# CL = 3 t HZ 5. 5. ns 9, 2 CL = 2 6.5 6.5 ns Data-out Low-Z window from /# t LZ.. ns 9 28

Electrical Specifications AC Operating Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Continued Notes 9 apply to all the parameters in this table; V DD /V DDQ =.7.95V Parameter Address and control input hold time fast slew rate Address and control input hold time slow slew rate Address and control input setup time fast slew rate Address and control input setup time slow slew rate Symbol -48-5 Min Max Min Max Unit Notes t IH F.9.9 ns 5, 2 t IH S.. ns t IS F.9.9 ns 5, 2 t IS S.. ns Address and control input pulse width t IPW 2.3 2.3 ns 6 LOAD MODE REGISTER command cycle time DQ DQS hold, DQS to first DQ to go nonvalid, per access t MRD 2 2 t t QH t HP - t QHS t HP - t QHS Data hold skew factor t QHS.5.5 ns ns 3, 7 ACTIVE-to-PRECHARGE command t RAS 38.4 7, 4 7, ns 22, 23 ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH command period t RC 52.8 55 ns 23 Active to read or write delay t RCD 4.4 5 ns Refresh period t REF 64 64 ms 29 Average periodic refresh interval: 64Mb, 28Mb, and 256Mb x32 Average periodic refresh interval: 256Mb, 52Mb, Gb, 2Gb AUTO REFRESH command period t REFI 5.6 5.6 μs 29 t REFI 7.8 7.8 μs 29 t RFC 72 72 ns PRECHARGE command period t RP 4.4 5 ns DQS read preamble CL = 3 t RPRE.9..9. t CL = 2 t RPRE.5..5. t DQS read postamble t RPST.4.6.4.6 t Active bank a to active bank b command t RRD 9.6 ns Read of SRR to next valid command t SRC CL + CL + t SRR to read t SRR 2 2 t Internal temperature sensor valid temperature output enable t TQ 2 2 ms DQS write preamble t WPRE.25.25 t DQS write preamble setup time t WPRES ns 24, 25 DQS write postamble t WPST.4.6.4.6 t 26 Write recovery time t WR 4.4 5 ns 27 29

Electrical Specifications AC Operating Conditions Table 2: Electrical Characteristics and Recommended AC Operating Conditions Continued Notes 9 apply to all the parameters in this table; V DD /V DDQ =.7.95V Parameter Internal WRITE-to-READ command delay Exit power-down mode to first valid command Exit self refresh to first valid command Symbol -48-5 Min Max Min Max Unit t WTR 2 2 t t XP 2 2 t Notes t XSR 2.5 ns 28 Notes:. All voltages referenced to V SS. 2. All parameters assume proper device initialization. 3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ranges specified. 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Specifications are correlated to production test conditions generally a coaxial transmission line terminated at the tester electronics. For the half-strength driver with a nominal pf load, parameters t AC and t QH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or other simulation tools for system design validation is suggested. I/O 5 5 I/O 2pF pf Full drive strength Half drive strength 5. The /# input reference voltage level for timing referenced to /# is the point at which and # cross; the input reference voltage level for signals other than /# is V DDQ/2. 6. A and # input slew rate V/ns 2 V/ns if measured differentially is assumed for all parameters. 7. All AC timings assume an input slew rate of V/ns. 8. CAS latency definition: with CL = 2, the first data element is valid at t + t AC after the clock at which the READ command was registered; for CL = 3, the first data element is valid at 2 t + t AC after the first clock at which the READ command was registered. 9. Timing tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V DDQ/2 or to the crossing point for /#. The output timing reference voltage level is V DDQ/2.. Clock frequency change is only permitted during clock stop, power-down, or self refresh mode.. In cases where the device is in self refresh mode for t E, t E starts at the rising edge of the clock and ends when E transitions HIGH. 2. t DAL = t WR/ t + t RP/ t : for each term, if not already an integer, round up to the next highest integer. 3

Electrical Specifications AC Operating Conditions 3. Referenced to each output group: for x6, LDQS with DQ[7:]; and UDQS with DQ[5:8]. For x32, DQS with DQ[7:]; DQS with DQ[5:8]; DQS2 with DQ[23:6]; and DQS3 with DQ[3:24]. 4. DQ and DM input slew rates must not deviate from DQS by more than %. If the DQ/DM/DQS slew rate is less than. V/ns, timing must be derated: 5ps must be added to t DS and t DH for each mv/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, functionality is uncertain. 5. The transition time for input signals CAS#, E, CS#, DM, DQ, DQS, RAS#, WE#, and addresses are measured between V ILDC to V IHAC for rising input signals and V IHDC to V ILAC for falling input signals. 6. These parameters guarantee device timing but are not tested on each device. 7. The valid data window is derived by achieving other specifications: t HP t /2, t DQSQ, and t QH t HP - t QHS. The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is provided a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. 8. t HP MIN is the lesser of t CL MIN and t CH MIN actually applied to the device and # inputs, collectively. 9. t HZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving t HZ or begins driving t LZ. 2. t HZ MAX will prevail over t DQS MAX + t RPST MAX condition. 2. Fast command/address input slew rate V/ns. Slow command/address input slew rate.5 V/ns. If the slew rate is less than.5 V/ns, timing must be derated: t IS has an additional 5ps per each mv/ns reduction in slew rate from the.5 V/ns. t IH has ps added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. 22. READs and WRITEs with auto precharge must not be issued until t RAS MIN can be satisfied prior to the internal PRECHARGE command being issued. 23. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability. 24. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 25. It is recommended that DQS be valid HIGH or LOW on or before the WRITE command. The case shown DQS going from High-Z to logic low applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS. 26. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance bus turnaround will degrade accordingly. 27. At least clock cycle is required during t WR time when in auto precharge mode. 28. Clock must be toggled a minimum of two times during the t XSR period. 29. For the Automotive Temperature parts, t REF = t REF /2 and t REF I = t REF I/2. 3

Output Drive Characteristics Output Drive Characteristics Table 3: Target Output Drive Characteristics Full Strength Notes 2 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current ma Pull-Up Current ma Voltage V Min Max Min Max...... 2.8 8.53 2.8 8.53.2 5.6 26.8 5.6 26.8.3 8.4 32.8 8.4 32.8.4.2 37.5.2 37.5.5 4. 4. 4. 4..6 6.8 42.5 6.8 42.5.7 9.6 44.57 9.6 44.57.8 22.4 46.5 22.4 46.5.85 23.8 47.48 23.8 47.48.9 23.8 48.5 23.8 48.5.95 23.8 49.4 23.8 49.4. 23.8 5.5 23.8 5.5. 23.8 5.35 23.8 5.35.2 23.8 52.65 23.8 52.65.3 23.8 53.95 23.8 53.95.4 23.8 55.25 23.8 55.25.5 23.8 56.55 23.8 56.55.6 23.8 57.85 23.8 57.85.7 23.8 59.5 23.8 59.5.8 6.45 6.45.9 6.75 6.75 Notes:. Based on nominal impedance of 25Ω full strength at V DDQ /2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 32

Output Drive Characteristics Table 4: Target Output Drive Characteristics Three-Quarter Strength Notes 3 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current ma Pull-Up Current ma Voltage V Min Max Min Max.......96 2.97.96 2.97.2 3.92 8.76 3.92 8.76.3 5.88 22.96 5.88 22.96.4 7.84 25.94 7.84 25.94.5 9.8 28. 9.8 28..6.76 29.75.76 29.75.7 3.72 3.2 3.72 3.2.8 5.68 32.55 5.68 32.55.85 6.66 33.24 6.66 33.24.9 6.66 33.95 6.66 33.95.95 6.66 34.58 6.66 34.58. 6.66 35.4 6.66 35.4. 6.66 35.95 6.66 35.95.2 6.66 36.86 6.66 36.86.3 6.66 37.77 6.66 37.77.4 6.66 38.68 6.66 38.68.5 6.66 39.59 6.66 39.59.6 6.66 4.5 6.66 4.5.7 6.66 4.4 6.66 4.4.8 42.32 42.32.9 43.23 43.23 Notes:. Based on nominal impedance of 37Ω three-quarter drive strength at V DDQ /2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3. Contact factory for availability of three-quarter drive strength. 33

Output Drive Characteristics Table 5: Target Output Drive Characteristics One-Half Strength Notes 3 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current ma Pull-Up Current ma Voltage V Min Max Min Max.......27 8.42.27 8.42.2 2.55 2.3 2.55 2.3.3 3.82 4.95 3.82 4.95.4 5.9 6.84 5.9 6.84.5 6.36 8.2 6.36 8.2.6 7.64 9.3 7.64 9.3.7 8.9 2.3 8.9 2.3.8.6 2.2.6 2.2.85.8 2.6.8 2.6.9.8 22..8 22..95.8 22.45.8 22.45..8 22.73.8 22.73..8 23.2.8 23.2.2.8 23.67.8 23.67.3.8 24.4.8 24.4.4.8 24.6.8 24.6.5.8 25.8.8 25.8.6.8 25.54.8 25.54.7.8 26..8 26..8 26.48 26.48.9 26.95 26.95 Notes:. Based on nominal impedance of 55Ω one-half drive strength at V DDQ /2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3. The I-V curve for one-quarter drive strength is approximately 5% of one-half drive strength. 34