Material Engineering for 7nm FinFETs Victor Moroz 2014 Synopsys. All rights reserved. 1 July 10, JTG Semicon West 2014, San Francisco
Outline 2014 Synopsys. All rights reserved. 2
Outline 2014 Synopsys. All rights reserved. 3
Size, nm Evolution of Transistor Scaling 1000 100 Leff L=Node 10 1 L used to be in sync with technology node L quickly accelerated then saturated Will fall behind 2014 Synopsys. All rights reserved. 4
Intel Investor Meeting, Nov. 21, 2013 2014 Synopsys. All rights reserved. 5
2014 Synopsys. All rights reserved. 6
Expected Design Rules Node Gate pitch L Spacer Fin width Fin height Fin pitch Contact size EOT 10 63 20 11 8 32 34 21 0.85 7 44 15 7 6 30 24 15 0.8 2014 Synopsys. All rights reserved. 7 All sizes are in nm
Stress Engineering at 14 nm Node NMOS: Low Stress PMOS: High Stress Junct ion Si Si Main stress source is SiGe PMOS source/drain epitaxy 2014 Synopsys. All rights reserved. 8
Common SRB Epi for NMOS & PMOS Wafer before fin patterning Standard cell row Another cell row Ge SiGeSn channel PMOS NMOS PMOS SiGe SRB SiGe SRB Si wafer Si wafer Considering cell heights (pitches) of 360 nm, it is impractical to have separate SRB s for NMOS and PMOS 2014 Synopsys. All rights reserved. 9
7nm Stress Engineering: SRB + S/D Epi Si channel SiGe channel Ge channel NMOS Si Si 15% Ge 50% Ge 30% Ge Ge +1.5 GPa 25% Ge 50% Ge 75% Ge PMOS -1.5 GPa 70% Ge Si 85% Ge 50% Ge Ge Ge 25% Ge 50% Ge 75% Ge 2014 Synopsys. All rights reserved. 10 Stress analysis in S-Process
Ballistic Ratio Ballistic Transport Evolution 1.0 0.8 0.6 0.90 0.84 0.85 0.77 0.71 0.77 0.70 0.64 0.61 Relaxed 2 GPa Ballistic transport is currently ~64% Is expected to rise to ~84% at 7nm node 0.4 0.53 14nm 0.41 Even higher for Ge and InGaAs 0.2 0.0 10nm 0.32 7nm 5nm technology node 10 100 Channel Length, nm 0.11 0.16 Therefore, ballistic transport approximation is reasonable for 7nm node Si NMOS FinFET with 6nm wide fin 2014 Synopsys. All rights reserved. 11 Calculated in Sentaurus Monte Carlo
Outline 2014 Synopsys. All rights reserved. 12
Drain current, A/um Stress Free SiGe: IdVg Curves Vdd = 0.7 V in this project BTBT model calibrated by IMEC Ge Higher Ge % Si Gate bias, V 2014 Synopsys. All rights reserved. 13 3D analysis in S-Device
Ion, ua/um Strained SiGe: 2 GPa Tensile Stress 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2500 2,429 2000 1,900 2,003 1,902 HP: 100 na/um (Servers) 1500 1,233 1,310 1,054 1000 970 722 638 500 0 SP: 1 na/um (Laptops) LP: 50 pa/um (Mobile) Germanium mole fraction 2014 Synopsys. All rights reserved. 14 7nm NMOS FinFET
Ion, ua/um Strained SiGe: 2 GPa Tensile Stress SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 3000 2500 Flat Dip 2,429 Best 2000 1,900 2,003 1,902 HP: 100 na/um 1500 1,233 1,310 1000 722 638 500 970 Gone 1,054 SP: 1 na/um LP: 50 pa/um 0 Germanium mole fraction 2014 Synopsys. All rights reserved. 15 7nm NMOS FinFET
Inversion charge, 1/cm2 Injection velocityj, cm/s Strained SiGe: N inv and V inj 1.2E+13 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 3.E+07 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 1.0E+13 8.0E+12 2.E+07 6.0E+12 4.0E+12 1.E+07 2.0E+12 0.0E+00 Germanium mole fraction 0.E+00 Germanium mole fraction 2014 Synopsys. All rights reserved. 16 7nm NMOS FinFET
Valley occupancy % Ninv (1/cm2) Delta & Lambda Valley Population 100% 2.0E+12 80% X 1.5E+12 Absolute 60% Relative 1.0E+12 X L 40% 20% L 5.0E+11 0% 0.0E+00 Germanium mole fraction Germanium mole fraction Here, Vgs = 0.7 V and gate WF is adjusted to have min Ioff at Vgs = 0 There are too few electrons at 80% to 90% Ge mole fractions 2014 Synopsys. All rights reserved. 17 S-Band
Ion, ua/um Strained SiGe: LP, SP & HP Champions 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2500 2000 1,900 2,003 1,902 2,429 HP: Ge 1500 1,233 1,310 1000 722 638 500 970 1,054 SP: Mid-range SiGe LP: Si 0 Germanium mole fraction 2014 Synopsys. All rights reserved. 18 7nm NMOS FinFET
Ion, ua/um Strained SiGe: Combination Champion 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2,429 2500 2,003 1,900 1,902 2000 1500 1,233 1,310 1,054 1000 970 722 638 500 0 Germanium mole fraction Better NMOS s Only Si and SiGe with low Ge % can match LP spec HP performance penalty to pure Ge is ~20% The choice between pure Si vs SiGe with low Ge % can be made based on PMOS/NMOS stress trade-off Better PMOS s 2014 Synopsys. All rights reserved. 19 7nm NMOS FinFET
Outline 2014 Synopsys. All rights reserved. 20
IdVg After Work-Function Adjustment BTBT InAs BTBT model calibrated by IMEC Vdd = 0.7 V GaAs 2014 Synopsys. All rights reserved. 21 3D analysis in S-Device
Leakage Patterns InAs BTBT is spread along junction GaAs GIDL happens at the fin top 2014 Synopsys. All rights reserved. 22 Vgs = -0.3 V
Bandgap, ev stress Bandgap, ev confinement confinement Band Gap Widening and Narrowing 1.2 1.8 1.1 SiGe 1.6 1.4 InGaAs 1.0 1.2 0.9 1.0 0.8 0.8 0.6 0.7 Bulk Strained narrow fin Stress-free narrow fin 0.4 0.2 Bulk Narrow fin 0.6 0.0 Germanium mole fraction Gallium mole fraction For SiGe, 6nm wide fin widens bandgap by 40 mv to 50 mv Tensile uniaxial 2 GPa stress pushes it down by 70 mv to 100 mv For GaAs, the widening is 155 mv, and for InAs it grows to 340 mv 2014 Synopsys. All rights reserved. 23 7nm NMOS FinFET
Bandgap, ev stress Bandgap, ev confinement confinement Band Gap Widening and Narrowing 1.2 1.8 LP Ioff spec 1.1 SiGe 1.6 1.4 InGaAs 1.0 1.2 0.9 1.0 0.8 0.8 0.6 0.7 Bulk Strained narrow fin Stress-free narrow fin 0.4 0.2 Bulk Narrow fin 0.6 0.0 Germanium mole fraction Gallium mole fraction High mobility materials need to have bandgap wider than silicon! 2014 Synopsys. All rights reserved. 24 7nm NMOS FinFET
Valley occupancy % Valley occupancy % Gamma, Delta & Lambda Valleys 100% 80% X 100% 80% G 60% 40% SiGe 60% 40% InGaAs 20% L 20% L 0% Germanium mole fraction 0% Gallium mole fraction 2014 Synopsys. All rights reserved. 25 7nm NMOS FinFET
Inversion charge, 1/cm2 Injection velocityj, cm/s Group IV vs III-V: N inv and V inj InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 1.2E+13 6.E+07 1.0E+13 5.E+07 8.0E+12 4.E+07 6.0E+12 3.E+07 4.0E+12 2.E+07 2.0E+12 1.E+07 0.0E+00 0.E+00 Mole fraction (Germanium or Gallium) Mole fraction (Germanium or Gallium) 2014 Synopsys. All rights reserved. 26 7nm NMOS FinFET
Ion, ua/um Group IV vs III-V 3000 2500 InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2,612 2,589 2,449 2,429 2000 1,900 2,003 1,977 1,902 1500 1,233 1,310 1000 722 638 500 970 1,054 601 754 0 Mole fraction (Germanium or Gallium) 199 2014 Synopsys. All rights reserved. 27 7nm NMOS FinFET
Ion, ua/um Group IV vs III-V: LP, SP & HP Champions InGaAs LP InGaAs SP InGaAs HP 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2500 2000 1,900 2,449 2,612 2,589 2,003 1,977 1,902 2,429 HP: Mid-range InGaAs 1500 SP: 30% In InGaAs 1,233 1,310 1000 722 638 500 970 1,054 601 754 LP: Si 0 Mole fraction (Germanium or Gallium) 199 2014 Synopsys. All rights reserved. 28 7nm NMOS FinFET
Ion, ua/um Group IV vs III-V: Combination Champion 3000 2500 2000 1500 InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2,612 2,589 2,449 2,429 2,003 1,900 1,902 1,977 Only Si, low Ge SiGe, and GaAs can match LP spec InGaAs with 10% In has competitive performance, but is too sensitive to In content 1,233 1,310 1,054 1000 970 722 638 601 500 0 Mole fraction (Germanium or Gallium) 754 199 This would bring severe variability So, silicon looks the best SiGe with low Ge % can be used for stress engineering 2014 Synopsys. All rights reserved. 29 7nm NMOS FinFET
Ion, ua/um 0.5 V Vdd Instead of 0.7 V Vdd InGaAs LP InGaAs SP InGaAs HP 2000 1800 1600 1400 1200 1000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 1,962 1,547 1,651 1,510 1,239 1,131 1,082 1,211 1,090 1,064 InGaAs with 30% In really shines at SP and HP specs Nobody can pull off LP at 0.5 V Vdd. Would you like your iphone to be ~30x slower? 800 600 400 200 0 689 694 331 364 239 112 30 27 Mole fraction (Germanium or Gallium) To have 0.5 V Vdd, variability has to go down ~2x. That is a stretch. The best InGaAs composition has Silike bandgap 2014 Synopsys. All rights reserved. 30 7nm NMOS FinFET
Summary It is a close race, no clear winner The best choice depends on particular chip spec 2014 Synopsys. All rights reserved. 31 7nm NMOS FinFET