2048MB DDR2 SDRAM SO-DIMM

Transcription

1 248MB R2 SRAM S-IMM 248MB R2 SRAM S-IMM based 28Mx8, 8Banks,.8V R2 SRAM with SP Features Performance range (Bandwidth 6.4GB/sec) Part No. 78.A2G86.45 Max Freq. (lock) Speed Grade 8 Mbps Jstandard.8V ±.V Power Supply VQ =.8V±.V Internal Bank: 8 Bank Posted AS Programmable AS Latency: 4, 5, 6 Programmable Additive Latency:,, 2, 3 and 4 Write Latency(WL) = Read Latency(RL) - Burst Length: 4, 8(Interleave/nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional ifferential ata-strobe (Single-ended data-strobe is an optional feature) ff-hip river() Impedance Adjustment n ie ermination Refresh and Self Refresh Average Refesh Period 7.8us Serial presence detect with PRM ompliance with RoHS ompliance with perating emperature Range: ommercial 85 Refresh: auto-refresh, self-refresh Average refresh period 7.8us at us at escription his module is256m x 64 bit ouble ata Rate SRAM high density memory modules based on first generation of 248MB R2 SRAM respectively. It consists of sixteen MS 28M x 8bit with 8banks ouble ata Rate SRAMs in 6Ball FBGA packages mounted on a 2pin glass-epoxy substrate. hree.uf decoupling capacitors are mounted on the printed circuit board in parallel for each R2 SRAM. Synchronous design allows precise cycle control with the use of system clock. ata I/ transactions are possible on both edges of. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

2 Pin onfigurations (Front side/back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back V RF 2 V SS A 2 A 5 Q42 52 Q46 3 V SS 4 Q4 53 V SS 54 V SS 3 V 4 V 53 Q43 54 Q47 5 Q 6 Q5 55 Q8 56 Q22 5 A/AP 6 BA 55 V SS 56 V SS 7 Q 8 V SS 57 Q9 58 Q23 7 BA 8 RAS 57 Q48 58 Q52 9 V SS 59 V SS 6 V SS 9 W S 59 Q49 6 Q53 2 V SS 6 Q24 62 Q28 V 2 V 6 V SS 62 V SS 3 4 Q6 63 Q25 64 Q29 3 AS 4 63 N, S 64 5 V SS 6 Q7 65 V SS 66 V SS 5 N/S 6 A3 65 V SS 66 7 Q2 8 V SS V 8 V V SS 9 Q3 2 Q2 69 N N/ 2 N V SS 22 Q3 7 V SS 72 V SS 2 V SS 22 V SS 7 V SS 72 V SS 23 Q8 24 V SS 73 Q26 74 Q3 23 Q32 24 Q36 73 Q5 74 Q54 25 Q Q27 76 Q3 25 Q33 26 Q37 75 Q5 76 Q55 27 V SS 28 V SS 77 V SS 78 V SS 27 V SS 28 V SS 77 V SS 78 V SS N/ Q56 8 Q V 82 V V SS 8 Q57 82 Q6 33 V SS 34 V SS 83 N 84 N 33 V SS 34 Q38 83 V SS 84 V SS 35 Q 36 Q4 85 BA2 86 N 35 Q34 36 Q Q 38 Q5 87 V 88 V 37 Q35 38 V SS 87 V SS V SS 4 V SS 89 A2 9 A 39 V SS 4 Q44 89 Q58 9 V SS 4 V SS 42 V SS 9 A9 92 A7 4 Q4 42 Q45 9 Q59 92 Q62 43 Q6 44 Q2 93 A8 94 A6 43 Q4 44 V SS 93 V SS 94 Q63 45 Q7 46 Q2 95 V 96 V 45 V SS SA 96 V SS 47 V SS 48 V SS 97 A5 98 A SL 98 SA N 99 A3 A2 49 V SS 5 V SS 99 V SP 2 SA Pin escription Pin Name Function Pin Name Function, lock s, positive line SA SP ata /utput, lock s, negative line SA,SA SP address, lock nables Q~Q63 ata /utput RAS Row Address Strobe ~7 ata Masks AS olumn Address Strobe ~7 ata strobes W Write nable ~7 ata strobes complement S,S hip Selects S Logic Analyzer specific test pin (No connect on So-IMM) A~A9, A~A3 Address s V ore and I/ Power A/AP Address /Autoprecharge V SS Ground BA~BA2 SRAM Bank Address V RF /utput Reference, n-die termination control V SP SP Power SL Serial Presence etect(sp) lock N Spare pins, No connect

3 /utput Functional escription Symbol ype Function S-S RAS, AS, W he system clock inputs. All address and command lines are sampled on the cross point of the rising edge of and falling edge of. A elay Locked Loop (LL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock. Activates the R2 SRAM signal when high and deactivates the signal when low, By deactivating the clocks, low initiates the Power own mode or the Self Refesh mode. nables the associated R2 SRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank is selected by S, Rank is selected by S. Ranks are also called Physical banks. When sampled at the cross point of the rising edge of and falling edge of, AS, RAS, and W define the operation to be executed by the SRAM. BA~BA2 Selects which R2 SRAM internal bank is activated. ~ A~A9, A/AP, A~A3 Asserts on-die termination for Q,,, and signals if enabled via the R2 SRAM xtended Mode Register Set (MRS). uring a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of and falling edge of. uring a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of and falling edge of. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. uring a Precharge command cycle, AP is used in conjunction with BA-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA-BAn inputs. If AP is low, then BA-BAn are used to define which bank to precharge. Q~Q63 In/ut ata /utput pins. ~7 ~7 ~7 In/ut he data write masks, associated with one data byte. In Write mode, operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, lines have no effect. he data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the R2 SRAMs and is sent at the leading edge of the data window. signals are complements, and timing is relative to the crosspoint of respective and If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to VSS and R2 SRAM mode registers programmed appropriately. V,V SP,V SS Supply Power supplies for core, I/, Serial Presence etect, and ground for the module. SA SL In/ut his is a bidirectional pin used to transfer data into or out of the SP PRM. A resistor must be connected to V to act as a pull up. his signal is used to clock data into and out of the SP PRM. A resistor may be connected from SL to V to act as a pull up. SA~SA Address pins used to select the Serial Presence etect base address. S In/ut he S pin is reserved for bus analysis tools and is not connected on normal memory modules(s- IMMs).

4 FUNINAL BL IAGRAM + 5% S S Q Q Q2 Q3 Q4 Q5 Q6 Q7 I/ I/ S I/ I/ S S Q32 I/ I/ Q33 Q34 Q35 Q36 Q37 Q38 Q39 I/ 4 I/ S 2 Q8 Q9 Q Q Q2 Q3 Q4 Q5 I/ I/ S I/ I/ S Q4 Q4 Q42 Q43 Q44 Q45 Q46 Q47 I/ I/ S 5 I/ I/ S Q6 Q7 Q8 Q9 Q2 Q2 Q22 Q23 I/ I/ S 2 I/ I/ S Q48 Q49 Q5 Q5 Q52 Q53 Q54 Q55 I/ I/ S 6 I/ I/ S Q24 Q25 Q26 Q27 Q28 Q29 Q3 Q3 I/ I/ S 3 I/ I/ S Q56 Q57 Q58 Q59 Q6 Q6 Q62 Q63 I/ I/ S 7 I/ I/ S 5 BA - BA2 A - A3 RAS AS W + 5% R2 SRAMs - 5 R2 SRAMs - 5 R2 SRAMs - 5 R2 SRAMs - 5 R2 SRAMs - 5 SL SA SA SL A A A2 SP WP SA * lock Wiring lock R2 SRAMs */ */ 8 R2 SRAMs 8 R2 SRAMs * Wire per lock Loading able/wiring iagrams V SP V RF V Serial P R2 SRAMs - 5 R2 SRAMs - 5, V and V Q Notes :. Q,, / resistors : 22 hms 5%. 2. BAx, Ax, RAS, AS, W resistors : 3. hms 5%. V SS R2 SRAMs - 5, SP

5 PAAG IMNSINS 67.6 mm SP mm max 6. a b " mm max 2 a mm AIL a AIL b FRN SI r"..5 r". BA SI 4. r".. r".5.2 " r".. r".5.8 r" r" r".3 olerances:+-.5mm unless otherwise specified

6 Mouser lectronics Authorized istributor lick to View Pricing, Inventory, elivery & Lifecycle Information: Apacer: 78.A2G86.45