Development and validation of design rules to improve integrated circuit immunity before manufacturing

Transcription

1 Development and validation of design rules to improve integrated circuit immunity before manufacturing PhD Seminar - 17/11/2009 Mikael DEOBARRO (PhD-2) mikael.deobarro@freescale.com Freescale Semiconductor 134 avenue du général Eisenhower TOULOUSE PLAN I. Thesis status II. Presentation of the subject IV. Publications V. Perspectives 1

2 I. Thesis status CIFRE thesis made in partnership with the LATTIS laboratory (INSA) (December December 2010) PhD advisors: Bertrand VRIGNON (Freescale) Sonia BEN DHIA (LATTIS INSA Toulouse) Industrial need: Develop simulation tools to predict immunity thresholds of integrated circuit from design level to PCB level Key words: Modeling, immunity, integrated circuits, EMC, BCI/ DPI, design flow, on-chip sensor 2 II. Presentation of the subject Issue: Lack of information about disturbance propagation through an integrated circuit? Industrial need: Perturbation RF Most of the time, EMC measurements are performed once the equipment is made Designers want to predict EMC before manufacturing Reduction of costs 3

3 II. Presentation of the subject My approach: 1. Immunity tests modeling : from injection paths (BCI & DPI) to the vehicle test internal blocks Specifications Circuit design Design rules EMC simulations NO VALID? OK Circuit manufacturing Model Extraction NO EMC tests VALID? Component manufacturer OK 2. Validate the entire model by ICs internal measurements with on-chip sensor 3. Develop and validate simulation tools (simulation flow) System design EMC simulations VALID? NO OK System manufacturing System manufacturer 4 Modeling of the injection path (DPI & BCI tests) 3 models (discrete, N-port, polynomial) were developed and compared for each susceptibility test 5

4 Evaluation of conducted RF disturbances propagated inside a test vehicle (test chip) by using on-chip sampling sensor DC & AC characterization of the on-chip sensor Signal Synthesizer Power meter P INC P refl RFI Probability V density (on-chip meas.) sensor Develop a Labview code to acquire signal randomly (without synchronization) Amplifier Directional coupler Oscilloscope (off-chip meas.) DPI Capacitor Decoupling network I/O ESD Chip under test Test the I/Os power rail immunity (DPI tests: IEC ) with different input signal (DC signal: 0 & 5 V and square signal 0-5 V) Show limits of DPI tests 6 Modeling of the test vehicle EMC Test board (PCB) Z & S matrix extraction from geometry datas of PCB Test chip: 2 nd step = PDN Power Distribution Network impedance deduced from S parameters measurements Test chip: 1 st step = Package Use of ICEMC software from package dimensions Test chip: 3 rd = Internal structure of I/Os Physical extraction of ESD protections structures from TLP measurements & deduction of IBIS files 7

5 IV. Publications (2009) Topical session Subject: Comparison of Bulk Current Injection models Poster Subject: Modeling of conducted disturbance injection to develop a simulation flow in Integrated Circuit design stage Oral session Subject: Use of on-chip sampling sensor to evaluate conducted RF disturbances propagated inside an integrated circuit 8 Perspectives I/Os modeling of the test vehicle (2 models developed & compared) Paper APEMC Correlation of BCI & DPI tests (development of a Matlab code) & develop the EMC simulation flow Publication for electronic letters Use of the simulation flow to model a FSL component ( on-chip sensor, correlation measurements/ simulations of DPI & BCI tests) Paper submission for IEEE transactions on EMC or Paper EMC IEEE symposium (Florida) Thesis report 9

6 Thank you for your attention 10