Port A. Slew rate gate drive logic level shift GND. Fig. 1 - Typical Application Circuit
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1 6.5 m, Bidirctional Battry Switch in Compact WCSP DESCRIPTION Th bidirctional switch fatur rvrs blocking capability to isolat th battry from th systm. Th intrnal switch has an ultra low 6.5 m (typ. at 3.3 V) on-rsistanc and oprats from a +2.3 V to +5.5 V input voltag rang, making th dvics idal battry-disconnct switchs for high capacity battry applications. Th has slw rat control, making it idal in larg load capacitor as wll as high currnt load switching applications. This dvic is also highly fficint, consuming only 110 na (typ.) currnt in shutdown and whil oprating. Th has an activ low nabl. It can intrfac dirctly with a low voltag control signal. Th is availabl in an ultra compact 12-bump, 1.3 mm x 1.7 mm, 0.4 mm pitch WCSP packag with top sid lamination. Th dvic oprats ovr th tmpratur of -40 C to +85 C. FEATURES Bidirctional on and off 7 A continuous currnt capability Ultra low R on, 6.5 m (typ.) at 3.3 V Wid input voltag, 2.3 V to 5.5 V Slw rat controlld turn on Low quiscnt currnt: 110 na EN pin with intgratd pull up or pull down rsistor Compact 12-bump, 1.3 mm x 1.7 mm x 0.55 mm WCSP packag Matrial catgorization: for dfinitions of complianc plas s APPLICATIONS Smartphons and tablts Digital still / vido camras Portabl mtrs and tst instrumnts Communication dvics with mbddd battris Portabl mdical and halthcar systms Data storag Battry bank TYPICAL APPLICATION CIRCUIT Systm connctor powr input Charging control and rgulator Systm charging block EN Slw rat gat driv logic lvl shift Systm Powr Input Chargr output To battry pack GND Fig. 1 - Typical Application Circuit ORDERING INFORMATION PART NUMBER MARKING ENABLE ENABLE PULL RESISTOR PACKAGE TEMPERATURE DB-T1-GE A Low Enabl pull Low 12-bump, 1.3 mm x 1.7 mm, 0.4 mm pitch -40 C to +85 C WCSP packag EVB Evaluation board - Not GE1 dnots halogn-fr and RoHS-compliant MARKING A B C FYWL 32101A S Rv. A, 03-Apr-17 1 Documnt Numbr: 78628
2 ABSOLUTE MAXIMUM RATINGS PARAMETER CONDITIONS LIMIT UNIT Rfrnc to GND -0.3 to +6 V PA, V PB Puls at 1 ms rfrnc to GND a -1.6 V V EN Rfrnc to GND -0.3 to +6 Maximum continuous switch currnt 7 Maximum puls currnt 100 μs puls 15 A ESD (HBM) 8000 V Oprating tmpratur -40 to +85 Oprating junction tmpratur 125 C Storag tmpratur -65 to +150 Thrmal rsistanc ( JA ) b 73 C/W Powr dissipation (P D ) b, c T A = 70 C 1096 mw Nots a. Ngativ currnt injction up to 300 ma b. All bumps soldrd to 1" x 1", 2 oz. coppr, 4 layrs PC board c. Drat 13.7 mw/ C abov T A = 70 C Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of th spcifications is not implid. Exposur to absolut maximum rating/conditions for xtndd priods may affct dvic rliability. SPECIFICATIONS TEST CONDITIONS UNLESS SPECIFIED LIMITS PARAMETER SYMBOL V IN = V PA /V PB = 2.3 V to 5.5 V, T A = -40 C to 85 C (Typical valus ar at V PA, V PB = 4.2 V, MIN. a TYP. b MAX. a UNIT C PA, C PB = 0.1 μf, T A = 25 C) Powr Supply Oprating voltag c V PA/PB V Quiscnt currnt I Q V EN = 0 V, no load na Shutdown currnt I SHDN V EN = V IN, no load na Intrnal FET V PA /V PB = 2.3 V, I L = 500 ma, T A = 25 C On-rsistanc R DS(on) V PA /V PB = 3.3 V, I L = 500 ma, T A = 25 C m Control EN input logic-low voltag c V IL EN input logic-high voltag c V IH V EN input logic hystrsis V I(HYS) - > mv EN pull rsistor R EN V PA /V PB = 5.5 V, V EN (or V EN ) = 2.3 V k Timing Output turn-on dlay tim t d(on) Output turn-on ris tim t r V IN = 4.2 V, R L = 100, C L = 0.1 μf, T A = 25 C Output turn-off dlay tim t d(off) ms Output turn-off fall tim t f Nots a. Th algbraic convntion whrby th most ngativ valu is a minimum and th most positiv a maximum b. Typical valus ar for DESIGN AID ONLY, not guarantd nor subjct to production tsting c. For V IN outsid this rang consult typical EN, EN thrshold curv S Rv. A, 03-Apr-17 2 Documnt Numbr: 78628
3 BUMP CONFIGURATION A A1 A2 A3 A4 /EN B B1 B2 B3 B4 C C1 C2 C3 C4 GND Top viw (soldr bumps on bottom) Fig. 2 - WCSP12, 1.3 mm x 1.7 mm BUMP DESCRIPTION BUMP NUMBER NAME FUNCTION A1, B1, A3, B3, C3 PB Powr port B C1 GND Ground A2, B2, C2, B4, C4 PA Powr port A A4 EN Switch nabl input, activ low FUNCTIONAL BLOCK DIAGRAM Intrnal bias circuit EN, Slw rat gat driv logic lvl shift TYPICAL CHARACTERISTICS (intrnally rgulatd 25 C, unlss othrwis notd) I QPA/PB - Quiscnt Currnt (na) V PA/PB (V) GND V PA/PB (V) Fig. 3 - Quiscnt vs. Input Voltag Fig. 4 - Shutdown Currnt vs. Input Voltag I SHDN-PA/PB - Shutdown Currnt (na) S Rv. A, 03-Apr-17 3 Documnt Numbr: 78628
4 TYPICAL CHARACTERISTICS (intrnally rgulatd 25 C, unlss othrwis notd) I QPA/PB - Quiscnt Currnt (na) V PA/PB = 5.0 V V PA/PB = 2.7 V R DS - On-Rsistanc (mω) I L = 0.5 A 80 Fig. 5 - Quiscnt vs. Tmpratur V PA /V PB (V) Fig. 8 - On Rsistanc vs. Input Voltag I L = 0.5 A V PA /V PB = 4.2 V 580 V EN = 2.3 V V PA/PB = 5.5 V R DS - On-Rsistanc (mω) R EN - EN Pulldown Rsistanc (k Ω) Fig. 6 - On Rsistanc vs. Tmpratur Fig. 9 - EN Pull Down Rsistanc vs. Tmpratur T A = 25 C V PA /V PB = 2.7 V I SHDN-PA/PB - Shutdown Currnt (na) V PA/PB = 5.0 V V PA/PB = 2.7 V R DS(norm) - Normalizd On -Rsistanc V PA /V PB = 3.3 V V PA /V PB = 4.35 V V PA /V PB = 5 V 80 Fig. 7 - Shutdown Currnt vs.tmpratur I OUT (A) Fig Normalizd On Rsistanc vs. Load Currnt S Rv. A, 03-Apr-17 4 Documnt Numbr: 78628
5 TYPICAL CHARACTERISTICS (intrnally rgulatd 25 C, unlss othrwis notd) C L = 0.1 μf I PB/PA - Input Currnt (na) V PB/PA = 2.3 V t d(on) - Turn-On Dlay Tim (ms) V PA/PB (V) Fig Rvrs Blocking Currnt (I RB ) vs. Output Voltag 0.5 Fig Turn-on Dlay Tim vs. Tmpratur t r -Ris Tim (ms) C L = 0.1 μf R L = 10 Ω t d(off) - Turn-Off Dlay Tim (ms) C L = 0.1 μf R L = 10 Ω 1.00 Fig Ris Tim vs. Tmpratur Fig Turn-off Dlay Tim vs. Tmpratur EN Thrshold Voltag (V) V IH V IL t f -Fall Tim (ms) C L = 0.1 μf R L = 10 Ω V PA/PB (V) Fig EN Thrshold Voltag vs. Input Voltag Fig Fall Tim vs. Tmpratur S Rv. A, 03-Apr-17 5 Documnt Numbr: 78628
6 DETAILED DESCRIPTION Th bidirctional switch faturs rvrs blocking capability to isolat th battry from th systm. Th intrnal switch has an ultra low 6.5 m (typ. at 3.3 V) on-rsistanc and oprats from a +2.3 V to +5.5 V input voltag rang, making th dvic idal battry disconnct-switch for high capacity battry applications. Th parts can handl 7 A continuous currnt at both dirctions. Th has slw rat control, making it idal in larg load capacitor as wll as high currnt load switching applications. Th is availabl in an ultra compact 12-bump, 1.3 mm x 1.7 mm, 0.4 mm pitch WCSP packag with top sid lamination. Th dvic oprats ovr th tmpratur of -40 C to +85 C. REVERSE CURRENT BLOCKING Th is a bidirctional switch that prvnt currnt flowing from ithr port to th othr whn th dvic is disabld. EN INPUT has an activ-low nabl pin which can intrfac with low voltag GPIO dirctly. Th switch is on whn EN is low and off whn EN is high. Th has an intgratd pull down rsistor at EN pin. DEVICE PIN OUT Fig Turn-Off Tim (V PA = 4.2 V, R L = 10, C L = 0.1 μf) Dvic pin out is dsignd for as of layout. SWITCH ON AND OFF PERFORMANCE Th has a slw rat control. This minimizs th inrush currnt and provids a soft turn on. /EN A1 A2 A3 A4 /EN Currnt B1 B2 B3 B4 C1 C2 C3 C4 GND GND Fig Turn-On Tim (V PA = 4.2 V, R L = 10, C L = 0.1 μf) Fig Proposd Layout maintains worldwid manufacturing capability. Products may b manufacturd at on of svral qualifid locations. Rliability data for Silicon Tchnology and Packag Rliability rprsnt a composit of all qualifid locations. For rlatd documnts such as packag / tap drawings, part marking, and rliability data, s S Rv. A, 03-Apr-17 6 Documnt Numbr: 78628
7 Packag Information WCSP12: 12 Bumps (3 x 4, 0.4 mm pitch, 208 μm bump hight, 1.71 mm x 1.31 mm di siz) Indx Bump A1 b FYWL ABCDE D A4 B4 C4 A3 B3 C3 A2 B2 C2 A1 B1 C1 s s E Top Viw s s Bottom Viw A1 Not 4 A1 A Not 3 Sid Viw Bump Not 2 RECOMMENDED LAND PATTERN (NSMD) MILLIMETERS (5) INCHES DIMENSION MIN. NOM. MAX. MIN. NOM. MAX. A A b s D E Nots (unlss othrwis spcifid) (1) Lasr mark on th silicon di back coatd with an poxy film. (2) Bumps ar SAC396. (3) max. co-planarity. (4) Laminat tap thicknss is mm. (5) Us millimtrs as th primary masurmnt. ECN: S Rv. B, 16-Dc-13 DWG: 6017 Rvision: 16-Dc-13 1 Documnt Numbr: 62592
8 Lgal Disclaimr Notic Vishay Disclaimr ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intrtchnology, Inc., its affiliats, agnts, and mploys, and all prsons acting on its or thir bhalf (collctivly, Vishay ), disclaim any and all liability for any rrors, inaccuracis or incompltnss containd in any datasht or in any othr disclosur rlating to any product. Vishay maks no warranty, rprsntation or guarant rgarding th suitability of th products for any particular purpos or th continuing production of any product. To th maximum xtnt prmittd by applicabl law, Vishay disclaims (i) any and all liability arising out of th application or us of any product, (ii) any and all liability, including without limitation spcial, consquntial or incidntal damags, and (iii) any and all implid warrantis, including warrantis of fitnss for particular purpos, non-infringmnt and mrchantability. Statmnts rgarding th suitability of products for crtain typs of applications ar basd on Vishay s knowldg of typical rquirmnts that ar oftn placd on Vishay products in gnric applications. Such statmnts ar not binding statmnts about th suitability of products for a particular application. It is th customr s rsponsibility to validat that a particular product with th proprtis dscribd in th product spcification is suitabl for us in a particular application. Paramtrs providd in datashts and / or spcifications may vary in diffrnt applications and prformanc may vary ovr tim. All oprating paramtrs, including typical paramtrs, must b validatd for ach customr application by th customr s tchnical xprts. Product spcifications do not xpand or othrwis modify Vishay s trms and conditions of purchas, including but not limitd to th warranty xprssd thrin. Excpt as xprssly indicatd in writing, Vishay products ar not dsignd for us in mdical, lif-saving, or lif-sustaining applications or for any othr application in which th failur of th Vishay product could rsult in prsonal injury or dath. Customrs using or slling Vishay products not xprssly indicatd for us in such applications do so at thir own risk. Plas contact authorizd Vishay prsonnl to obtain writtn trms and conditions rgarding products dsignd for such applications. No licns, xprss or implid, by stoppl or othrwis, to any intllctual proprty rights is grantd by this documnt or by any conduct of Vishay. Product nams and markings notd hrin may b tradmarks of thir rspctiv ownrs VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Rvision: 08-Fb-17 1 Documnt Numbr: 91000
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