Low Voltage PLL Clock Driver

Transcription

1 Freescale Semiconductor Technical ata Low Voltage PLL Clock river The is a 2.5 V and 3.3 V compatible, PLL-based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 2 and maximum output skews of 5 ps, the is ideal for the most demanding clock tree designs. The device offers 9 low skew clock outputs, with each one configurable to support the clocking needs of the various high-performance microprocessors, including the PowerQUICC II integrated communication microprocessor. The extended temperature range of the supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. Features 9 output LVCMOS PLL clock generator 25 2 output frequency range 2.5 V and 3.3 V compatible Compatible to various microprocessors such as PowerQuicc II Supports networking, telecommunications and computer applications Fully integrated PLL Configurable outputs: divide-by-2, 4 and 8 of VCO frequency Selectable output to input frequency ratio of 8:, 4:, 2: or : Oscillator or crystal reference inputs Internal PLL feedback Output disable PLL enable/disable Low skew characteristics: maximum 5 ps output-to-output 32-lead LQFP package 32-lead Pb-free Package Available Temperature range 4 C to +85 C LOW VOLTAGE 3.3 V AN 2.5 V PLL CLOCK GENERATOR FA SUFFIX 32-LEA LQFP PACKAGE CASE 873A-3 AC SUFFIX 32-LEA LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-3 Rev 6, 4/25 Functional escription The generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference clock signal. The internal PLL allows the to operate in frequency locked condition and to multiply the input reference clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable PLL feedback frequency ratios are available on the to provide input frequency range flexibility. The FBSEL pin selects between divide-by-6 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match the VCO frequency range. With the available feedback output dividers, the internal VCO of the is running at either 6x or 32x of the reference clock frequency. The frequency of the QA, QB, QC and Q outputs is either one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSEL pins, respectively. The available output to input frequency ratios are 6:, 8:, 4: and 2:. The REF_SEL pin selects the crystal oscillator input or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The is fully 2.5 V and 3.3 V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 5 Ω transmission lines. For series terminated transmission lines, each of the outputs can drive one or two traces giving the device an effective fanout of :8. The device is packaged in a 7x7 mm 2 32-lead LQFP package. Freescale Semiconductor, Inc., 25. All rights reserved.

2 XTAL XTAL2 TCLK REF_SEL Ref PLL Q QA FB Q QB FBSEL PLL_EN FSELA FSELB FSELC FSEL (Pullup) Q QC QC Q Q Q Q2 Q3 Q4 OE Figure. Logic iagram QC V CCO QC Q V CCO Q Q2 QB 26 5 V CCO V CCO 27 4 Q3 QA Q4 TCLK 3 V CCO PLL_EN 3 OE REF_SEL 32 9 XTAL V CCA FBSEL FSELA FSELB FSELC FSEL XTAL Figure 2. Pinout: 32-Lead Package Pinout (Top View) 2 Freescale Semiconductor

3 Table. Pin escription Number Name Type escription XTAL, XTAL2 Input Analog Crystal oscillator terminals TCLK Input LVCMOS Single ended reference clock signal or test clock FBSEL Input LVCMOS Selects feedback divider ratio REF_SEL Input LVCMOS Selects input reference source FSELA Input LVCMOS Output A divider selection FSELB Input LVCMOS Output B divider selection FSELC Input LVCMOS Outputs C divider selection FSEL Input LVCMOS Outputs divider selection OE Input LVCMOS Output enable/disable QA Output LVCMOS Bank A clock output QB Output LVCMOS Bank B clock output QC, QC Output LVCMOS Bank C clock outputs Q Q4 Output LVCMOS Bank clock outputs Supply Ground Negative power supply V CCA Supply V CC Positive power supply for the PLL V CC Supply V CC Positive power supply for I/O and core Table 2. Function Table Control efault REF_SEL Selects XTAL Selects TCLK PLL_EN Test mode with PLL disabled. The input clock is directly routed to the output dividers FBSEL Selects feedback divider 32 VCO = 32 * Input reference clock PLL enabled. The VCO output is routed to the output dividers Selects feedback divider 6 VCO = 6 * Input reference clock OE Outputs enabled Outputs disabled FSELA QA = VCO 2 QA = VCO 4 FSELB QB = VCO 4 QB = VCO 8 FSELC QC = VCO 4 QC = VCO 8 FSEL Q = VCO 4 Q = VCO 8 Table 3. Absolute Maximum Ratings () Symbol Characteristics Min Max Unit Condition V CC Supply Voltage V V IN C Input Voltage.3 V CC +.3 V V OUT C Output Voltage.3 V CC +.3 V I IN C Input Current ±2 ma I OUT C Output Current ±5 ma T S Storage temperature 4 25 C. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Freescale Semiconductor 3

4 Table 4. C Characteristics (V CC = 3.3 V ± 5%, T A = -4 to 85 C) Symbol Characteristics Min Typ Max Unit Condition V IH Input high voltage 2. V CC +.3 V LVCMOS V IL Input low voltage.3.8 V LVCMOS V OH Output High Voltage 2.4 V I OH = 24 ma () V OL Output Low Voltage The is capable of driving 5 Ω transmission lines on the incident edge. Each output drives one 5 Ω parallel terminated transmission line to a termination voltage of V TT. Alternatively, the device drives up to two 5 Ω series terminated transmission lines. V V I OL = 24 ma I OL = 2 ma I IN Input Current 2 µa V IN = V or V IN = V CC Z OUT Output impedance 4 7 Ω C IN Input capacitance 4. pf C P Power issipation Capacitance pf Per Output I CCA Maximum PLL Supply Current ma V CCA Pin I CC Maximum Quiescent Supply Current. ma All V CC Pins V TT Output termination voltage V CC 2 V Table 5. AC Characteristics (V CC = 3.3 V ± 5% or V CC = 2.5 V ± 5%, T A = -4 to 85 C) () f ref Symbol Characteristics Min Typ Max Unit Condition Input Frequency Static Test Mode 6 feedback 32 feedback AC characteristics apply for parallel output termination of 5Ω to V TT FBSEL = FBSEL = PLL_EN = f XTAL Crystal Oscillator Frequency 25 XTAL inputs f VCO VCO Frequency 2 4 PLL_EN = f MAX Maximum Output Frequency 2 output 4 output 8 output f refc Reference Input uty Cycle % t r, t f TLCK Input Rise/Fall Time V CC = 2.5 V V CC = 3.3 V t sk(o) Output-to-output Skew 45 5 ps ns ns.7 V to.7 V.8 V to 2. V t PW Output uty Cycle ps T=Clock period t r, t f Output Rise/Fall Time..5. ns see Figure t PLZ, HZ Output isable Time ns t PZL, LZ Output Enable Time ns BW PLL closed loop bandwidth 6 feedback (V CC = 3.3 V) 6 feedback (V CC = 2.5 V) 32 feedback (V CC = 3.3 V) 32 feedback (V CC = 2.5 V) t JIT(CC) Cycle-to-cycle jitter single frequency multiple frequencies t JIT(PER) Period Jitter 6 feedback 32 feedback t LOCK Maximum PLL Lock Time ms t JIT( ) I/O Phase Jitter (RMS) 5 2 ps RMS value ps ps ps ps 4 Freescale Semiconductor

5 Table 6. C Characteristics (V CC = 2.5 V ± 5%, T A = -4 to 85 C) Symbol Characteristics Min Typ Max Unit Condition V IH Input high voltage.7 V CC +.3 V LVCMOS V IL Input low voltage.3.7 V LVCMOS V OH Output High Voltage.8 V I OH = 5 ma () V OL Output Low Voltage.6 V I OL = 5 ma Z OUT Output impedance 7 2 Ω I IN Input Current 2 µa V IN = V or V IN = V CC C IN Input capacitance 4. pf C P Power issipation Capacitance pf Per Output I CCA Maximum PLL Supply Current ma V CCA Pin I CC Maximum Quiescent Supply Current. ma All V CC Pins V TT Output termination voltage V CC 2 V. The is capable of driving 5 Ω transmission lines on the incident edge. Each output drives one 5 Ω parallel terminated transmission line to a termination voltage of V TT. Alternatively, the device drives up to two 5 Ω series terminated transmission lines per output. Freescale Semiconductor 5

6 APPLICATIONS INFORMATION Programming the The clock driver outputs can be configured into several divider modes. In addition, the internal feedback of the device allows for flexibility in establishing two input to output frequency relationships. The output division settings establish the output frequency relationship. The output divider of the four output groups allows the user to configure the outputs into :, 2:, 4: and 4:2: frequency ratios. The use of even dividers ensures that the output duty cycle is always 5%. Table 7 and Table 8 illustrate the various output configurations. The tables describe the outputs using the input clock frequency CLK as a reference. In addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 25 to 2 while the VCO frequency range is specified from 2 to 4 and should not be exceeded for stable operation. Table 7. Output Frequency Relationship () FBSEL =, (VC = 32 * CLK) Inputs Outputs FSELA FSELB FSELC FSEL QA QB QC, QC Q Q4 6 * CLK 8 * CLK 8 * CLK 8 * CLK 6 * CLK 8 * CLK 8 * CLK 4 * CLK 6 * CLK 8 * CLK 4 * CLK 8 * CLK 6 * CLK 8 * CLK 4 * CLK 4 * CLK 6 * CLK 4 * CLK 8 * CLK 8 * CLK 6 * CLK 4 * CLK 8 * CLK 4 * CLK 6 * CLK 4 * CLK 4 * CLK 8 * CLK 6 * CLK 4 * CLK 4 * CLK 4 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 8 * CLK 4 * CLK 8 * CLK 8 * CLK 4 * CLK 8 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 8 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 8 * CLK 4 * CLK 4 * CLK 8 * CLK 8 * CLK 4 * CLK 4 * CLK 4 * CLK. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC935 data sheet for more input to output relationships in external feedback mode. Table 8. Output Frequency Relationship () FBSEL =, (VC = 6 * CLK) Inputs Outputs FSELA FSELB FSELC FSEL QA QB QC, QC Q Q4 8 * CLK 4 * CLK 4 * CLK 4 * CLK 8 * CLK 4 * CLK 4 * CLK 2 * CLK 8 * CLK 4 * CLK 2 * CLK 4 * CLK 8 * CLK 4 * CLK 2 * CLK 2 * CLK 8 * CLK 2 * CLK 4 * CLK 4 * CLK 8 * CLK 2 * CLK 4 * CLK 2 * CLK 8 * CLK 2 * CLK 2 * CLK 4 * CLK 8 * CLK 2 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 4 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 4 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 4 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 4 * CLK 2 * CLK 2 * CLK 4 * CLK 4 * CLK 2 * CLK 2 * CLK 2 * CLK. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC935 data sheet for more input to output relationships in external feedback mode. 6 Freescale Semiconductor

7 Power Supply Filtering The is a mixed analog/digital product and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The provides separate power supplies for the output buffers (V CCO ) and the phase-locked loop (V CCA ) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient; however, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the V CCA pin for the. Figure 3 illustrates a typical power supply filter scheme. The is most susceptible to noise with spectral content in the khz to 5 range; therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the C voltage drop that will be seen between the V CC supply and the V CCA pin of the. From the data sheet the I VCCA current (the current sourced through the V CCA pin) is typically ma (5 ma maximum), assuming that a minimum of 3. V must be maintained on the V CCA pin. Very little C voltage drop can be tolerated when a 3.3 V V CC supply is used. The resistor shown in Figure 3 must have a resistance of 5 Ω to meet the voltage drop criteria for V CC = 3.3 V. For V CC = 2.5 V operation, R S must be selected to maintain the minimum V CC specification of V for the PLL supply pin for proper operation. The RC filter pictured will provide a broadband filter with approximately : attenuation for noise whose spectral content is above 2 khz. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and, thus, increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8 Ω resistor to avoid potential V CC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. R S =5 5Ω 2.5V or 3.3V Although the has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. riving Transmission Lines The clock driver was designed to drive highspeed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 5 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale application note AN9. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 5 Ω resistance to V CC 2. This technique draws a fairly high level of C current, and thus, only a single terminated line can be driven by each output of the clock driver. For the series terminated case, however, there is no C current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the clock driver is effectively doubled due to its capability to drive multiple lines. IN IN Output Buffer 4Ω Output Buffer 4Ω R S = 36Ω R S = 36Ω R S = 36Ω Z O = 5Ω Z O = 5Ω Z O = 5Ω OutA OutB OutB V CCA.µF 22µF Figure 4. Single versus ual Transmission Lines V CC.µF Figure 3. Power Supply Filter The waveform plots in Figure 5 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the output buffer is more than sufficient to drive 5 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight Freescale Semiconductor 7

8 output-to-output skew of the. The output waveform in Figure 5 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: V L =V S (Z (R S +R +Z )) Z =5 Ω 5 Ω R S =36 Ω 36 Ω R =7 Ω V L = 3. (25 (8+7+25)) =.25 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment toward the quiescent 3. V in steps separated by one round trip delay (in this case 4. ns) OutA t = OutB t = Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. Output Buffer 4Ω R S = 22Ω R S = 22Ω Z O = 5Ω Z O = 5Ω 4Ω + 22Ω 22Ω = 5Ω 5Ω 25Ω = 25Ω Figure 6. Optimized ual Line Termination Voltage (V) 2..5 In Time (ns) Figure 5. Single versus ual Waveforms Pulse Generator Z = 5Ω Z O = 5Ω UT Z O = 5Ω R T = 5Ω R T = 5Ω V TT V TT Figure 7. TCLK AC Test Reference for V CC = 3.3 V and V CC = 2.5 V 8 Freescale Semiconductor

9 V CC V CC 2 V CC V CC 2 t SK(O) V CC V CC 2 t P T C = t P /T x % The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. Figure 8. Output-to-Output Skew t SK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 9. Output uty Cycle (C) V CC =3.3 V V CC =2.5 V V.55.6 V t F tr The time from the maximum low level voltage to minimum high level of a clock signal, expressed in ns. Figure. Transition Time Test Reference T N T JIT(CC) = T N T N+ T N+ The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. T T JIT(PER) = T N /f The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles. Figure. Cycle-to-Cycle Jitter Figure 2. Period Jitter Freescale Semiconductor 9

10 PACKAGE IMENSIONS PIN INEX / X.2 H A-B e/2 3 A, B, E/2 A B F 6 E E 4 ETAIL G 8 7 E/2 ETAIL G F 4X 7.2 C A-B H SEATING PLANE C 28X e 9 /2 4 ETAIL A 32X. C PLATING BASE METAL b NOTES:. IMENSIONS ARE IN MILLIMETERS. 2. INTERPRET IMENSIONS AN TOLERANCES PER ASME Y4.5M, ATUMS A, B, AN TO BE ETERMINE AT ATUM PLANE H. 4. IMENSIONS AN E TO BE ETERMINE AT SEATING PLANE C. 5. IMENSION b OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL NOT CAUSE THE LEA WITH TO EXCEE THE MAXIMUM b IMENSION BY MORE THAN.8-mm. AMBAR CANNOT BE LOCATE ON THE LOWER RAIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AN AJACENT LEA OR PROTRUSION:.7-mm. 6. IMENSIONS AN E O NOT INCLUE MOL PROTRUSION. ALLOWABLE PROTRUSION IS.25-mm PER SIE. AN E ARE MAXIMUM PLASTIC BOY SIZE IMENSIONS INCLUING MOL MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE IMENSIONS APPLY TO THE FLAT SECTION OF THE LEA BETWEEN.-mm AN.25-mm FROM THE LEA TIP. A A2 A (S) 8X (θ ) (L) L ETAIL A R R2 R R.25 θ c GAUGE PLANE b SECTION F-F c.2 M C A-B 5 8 MILLIMETERS IM MIN MAX A.4.6 A.5.5 A b.3.45 b.3.4 c.9.2 c.9.6 e E E 9. BSC 7. BSC.8 BSC 9. BSC 7. BSC L.5.7 L. REF q q 7 2 REF R.8.2 R S.2 REF CASE 873A-3 ISSUE B 32-LEA LQFP PACKAGE Freescale Semiconductor

11 NOTES Freescale Semiconductor

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