MPC8260 UPM Timing Diagram

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1 Freescale Semiconductor Application Note Document Number: AN2179 Rev. 2, 07/2006 MPC8260 UPM Timing Diagram The three user-programmable machine (UPMs) of the MPC8260 PowerQUICC II integrated communications processor are flexible interfaces that connect to a wide range of memory devices. At the heart of each UPM is an internal-memory RAM array that specifies the logical value driven on the external memory controller pins for a given clock cycle. This application note presents a series of timing diagrams for several UPM usage scenarios. All the timing diagrams are based on simulations and are for the 60x bus. Timing for the local bus is basically the same as for the 60x bus, except that there are no and TA signals to indicate the termination of the memory cycle. Also, the local bus has its own signals: Local ess bus Local data bus L LGPLx Local ess pins are multiplexed with PCI signals. To select the local bus function of these pins, configure the HRCW[L2CPC] bits to 00 during configuration or program them to 00 after configuration. Because of the similarity of the timing for the 60x and local buses, refer to the 60x bus timing diagrams for local bus timings. Contents 1 UPM Programming UPM Timings UPM ARTRY Cycle UPM Read-Modify-Write Cycle Freescale Semiconductor, Inc., 1999, All rights reserved.

2 UPM Programming 1 UPM Programming The basic steps to program the UPMs are as follows: 1. Set up BRx and ORx. 2. Configure MxMR[OP] = 01 for writing to a RAM array. 3. Write patterns to the RAM array by accessing the UPM with a single-byte transaction. 4. Program MPTPR and L/PSRT if refresh is required. 5. Configure MxMR[OP] = 00 for normal operation. Example 1 shows the detailed assembly code for completing these general steps. Example 1. Assembly Language # Set up OR1 addis r2,r0,0xffff r2,r2,0x0820 r1,r1,0x010c # Set up BR1 r2,r2,0x1881 r1,r1,0x0108 # MAMR OP = 01 for write RAM code starting at ess 00 (READ Routine) addis r2,r0,0x1000 r2,r2,0x8000 r1,r1,0x0170 # MDR addis r2,r0,0x08ea r2,r2,0xa800 2 Freescale Semiconductor

3 UPM Programming r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 00 stb r1, 0x0008(r2) # MDR addis r2,r0,0x00a0 r2,r2,0xa800 r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 01 stb r1, 0x0008(r2) # MDR addis r2,r0,0x00a0 r2,r2,0xa800 r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 02 stb r1, 0x0008(r2) # MDR addis r2,r0,0x00a0 r2,r2,0xa800 r1,r1,0x0188 Freescale Semiconductor 3

4 UPM Programming # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 03 stb r1, 0x0008(r2) # MDR addis r2,r0,0x00a0 r2,r2,0xa800 r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 04 stb r1, 0x0008(r2) # MDR addis r2,r0,0x01b5 r2,r2,0x4405 r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 05 stb r1, 0x0008(r2) # MAMR OP = 01 for write RAM code starting at ess 18 (WRITE Routine) addis r2,r0,0x1000 r2,r2,0x8018 r1,r1,0x Freescale Semiconductor

5 UPM Programming # MDR addis r2,r0,0x8000 r2,r2,0xa800 r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 18 stb r1, 0x0008(r2) # MDR addis r2,r0,0x1000 r2,r2,0x0005 r1,r1,0x0188 # Single byte hit (stb) of 0x0100_0008 to write MDR to RAM array 19 stb r1, 0x0008(r2) # MAMR OP = 00 for normal operation addis r2,r0,0x0000 r1,r1,0x0170 #Access to memory controlled by UPM lwz r3, 0x0018(r2) r1, 0x0018(r2) Freescale Semiconductor 5

6 UPM Timings 2 UPM Timings Figure 1 shows a 32-bit single beat read/write on a 32-bit port. D0 TS ALE AACK ABB DBB TA Notes: 1 RAM word for a single-beat read (a single-beat write starts at RAM ess 0x18) 00: 08ea a800 03: 00a : 00a : 00a : 00a : 01b Data bus end at for both a single-beat read and write. For a write, the data bus starts when DBB is asserted. For a read, the starting-point depends on the RAM pattern and the memory UPM controls. Figure Bit Single Beat Read/Write on 32-Bit Port 6 Freescale Semiconductor

7 UPM Timings Figure 2 shows a 32-bit single beat read/write on a 16-bit port. D0 D1 TS ALE AACK ABB DBB TA B + 2 Notes: 1 RAM code is the same as for Figure 1. 2 The single-beat 32-bit access is split to two 16-bit back-to-back accesses due to port size limitations. Figure Bit Single Beat Read/Write on 16-Bit Port Freescale Semiconductor 7

8 UPM Timings Figure 3 shows a 32-bit single-beat read/write on a 32-bit port. D0 TS ALE AACK ABB DBB TA LOOP Note: 1 RAM word for single beat read with LOOP: 00: 08ea a800 03: 00a : 00a : 00a //LOOP=1 02: 00a //LOOP=1 05: 01b Loop number is set at MxMR. RLFx for read, WLFx for write. Loop number is one for the above figure. Figure 3. UPM with LOOP, 32-Bit Single Beat Read/Write on 32-Bit Port 8 Freescale Semiconductor

9 UPM Timings Figure 4 shows the UPM with REDO. D0 TS ALE AACK ABB DBB TA REDO Note: 1 The RAM word for a single-beat read with REDO: 00: 08ea a800 03: 00a : 00a // REDO=3 04: 00a : 00a : 01b Figure 4. UPM with REDO Freescale Semiconductor 9

10 UPM Timings Figure 5 shows the UPM with two consecutive WAEN. D0 UPWAIT internal UPWAIT Note: 1 Minimum RAM words for UPWAIT to take effect: 00: 08ea a800 01: 00a : 00a // WAEN=1 03: 00a // WAEN=1 04: 01b WAEN needs to be set in two consecutive RAM words. The UPM waits at the second RAM word. Figure 6 shows what happens if only one WAEN is set. 3 Due to synchronization of UPWAIT, the internal UPWAIT is two cycles later than external UPWAIT. If the external UPWAIT goes active half a cycle after is active, the first WAEN that has an effect is at RAM ess 02 for a read. Even if WAEN values of 00 and 01 are configured, the UPM does not wait because UPWAIT has not arrived yet due to delay. Figure 5. UPM with Two Consecutive WAEN 10 Freescale Semiconductor

11 UPM Timings Figure 6 shows the UPM with UPWAIT and one WAEN. D0 UPWAIT internal UPWAIT Note: 1 RAM words with one WAEN 00: 08ea a800 01: 00a : 00a //WAEN=1 03: 00a : 01b Setting WAEN at RAM ess 02 causes a single-cycle wait at pattern 03. If UPAWIT is negated, of course the UPM does not wait. However, even if UPWAIT is asserted, a single WAEN causes a wait of only one cycle for next the RAM pattern. Then it proceeds while ignng the UPWAIT. That is why two consecutive WAENs are needed for a continuous UPWAIT. Figure 6. UPM with UPWAIT, One WAEN Freescale Semiconductor 11

12 UPM ARTRY Cycle Figure 7 shows the UPM burst read/write on a 64-bit port. D0 D1 D2 D3 TA a 0b 0c 0d Note: 1 Example RAM words for burst read: 08: 08ea a800 09: 00a // UTA=1 0a: 00a // UTA=1 0b: 00a // UTA=1 0c: 00a // UTA=1 0d: 01b A burst write starts at RAM ess 0x20 3 Care should be taken to program the correct number of UTAs in the burst code so that the UPM generates the required number of PSDAL signals for a burst. 3 UPM ARTRY Cycle Figure 7. UPM Burst Read/Write on 64-Bit Port In 60x-compatible mode, the ess transfer can be terminated with the requirement to retry if ARTRY is asserted during the ess tenure and through the cycle following AACK. The assertion causes the entire transaction (ess and data tenure) to be rerun. 12 Freescale Semiconductor

13 UPM ARTRY Cycle Figure 8 shows the UPM ARTRY cycle. (retry) aborted data TS ALE AACK ARTRY ABB DBB TA Note: 1 RAM word for ARTRY cycle: 00: 08ea a800 03: 00a : 00a : 00a : 00a : 01b When a valid ARTRY is recognized, the UPM finishes running the current RAM pattern without asserting and TA. After that, a retry phase starts. Figure 8. UPM ARTRY Cycle Freescale Semiconductor 13

14 UPM Read-Modify-Write Cycle 4 UPM Read-Modify-Write Cycle If the UPM is programmed for read-modify-write parity checking or ECC correction and checking, every write access to memory that is less than the port size automatically causes a read-modify-write cycle. The following is an example of RAM code: Read Pattern: 00: 08ea a800 01: 00a : 00a : 00a : 00a : 01b Write Pattern: 18: : Freescale Semiconductor

15 Figure 9 shows a 32-bit write to a 64-bit port to trigger the read-modify-write cycle. UPM Read-Modify-Write Cycle Read Data Write Data TS ALE AACK ABB DBB TA READ WRITE Figure 9. UPM with Read-Modify-Write Cycle Freescale Semiconductor 15

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